MD51V64400-60
更新时间：2024-09-18 06:07:29
品牌：OKI
描述：16,777,216-Word X 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
概述
数据手册MD51V64400-60 概述
16,777,216-Word X 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE 16777216字×4位动态RAM ：快速页面模式类型
MD51V64400-60 数据手册
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PDF下载E2G0135-18-11
This version: Mar. 1998
¡ Semiconductor
MD51V64400
16,777,216-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MD51V64400 is a 16,777,216-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MD51V64400 achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer
metal CMOS process. The MD51V64400 is available in a 32-pin plastic SOJ or 32-pin plastic TSOP.
FEATURES
• 16,777,216-word ¥ 4-bit configuration
• Single 3.3 V power supply, ±0.3 V tolerance
• Input
: LVTTL compatible, low input capacitance
• Output : LVTTL compatible, 3-state
• Refresh :
RAS-only refresh
: 8192 cycles/64 ms
: 4096 cycles/64 ms
CAS before RAS refresh, hidden refresh
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Package options:
32-pin 400 mil plastic SOJ
32-pin 400 mil plastic TSOP
(SOJ32-P-400-1.27)
(TSOPII32-P-400-1.27-K) (Product : MD51V64400-xxTA)
(Product : MD51V64400-xxJA)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Cycle Time
(Min.)
Power Dissipation
Family
tRAC tAA tCAC tOEA
50 ns 25 ns 13 ns 13 ns
60 ns 30 ns 15 ns 15 ns
Standby (Max.)
Operating (Max.)
MD51V64400-50
MD51V64400-60
90 ns
504 mW
432 mW
1.8 mW
110 ns
1/15
¡ Semiconductor
MD51V64400
PIN CONFIGURATION (TOP VIEW)
VCC
1
32 VSS
31 DQ4
30 DQ3
29 NC
28 NC
27 NC
26 CAS
25 OE
VCC
1
32 VSS
31 DQ4
30 DQ3
29 NC
28 NC
27 NC
26 CAS
25 OE
DQ1 2
DQ2 3
NC 4
NC 5
NC 6
NC 7
WE 8
RAS 9
A0 10
A1 11
A2 12
A3 13
A4 14
A5 15
VCC 16
DQ1 2
DQ2 3
NC 4
NC 5
NC 6
NC 7
WE 8
24 A12R RAS 9
24 A12R
23 A11R
22 A10
21 A9
23 A11R
22 A10
21 A9
A0 10
A1 11
A2 12
A3 13
A4 14
A5 15
VCC 16
20 A8
20 A8
19 A7
19 A7
18 A6
18 A6
17 VSS
17 VSS
32-Pin Plastic SOJ
32-Pin Plastic TSOP
(K Type)
Pin Name
A0 - A10,
A11R, A12R
RAS
Function
Address Input
Row Address Strobe
Column Address Strobe
Data Input/Data Output
Output Enable
CAS
DQ1 - DQ4
OE
WE
Write Enable
VCC
Power Supply (3.3 V)
Ground (0 V)
VSS
NC
No Connection
Note :
The same power supply voltage must be provided to every V pin, and the same GND
CC
voltage level must be provided to every V pin.
SS
2/15
¡ Semiconductor
MD51V64400
BLOCK DIAGRAM
WE
OE
Timing
Generator
RAS
I/O
Controller
Output
Buffers
4
4
4
CAS
DQ1 - DQ4
Column
Address
Buffers
Input
Buffers
Column Decoders
11
11
4
I/O
Selector
Internal
Address
Counter
Sense Amplifiers
4
4
Refresh
Control Clock
A0 - A10
11
2
Row
Address
Buffers
Row
Memory
Cells
13
Deco-
Word
Drivers
ders
A11R, A12R
VCC
On Chip
V
Generator
BB
On Chip
IV Generator
CC
VSS
3/15
¡ Semiconductor
MD51V64400
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VT
Rating
–0.5 to 4.6
50
Unit
V
IOS
mA
W
PD
*
1
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Symbol
VCC
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Unit
V
V
V
V
VSS
0
Input High Voltage
Input Low Voltage
VIH
2.0
–0.3
—
VCC + 0.3
0.8
VIL
—
Capacitance
(VCC = 3.3 V 0.3 V, Ta = 25°C, f = 1 MHꢀ)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance
(A0 - A10, A11R, A12R)
CIN1
—
5
pF
Input Capacitance (RAS, CAS, WE, OE)
CIN2
CI/O
—
—
7
7
pF
pF
Output Capacitance (DQ1 - DQ4)
4/15
¡ Semiconductor
MD51V64400
DC Characteristics
(VCC = 3.3 V 0.3 V, Ta = 0°C to 70°C)
MD51V64400
-50
MD51V64400
-60
Parameter
Symbol
Condition
Unit Note
Min.
2.4
0
Max.
Min.
2.4
0
Max.
VCC
Output High Voltage
Output Low Voltage
VOH IOH = –2.0 mA
VOL IOL = 2.0 mA
0 V £ VI £ VCC + 0.3 V;
ILI All other pins not
under test = 0 V
VCC
0.4
V
V
0.4
Input Leakage Current
–10
–10
—
10
10
–10
–10
—
10
10
90
mA
DQ disable
Output Leakage Current ILO
Average Power
mA
0 V £ VO £ VCC
RAS, CAS cycling,
Supply Current
(Operating)
ICC1
100
mA 1, 2
tRC = Min.
RAS, CAS = VIH
—
—
1
—
—
1
Power Supply
ICC2 RAS, CAS
≥ VCC –0.2 V
RAS cycling,
ICC3 CAS = VIH,
tRC = Min.
mA
1
Current (Standby)
0.5
0.5
Average Power
Supply Current
—
—
—
—
100
5
—
—
—
—
90
5
mA 1, 2
(RAS-only Refresh)
RAS = VIH,
Power Supply
ICC5 CAS = VIL,
DQ = enable
mA
1
Current (Standby)
Average Power
RAS cycling,
ICC6
Supply Current
140
80
120
70
mA 1, 2
mA 1, 3
CAS before RAS
(CAS before RAS Refresh)
Average Power
RAS = VIL,
Supply Current
ICC7 CAS cycling,
(Fast Page Mode)
tPC = Min.
Notes : 1. I Max. is specified as I for output open condition.
CC
CC
2. The address can be changed once or less while RAS = V .
IL
3. The address can be changed once or less while CAS = V
.
IH
5/15
¡ Semiconductor
MD51V64400
AC Characteristics (1/2)
(VCC = 3.3 V 0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3
MD51V64400
-50
MD51V64400
-60
Parameter
Symbol
Unit Note
Min.
90
Max.
—
Min.
110
155
40
Max.
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
tRC
tRWC
tPC
—
—
—
ns
ns
ns
131
35
—
—
Fast Page Mode Read Modify Write
Cycle Time
tPRWC
76
—
85
—
ns
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precharge
tRAC
tCAC
tAA
—
—
—
—
50
13
25
30
—
—
—
—
60
15
30
35
ns 4, 5, 6
ns
ns
ns
4, 5
4, 6
4
tCPA
Access Time from OE
Output Low Impedance Time from CAS
tOEA
tCLZ
—
0
13
—
—
0
15
—
ns
ns
ns
ns
ns
ms
ns
ns
4
4
7
7
3
CAS to Data Output Buffer Turn-off Delay Time tOFF
OE to Data Output Buffer Turn-off Delay Time
Transition Time
0
13
0
15
tOEZ
tT
tREF
tRP
0
3
—
30
50
13
50
64
0
3
—
40
60
15
50
64
Refresh Period
RAS Precharge Time
RAS Pulse Width
—
—
tRAS
10,000
10,000
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
RAS Hold Time referenced to OE
CAS Precharge Time (Fast Page Mode)
CAS Pulse Width
tRASP
tRSH
tROH
tCP
50
13
13
7
100,000
—
60
15
15
10
15
60
5
100,000
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
tCAS
tCSH
tCRP
tRHCP
tRCD
tRAD
tASR
tRAH
tASC
13
50
5
10,000
—
10,000
—
CAS Hold Time
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
—
—
30
17
12
0
—
35
20
15
0
—
37
45
5
6
25
30
—
—
7
—
10
0
—
Column Address Set-up Time
0
—
—
Column Address Hold Time
Column Address to RAS Lead Time
tCAH
tRAL
7
25
—
—
10
30
—
—
ns
ns
Read Command Set-up Time
tRCS
0
—
0
—
ns
Read Command Hold Time
Read Command Hold Time referenced to RAS
tRCH
tRRH
0
0
—
—
—
—
ns
ns
8
8
0
0
6/15
¡ Semiconductor
MD51V64400
AC Characteristics (2/2)
(VCC = 3.3 V 0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3
MD51V64400
-50
MD51V64400
-60
Parameter
Symbol
Unit Note
Min.
Max.
Min.
Max.
Write Command Set-up Time
Write Command Hold Time
tWCS
tWCH
tWP
0
7
—
—
—
—
—
—
0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
9
10
10
15
15
15
Write Command Pulse Width
OE Command Hold Time
7
tOEH
tRWL
tCWL
13
13
13
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
tDS
tDH
0
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
Data-in Hold Time
7
10
15
40
55
85
60
5
OE to Data-in Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
RAS to WE Delay Time
tOED
tCWD
tAWD
tRWD
tCPWD
tRPC
13
36
48
73
53
5
9
9
9
9
CAS Precharge WE Delay Time
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS) tCSR
RAS to CAS Hold Time (CAS before RAS) tCHR
WE to RAS Precharge Time (CAS before RAS) tWRP
WE Hold Time from RAS (CAS before RAS) tWRH
10
10
10
10
10
10
10
10
7/15
¡ Semiconductor
MD51V64400
Notes: 1. Astart-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume t = 5 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.
IH
IL
Transition times (t ) are measured between V and V .
T
IH
IL
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.
The output timing reference levels are V = 2.0 V and V = 0.8 V.
OH
OL
5. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
is greater than the specified
RCD
RAC
t
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
RCD
RCD
RCD
.
CAC
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RAC
is greater than the specified
RAD
t
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
RAD
RAD
RAD
.
AA
7. t
(Max.) and t
(Max.) define the time at which the output achieves the open
OEZ
OFF
circuit condition and are not referenced to output voltage levels.
8. t
9. t
or t
must be satisfied for a read cycle.
RRH
RCH
, t
, t
, t
and t
are not restrictive operating parameters. They are
WCS CWD RWD AWD
CPWD
included in the data sheet as electrical characteristics only. If t
≥t
(Min.), then
WCS WCS
the cycle is an early write cycle and the data out will remain open circuit (high
impedance)throughouttheentirecycle. Ift ≥t (Min.), t ≥t (Min.),
CWD CWD
RWD RWD
t
≥t
(Min.) and t
≥t
(Min.), then the cycle is a read modify write
AWD AWD
CPWD CPWD
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
8/15
E2G0114-17-41R
¡ Semiconductor
MD51V64400
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
tCRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
CAS
tRAD
tASC
tASR
Row
tRAH
tRAL
tCAH
Column
VIH
VIL
–
–
Address
tRCH
tRCS
tRRH
VIH
VIL
–
–
tAA
WE
OE
tROH
tOEA
VIH
VIL
–
–
tOFF
tCAC
tRAC
tOEZ
VOH
VOL
–
–
DQ
Open
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
VIH
VIL
–
–
tCRP
RAS
CAS
tCSH
tCRP
tRCD
tRAD
tRAH
tASC
tRSH
tCAS
VIH
VIL
–
–
tRAL
tASR
Row
tCAH
Column
tWCH
VIH
VIL
–
–
Address
tWCS
tCWL
VIH
VIL
–
–
tWP
WE
tRWL
VIH
VIL
–
–
OE
tDS
tDH
VIH
VIL
–
–
DQ
Open
Valid Data-in
"H" or "L"
9/15
¡ Semiconductor
MD51V64400
Read Modify Write Cycle
tRWC
tRAS
tRP
VIH
VIL
–
–
RAS
CAS
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
tRAH
tASC
tASR
tCAH
Column
VIH
VIL
–
–
Row
Address
tCWL
tRWL
tWP
tCWD
tAWD
tRAD
tRWD
tOEA
VIH
VIL
–
–
tAA
WE
OE
tRCS
VIH
VIL
–
–
tOED
tOEZ
tOEH
tDH
tCAC
tDS
tRAC
VI/OH
–
Valid
Data-out
Valid
Data-in
DQ
–
tCLZ
VI/OL
"H" or "L"
10/15
¡ Semiconductor
MD51V64400
Fast Page Mode Read Cycle
tRASP
tRP
tRHCP
VIH
VIL
–
–
RAS
CAS
tCRP
tPC
tRSH
tCRP
tRCD
tRAD
tRAH tASC
tCP
tCP
tCAS
tCAS
tCAS
tRAL
VIH
VIL
–
–
tCSH
tCAH
tASR
Row
tASC
tCAH
tASC tCAH
VIH
VIL
–
–
Column
Column
Column
tRCS
Address
tRCH
tRCS
tRCS
tRCH
tRCH
VIH
VIL
–
–
WE
tAA
tAA
tAA
tRRH
tCPA
tCPA
tOEA
tOEA
tOEA
VIH
VIL
–
–
OE
tOFF
tOEZ
tOFF
tOEZ
tCAC
tCLZ
tCAC
tCLZ
tOFF
tCAC
tRAC
tOEZ
VOH
VOL
–
–
Valid
Data-out
Valid
Data-out
Valid
Data-out
DQ
tCLZ
"H" or "L"
Fast Page Mode Write Cycle (Early Write)
tRASP
tPC
tRP
tCRP
tRHCP
VIH
VIL
–
–
RAS
CAS
tRSH
tCAS
tRAL
tCRP
tRCD
tCP
tCP
tCAS
tCAS
tCAH
Column
VIH
VIL
–
–
tCSH
tCAH
tASR
Row
tASC
tASC
tASC
tRAH
tCAH
VIH
VIL
–
–
Column
tCWL
tWCH
tWP
Column
Address
tRAD
tWCS
tCWL
tWCH
tWP
tRWL
tCWL
tWCH
tWP
tWCS
tWCS
VIH
VIL
–
–
WE
tDS
tDS
tDS
tDH
tDH
tDH
VIH
VIL
–
–
Valid
Data-in
Valid
Data-in
Valid Data-in
DQ
Note: OE = "H" or "L"
"H" or "L"
11/15
¡ Semiconductor
MD51V64400
Fast Page Mode Read Modify Write Cycle
tRASP
VIH
VIL
–
–
RAS
CAS
tRP
tCSH
tPRWC
tCAS
tRSH
tCAS
tCRP
tCP
tCP
tRCD
tRAD
tRAH
tCAS
VIH
VIL
–
–
tASC
tCAH
tASC
tRAL
tCAH
tCAH
tASR
tASC
VIH
VIL
–
–
Column
tRWD
Column
tRCS
Column
Address
Row
tRCS
tCPWD
tCPWD
tCWD
tRWL
tCWL
tCWD
tCWD
tRCS
tCWL
tCWL
VIH
VIL
–
–
WE
tAWD
tAWD
tAWD
tROH
tWP
tWP
tDH
tWP
tDH
tDH
tDS
tDS
tDS
tRAC
tCPA
tAA
tCPA
tAA
tAA
tOEA
tOEA
tOEA
tOED
tOED
tOED
VIH
VIL
–
–
OE
tOEZ
tOEZ
tOEZ
tCAC
tCAC
tCAC
VI/OH
–
DQ
Out
In
Out
In
Out
In
–
VI/OL
tCLZ
tCLZ
tCLZ
"H" or "L"
RAS-Only Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tCRP
tRPC
VIH
VIL
–
–
tASR tRAH
VIH
VIL
–
–
Address
DQ
Row
tOFF
VOH
VOL
–
–
Open
Note: WE, OE = "H" or "L"
"H" or "L"
12/15
¡ Semiconductor
MD51V64400
CAS before RAS Refresh Cycle
tRC
tRP
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tRPC
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
tWRP
tWRP
tWRH
VIH
VIL
–
–
WE
tOFF
VOH
VOL
DQ
–
–
Open
Note: OE, Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRAS
tRP
tRP
VIH
VIL
–
–
RAS
tCRP
tRSH
tRCD
tCHR
VIH
VIL
–
–
tRAD
tASC
tRAH
CAS
tCAH
tASR
VIH
VIL
–
–
Address
Row
Column
tRRH
tRCS
tRAL
VIH
VIL
–
–
tAA
WE
OE
tROH
tWRP
tWRH
tOEA
VIH
VIL
–
–
tCAC
tCLZ
tOFF
tRAC
tOEZ
VOH
VOL
–
–
DQ
Valid Data-out
"H" or "L"
13/15
¡ Semiconductor
MD51V64400
Hidden Refresh Write Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
VIH
VIL
–
–
RAS
tCRP
tRSH
tRCD
tCHR
VIH
VIL
–
–
tRAD
tASC
tRAH
CAS
tCAH
tASR
tRAL
VIH
VIL
–
–
Address
Column
Row
tWCS
tWCH
tWP
VIH
VIL
–
–
WE
tWRP
tWRH
VIH
VIL
–
–
OE
tDS
tDH
Valid Data-in
VIH
VIL
–
–
DQ
"H" or "L"
14/15
¡ Semiconductor
PACKAGE DIMENSIONS
SOJ32-P-400-1.27
MD51V64400
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.42 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
15/15
MD51V64400-60 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MD51V64405 | OKI | 16,777,216-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO | 获取价格 |
|
| MD51V64405-50JA | OKI | Fast Page DRAM, 16MX4, 50ns, CMOS, PDSO32, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-32 | 获取价格 |
|
| MD51V64405-60JA | OKI | Fast Page DRAM, 16MX4, 60ns, CMOS, PDSO32, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-32 | 获取价格 |
|
| MD51V64405-60TA | OKI | Fast Page DRAM, 16MX4, 60ns, CMOS, PDSO32, 0.400 INCH, 1.27 MM PITCH, PLASTIC, TSOP2-32 | 获取价格 |
|
| MD51V64405E-50JA | OKI | Fast Page DRAM, 16MX4, 25ns, CMOS, PDSO32, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOP-32 | 获取价格 |
|
| MD51V64405E-50TA | OKI | Fast Page DRAM, 16MX4, 25ns, CMOS, PDSO32, 0.400 INCH, 1.27 MM PITCH, PLASTIC, TSOP2-32 | 获取价格 |
|
| MD51V64405E-60JA | OKI | Fast Page DRAM, 16MX4, 30ns, CMOS, PDSO32, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOP-32 | 获取价格 |
|
| MD51V64405E-60TA | OKI | Fast Page DRAM, 16MX4, 30ns, CMOS, PDSO32, 0.400 INCH, 1.27 MM PITCH, PLASTIC, TSOP2-32 | 获取价格 |
|
| MD51V65165 | OKI | 4,194,304-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO | 获取价格 |
|
| MD51V65165-50JA | OKI | Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, PLASTIC, SOJ-50 | 获取价格 |
|
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