MD56V62160 [OKI]
4-Bank x 1,048,576-Word x 16-Bit SYNCHRONOUS DYNAMIC RAM; 4 - X银行1,048,576字×16位的同步动态RAM
| 型号： | MD56V62160 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 4-Bank x 1,048,576-Word x 16-Bit SYNCHRONOUS DYNAMIC RAM |
| 文件： | 总28页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2G1052-17-X1
Preliminary
This version: Mar. 1998
¡ Semiconductor
MD56V62160/H
4-Bank ¥ 1,048,576-Word ¥ 16-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MD56V62160/H is a 4-bank ¥ 1,048,576-word ¥ 16-bit synchronous dynamic RAM,
fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs
and outputs are LVTTL compatible.
FEATURES
• Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
• 4-bank ¥ 1,048,576-word ¥ 16-bit configuration
• 3.3 V power supply, ±0.3 V tolerance
• Input
: LVTTL compatible
• Output : LVTTL compatible
• Refresh : 4096 cycles/64 ms
• Programmable data transfer mode
– CAS latency (2, 3)
– Burst length (2, 4, 8)
– Data scramble (sequential, interleave)
• CBR auto-refresh, Self-refresh capability
• Package:
54-pin 400 mil plastic TSOP (Type II) (TSOPII54-P-400-0.80-K) (Product : MD56V62160/H-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Max.
Frequency
Family
tAC2
9 ns
tAC3
9 ns
MD56V62160-10
MD56V62160-12
MD56V62160H-15
100 MHz
83 MHz
66 MHz
14 ns
9 ns
10 ns
9 ns
1/28
¡ Semiconductor
MD56V62160/H
PIN CONFIGURATION (TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
54 VSS
DQ1
53 DQ16
VCCQ
52 VSSQ
DQ2
DQ3
51 DQ15
50 DQ14
VSSQ
49 VCCQ
DQ4
DQ5
48 DQ13
47 DQ12
VCCQ
46 VSSQ
DQ6 10
DQ7 11
45 DQ11
44 DQ10
VSSQ
12
43 VCCQ
DQ8 13
VCC 14
42 DQ9
41 VSS
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
LDQM 15
WE 16
CAS 17
RAS 18
CS 19
A13/BA0 20
A12/BA1 21
A10 22
A0 23
33 A8
32 A7
A1 24
31 A6
A2 25
30 A5
A3 26
29 A4
VCC 27
28 VSS
54-Pin Plastic TSOP (II)
(K Type)
Pin Name
CLK
Function
Pin Name
Function
System Clock
UDQM, LDQM Data Input/Output Mask
CS
Chip Select
DQi
VCC
VSS
VCC
Data Input/Output
CKE
Clock Enable
Power Supply (3.3 V)
Ground (0 V)
A0 - A11
A12, A13
RAS
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Q
Data Output Power Supply (3.3 V)
Data Output Ground (0 V)
No Connection
VSSQ
CAS
NC
WE
Note:
The same power supply voltage must be provided to every V pin and V Q pin.
CC CC
The same GND voltage level must be provided to every V pin and V Q pin.
SS
SS
2/28
¡ Semiconductor
MD56V62160/H
PIN DESCRIPTION
CLK
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
CS
UDQM and LDQM.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Address
Row address: RA0 – RA11
Column address: CA0 – CA7
A12, A13
(BA1, BA0)
RAS
Bank Access pins. These pins are dedicated to select one of 4 banks.
CAS
Functionality depends on the combination. For details, see the function truth table.
WE
UDQM,
LDQM
Masks the read data of two clocks later when UDQM and LDQM are set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when UDQM and LDQM are set "H" at the "H" edge of the clock signal.
UDQM controls upper byte and LDQM controls lower byte.
DQi
Data inputs/outputs are multiplexed on the same pin.
3/28
¡ Semiconductor
MD56V62160/H
BLOCK DIAGRAM
CLK
CKE
CLOCK
BUFFER
Row
Address
Latches
& Refresh
Counter
Command
Decoding
Logic
CS
RAS
CAS
WE
Command
Buffers
Row Decoders
Control
Logic
Word Drivers
UDQM
LDQM
Column
Address
Latches
& Counter
Memory
Cells
Latency
& Burst
controller
Mode
Register
Address
Buffers
A0 -
A13
BANK A
BANK B
BANK C
BANK D
Input
Data
Register
Input
Buffers
DQ1 - DQ16
Output
Data
Register
Output
Buffers
4/28
¡ Semiconductor
MD56V62160/H
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voltages referenced to VSS
)
Parameter
Symbol
Rating
–0.5 to VCC + 0.5
–0.5 to 4.6
–55 to 150
1
Unit
V
Voltage on Any Pin Relative to VSS
VIN, VOUT
V
CC Supply Voltage
VCC, VCC
Tstg
Q
V
Storage Temperature
Power Dissipation
°C
W
PD*
Short Circuit Current
Operating Temperature
IOS
50
mA
°C
Topr
0 to 70
*: Ta = 25°C
Recommended Operating Conditions
(Voltages referenced to VSS = 0 V)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
Min.
3.0
Typ.
3.3
—
Max.
3.6
Unit
VCC, VCC
VIH
Q
V
V
V
2.0
V
CC + 0.3
VIL
–0.3
—
0.8
Capacitance
(VCC = 3.3 V 0.3 V, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Min.
Max.
Unit
Input Capacitance (A0 - A13)
Input Capacitance (CLK, CKE, CS,
RAS, CAS, WE, UDQM, LDQM)
Input/Output Capacitance
(DQ1 - DQ16)
CIN1
2
5
pF
CIN2
2
5
7
pF
pF
COUT
2
5/28
¡ Semiconductor
MD56V62160/H
DC Characteristics
Condition
Version
-12
Min. Max.Min. Max. Min. Max.
Parameter
Symbol
Unit Note
-10
H-15
CKE
Others
Output High Voltage VOH
Output Low Voltage VOL
Input Leakage Current ILI
Output Leakage Current ILO
—
IOH = –2 mA
IOL = 2 mA
—
2.4
—
2.4
—
2.4
—
V
V
—
—
—
0.4
—
0.4
—
0.4
–
–
10 10 –10 10
10 10 –10 10
–
–
10 10 mA
10 10 mA
—
—
Average Power
Supply Current
(Operating)
I
CC1
CKE ≥ VIH
tCC = min
tRC = min
—
145
40
—
—
125
35
—
—
120 mA 1, 2
No Burst
Power Supply
Current (Stand by)
ICC
2
CKE ≥ VIH
CKE £ VIL
tCC = min
—
—
30 mA
15 mA
3
2
Average Power
Supply Current
(Clock Suspension)
ICC3S
tCC = min
tCC = min
tCC = min
15
—
15
—
Average Power
Supply Current
(Active Stand by)
ICC
3
4
CKE ≥ VIH
—
—
—
95
—
—
—
85
—
—
—
75 mA
3
Power Supply
Current (Burst)
ICC
CKE ≥ VIH
CKE ≥ VIH
210
185
180
155
160 mA 1, 2
I
CC5
tCC = min
tRC = min
Power Supply
Current
155 mA
2
(Auto-Refresh)
Average Power
Supply Current
(Self-Refresh)
ICC
6
7
CKE £ VIL
CKE £ VIL
tCC = min
—
—
2
2
—
—
2
2
—
—
2
2
mA
mA
Average Power
Supply Current
(Power down)
ICC
tCC = min
Notes: 1. Measured with outputs open.
2. The address and data can be changed once or left unchanged during one cycle.
3. The address and data can be changed once or left unchanged during two cycles.
6/28
¡ Semiconductor
MD56V62160/H
Mode Set Address Keys
CAS Latency
Burst Type
Burst Length
A2 A1 A0 BT = 0
Reserved Reserved
A6 A5 A4
CL
A3
BT
BT = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
2
4
8
3
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Note:
A7, A8, A9, A10, A11, A12 and A13 should stay "L" during mode set cycle.
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the V voltage has reached the specified level, pause for 200 ms or more with
CC
the input kept in NOP state.
3. Issue the precharge all bank command.
4. Apply a CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
7/28
¡ Semiconductor
MD56V62160/H
AC Characteristics
Note 1, 2
MD56V62160-10 MD56V62160-12 MD56V62160H-15
Parameter
Symbol
tCC
Unit Note
Min.
10
15
—
—
3
Max.
—
—
9
Min.
12
17.5
—
—
3
Max.
—
Min.
15
15
—
—
3
Max.
—
—
9
CL = 3
ns
ns
Clock Cycles Time
CL = 2
—
CL = 3
CL = 2
10
ns
ns
ns
ns
ns
ns
3, 4
3, 4
Access Time from
Clock
tAC
9
14
9
Clock "H" Pulse Time
Clock "L" Pulse Time
Input Setup Time
Input Hold Time
tCH
tCL
tSI
—
—
—
—
—
—
—
—
—
3
3
—
3
3
3
—
3
tHI
1
1.5
—
1
Output Low Impedance
Time from Clock
tOLZ
tOHZ
3
—
8
3
—
10
3
—
8
ns
ns
Output High Impedance
Time from Clock
—
—
—
Output Hold from Clock
RAS Cycle Time
tOH
tRC
3
—
—
—
105
—
—
3
115
45
70
35
24
—
—
—
105
—
—
3
105
30
70
30
15
—
—
—
105
—
—
ns
ns
ns
ns
ns
ns
3
90
30
60
30
15
RAS Precharge Time
RAS Active Time
tRP
tRAS
tRCD
tWR
RAS to CAS Delay Time
Write Recovery Time
RAS to RAS Bank Active
Delay Time
tRRD
20
—
24
—
24
—
ns
Refresh Time
tREF
—
64
—
3
—
tSI + 1 CLK
—
64
—
3
—
tSI + 1 CLK
—
64
—
3
ms
ns
Power-down Exit Set-up Time tPDE tSI + 1 CLK
Input Level Transition Time tT
CAS to CAS Delay Time (Min.) lCCD
—
ns
1
1
1
1
Cycle
Cycle
Clock Disable Time from CKE
lCKE
1
1
Data Output High Impedance
Time from UDQM, LDQM
lDOZ
2
0
0
2
3
2
2
2
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Data Input Mask Time from
UDQM, LDQM
lDOD
lDWD
lROH
lMRD
lOWD
0
0
2
3
2
0
0
2
3
2
Data Input Time from Write
Command
Data Output High Impedance
Time from Precharge Command
Active Command Input Time from Mode
Register Set Command Input (Min.)
Write Command Input Time
from Output
8/28
¡ Semiconductor
MD56V62160/H
Notes : 1. AC measurements assume that t = 1 ns.
T
2. The reference level for timing of input signals is 1.4 V.
3. Output load.
1.4 V
50 W
Z = 50 W
Output
50 pF
4. The access time is defined at 1.4 V.
5. If t is longer than 1 ns, then the reference level for timing of input signals is V and
T
IH
V .
IL
9/28
¡ Semiconductor
MD56V62160/H
TIMING WAVEFORM
Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRC
CKE
CS
tRP
RAS
tRCD
CAS
Ra
Ca0
Rb
Cb0
ADDR
A13
A12
A10
DQ
Ra
Rb
tOH
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
tOHZ
tAC
tWR
WE
UDQM,
LDQM
Row Active Read Command
Row Active Write Command
Precharge Command
Precharge Command
10/28
¡ Semiconductor
MD56V62160/H
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tCC
tCL
High
CKE
CS
tSI
tHI
RAS
lCCD
tHI
tSI
tSI
CAS
tSI
tSI
Ra
Ca
Cb
Cc
ADDR
tHI
tHI
A13
A12
A10
DQ
Ra
tAC
tHI
tSI
Qa
Db
Qc
tOLZ
tHI
tOH
tOHZ
lOWD
WE
tSI
UDQM,
LDQM
Row Active
Write Command
Precharge Command
Read Command
Read Command
11/28
¡ Semiconductor
MD56V62160/H
*Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE, UDQM, and
LDQM are invalid.
2. When issuing an active, read or write command, the bank is selected by A12 and A13.
A12
0
A13
0
Active, read or write
Bank A
0
1
Bank B
1
0
Bank C
1
1
Bank D
3. The auto precharge function is enabled or disabled by the A10 input when the read or write command
is issued.
A10
0
A12
0
A13
0
Operation
After the end of burst, bank A holds the idle status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the idle status.
After the end of burst, bank B is precharged automatically.
After the end of burst, bank C holds the idle status.
After the end of burst, bank C is precharged automatically.
After the end of burst, bank D holds the idle status.
After the end of burst, bank D is precharged automatically.
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
4. When issuing a precharge command, the bank to be precharged is selected by the A10, A12 and A13
inputs.
A10
0
A12
0
A13
0
Operation
Bank A is precharged.
Bank B is precharged.
Bank C is precharged.
Bank D is precharged.
All banks are precharged.
0
0
1
0
1
0
0
1
1
1
X
X
5. The input data and the write command are latched by the same clock (Write latency = 0).
6. The output is forced to high impedance by (1 CLK + tOHZ) after UDQM, LDQM entry.
12/28
¡ Semiconductor
MD56V62160/H
Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
Bank A Active
RAS
CAS
lCCD
Ca0
Cb0
Cc0
Cd0
ADDR
A13
A12
A10
DQ
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0
*Note2
tWR
lOWD
WE
*Note1
UDQM,
LDQM
Read Command Read Command
Write Command Write Command
Precharge Command
*Notes: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the
write command to avoid bus contention.
2. To assert row precharge before a burst write ends, wait tWR after the last write data input.
Input data during the precharge input cycle will be masked internally.
13/28
¡ Semiconductor
MD56V62160/H
Read & Write Cycle with Auto Precharge @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
tRRD
CAS
RAa
RDb CAa
CDb
ADDR
A13
A12
A10
WE
RAa
RDb
CAS Latency = 2
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
DQ
A-Bank Precharge Start
UDQM,
LDQM
CAS Latency = 3
DQ
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
tWR
A-Bank Precharge Start
UDQM,
LDQM
Row Active
(A-Bank)
A Bank Read with
Auto Precharge
D Bank Write with
Auto Precharge
D Bank Precharge
Start Point
Row Active
(D-Bank)
14/28
¡ Semiconductor
MD56V62160/H
Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
tRC
RAS
tRRD
CAS
RAa
CAa
RCb
CCb
RAc
CAc
ADDR
A13
A12
A10
DQ
RAa
RCb
RAc
QAa0 QAa1 QAa2 QAa3
QCb0 QCb1 QCb2 QCb3
QAc0 QAc1 QAc2 QAc3
WE
UDQM,
LDQM
Row Active Read Command
(A-Bank) (A-Bank)
Read Command
(C-Bank)
Read Command
(A-Bank)
Row Active
(C-Bank)
Precharge Command
(C-Bank)
Precharge Command
(A-Bank)
Row Active
(A-Bank)
15/28
¡ Semiconductor
MD56V62160/H
Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
RAa
CAa
RBb
CBb
RAc
CAc
ADDR
A13
A12
A10
DQ
RAa
RBb
RAc
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3
DAc0 DAc1
WE
UDQM,
LDQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Precharge
Command
(A-Bank)
Write Command
(A-Bank)
Write Command
(A-Bank)
Write Command
(B-Bank)
Row Active
(A-Bank)
Precharge Command
(A-Bank)
Precharge Command
(B-Bank)
16/28
¡ Semiconductor
MD56V62160/H
Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
*Note1
RAS
CAS
RAa
CAa
RCb
CCb
CAc
CCd
CAe
ADDR
A13
A12
A10
DQ
RAa
RCa
QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QCd0 QCd1 QAe0 QAe1
lROH
WE
UDQM,
LDQM
Row Active
(A-Bank)
Row Active
(C-Bank)
Read Command
(C-Bank)
Precharge Command
(A-Bank)
Read Command
(A-Bank)
Read Command
(C-Bank)
Read Command
(A-Bank)
Read Command
(A-Bank)
*Note:
1. CS is ignored when RAS, CAS and WE are high at the same cycle.
17/28
¡ Semiconductor
MD56V62160/H
Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
RBa
CBa
RDb
CDb
CBc
CDd
ADDR
A13
A12
A10
DQ
RBa
RDb
DBa0 DBa1 DBa2 DBa3 DDb0 DDb1 DDb2 DDb3 DBc0 DBc1 DDd0
WE
UDQM,
LDQM
Row Active
(B-Bank)
Row Active
(D-Bank)
Write Command
(D-Bank)
Write Command
(B-Bank)
Write Command
(D-Bank)
Write Command
(B-Bank)
Precharge Command
(All Banks)
18/28
¡ Semiconductor
MD56V62160/H
Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
RAa
CAa
RCb
CCb
RAc
CAc
ADDR
A13
A12
A10
DQ
RAa
RCb
RAc
QAa0 QAa1 QAa2 QAa3
DCb0 DCb1 DCb2 DCb3
QAc0 QAc1 QAc2 QAc3
WE
UDQM,
LDQM
Row Active
(A-Bank)
Write Command
(C-Bank)
Read Command
(A-Bank)
Row Active
(C-Bank)
Read Command
(A-Bank)
Precharge Command
(A-Bank)
Row Active
(A-Bank)
19/28
¡ Semiconductor
MD56V62160/H
Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
CAa0
CDb0
CAc0
ADDR
A13
A12
A10
DQ
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
QAc0 QAc1 QAc2 QAc3
WE
UDQM,
LDQM
Read Command
(A-Bank)
Write Command
(D-Bank)
Read Command
(A-Bank)
20/28
¡ Semiconductor
MD56V62160/H
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
*Note1
*Note1
CKE
CS
RAS
CAS
Ra
Ca
Cb
Cc
ADDR
A13
A12
Ra
A10
Qa0 Qa1
Qa2
Qa2
Qb0 Qb1
Qb0 Qb1
Dc0
Dc2
DQ1 - 8
tOHZ
tOHZ
*Note3
*Note4
DQ9 - 16
Qa0
Qa3
Dc0 Dc1
*Note2
WE
LDQM
*Note4
UDQM
Row Active
Read
DQM
CLOCK
Suspension
Read
Command
Write
DQM
Write
DQM
Read DQM
Read
Write
CLOCK
Read DQM
Command
Command Suspension
*Notes: 1. When Clock Suspension is asserted, the next clock cycle is ignored.
2. When LDQM and UDQM are asserted, the read data after two clock cycles is masked.
3. When LDQM and UDQM are asserted, the write data in the same clock cycle is masked.
4. When LDQM is set High, the input/output data of DQ1 - DQ8 is masked.
When UDQM is set High, the input/output data of DQ9 - DQ16 is masked.
21/28
¡ Semiconductor
MD56V62160/H
Read Interruption by Precharge Command @ Burst Length = 8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
Ra
Ca
ADDR
A13
A12
A10
WE
Ra
CAS Latency = 2
*Note1
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
DQ
UDQM,
LDQM
CAS Latency = 3
*Note1
Qa0 Qa1 Qa2 Qa3 Qa4
DQ
UDQM,
LDQM
Row Active
Read Command
Precharge Command
*Note:
1. If row precharge is asserted before burst read ends, then the read data will not output after the second
clock cycle of the precharge command.
22/28
¡ Semiconductor
MD56V62160/H
Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
*Note2
tSI
*Note1
tPDE
tSI
tSI
CKE
CS
RAS
CAS
Ra
Ca
ADDR
A13
A12
A10
DQ
Ra
Qa0 Qa1 Qa2
WE
UDQM,
LDQM
Row Active
Clock
Suspention
Exit
Precharge
Command
Power-down
Entry
Power-down
Exit
Clock
Suspention
Entry
Read
Command
*Notes: 1. Whenallbanksareinprechargestate, andifCKEissetlow, thentheMD56V62160/Henterspower-down
mode and maintains the mode while CKE is low.
2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (tSI + 1 CLK).
23/28
¡ Semiconductor
MD56V62160/H
Self Refresh Cycle
0
1
2
CLK
tRC
CKE
CS
tSI
RAS
CAS
Ra
BS
BS
Ra
ADDR
A13
A12
A10
DQ
Hi - Z
Hi - Z
WE
UDQM,
LDQM
Self
Self
Row
Refresh
Entry
Refresh
Exit
Active
24/28
¡ Semiconductor
MD56V62160/H
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
High
lMRD
High
CKE
CS
tRC
RAS
CAS
key
Ra
ADDR
DQ
Hi - Z
Hi - Z
WE
UDQM,
LDQM
MRS
New Command
Auto Refresh
Auto Refresh
25/28
¡ Semiconductor
MD56V62160/H
FUNCTION TRUTH TABLE (Table 1) (1/2)
Current State1 CS RAS CAS WE BA ADDR
Action
Idle
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
NOP
NOP
BA
BA
BA
BA
X
X
ILLEGAL 2
ILLEGAL 2
Row Active
NOP 4
X
H
L
CA
RA
A10
X
H
H
L
L
L
H
L
Auto-Refresh or Self-Refresh 5
L
L
L
OP Code Mode Register Write
Row Active
X
H
H
H
L
X
H
L
X
X
H
L
X
X
X
NOP
NOP
X
BA CA, A10 Read
BA CA, A10 Write
L
H
H
L
H
L
BA
BA
X
RA
A10
X
ILLEGAL 2
Precharge
ILLEGAL
L
L
X
X
H
L
Read
X
H
H
H
H
L
X
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Reserved
X
X
BA
X
H
L
BA CA, A10 Term Burst, start new Burst Read
BA CA, A10 Term Burst, start new Burst Write
L
H
H
L
H
L
BA
BA
X
RA
A10
X
ILLEGAL 2
L
Term Burst, execute Row Precharge
ILLEGAL
L
X
X
H
L
Write
X
H
H
H
H
L
X
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Reserved (Term Burst) --> Row Active
X
X
BA
X
H
L
BA CA, A10 Term Burst, start new Burst Read
BA CA, A10 Term Burst, start new Burst Write
L
H
H
L
H
L
BA
BA
X
RA
A10
X
ILLEGAL 2
L
Term Burst, execute Row Precharge
ILLEGAL
L
X
X
H
L
Read with
X
H
H
H
H
L
X
H
H
L
X
X
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL 2
Auto Precharge
X
X
BA
X
H
L
BA CA, A10 ILLEGAL 2
ILLEGAL
BA RA, A10 ILLEGAL 2
L
X
X
H
L
X
X
X
H
L
L
X
X
X
X
X
X
ILLEGAL
Write with
X
H
H
H
H
L
X
H
H
L
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL 2
Auto Precharge
X
BA
H
L
BA CA, A10 ILLEGAL 2
ILLEGAL
BA RA, A10 ILLEGAL 2
ILLEGAL
L
X
X
H
L
X
X
L
X
X
26/28
¡ Semiconductor
MD56V62160/H
FUNCTION TRUTH TABLE (Table 1) (2/2)
Current State1 CS RAS CAS WE BA ADDR
Action
Precharge
Write Recovery
Row Active
Refresh
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
NOP --> Idle after tRP
NOP --> Idle after tRP
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
NOP 4
BA
BA
BA
BA
X
X
X
H
L
CA
RA
A10
X
H
H
L
L
L
X
X
H
L
ILLEGAL
X
H
H
H
L
X
H
H
L
X
X
NOP
X
X
NOP
BA
BA
BA
BA
X
X
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL
X
H
L
CA
RA
A10
X
H
H
L
L
L
X
X
H
L
X
H
H
H
L
X
H
H
L
X
X
NOP --> Row Active after tRCD
NOP --> Row Active after tRCD
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
X
X
BA
BA
BA
BA
X
X
X
H
L
CA
RA
A10
X
H
H
L
L
ILLEGAL 2
L
X
X
X
X
X
X
X
H
L
ILLEGAL
X
H
H
L
X
H
L
X
X
NOP --> Idle after tRC
NOP --> Idle after tRC
ILLEGAL
X
X
X
X
H
L
X
X
ILLEGAL
L
X
X
ILLEGAL
Mode Register
Access
X
H
H
H
L
X
H
H
L
X
X
NOP
X
X
NOP
X
X
ILLEGAL
X
X
X
X
ILLEGAL
X
X
X
ILLEGAL
ABBREVIATIONS
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
NOP = No OPeration command
Notes:
1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegaltobankinspecifiedstate,butmaybelegalinsomecasesdependingonthestateofbank
selection.
3. Satisfy the timing of tCCD and tWR to prevent bus contention.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
27/28
¡ Semiconductor
MD56V62160/H
FUNCTION TRUTH TABLE for CKE (Table 2)
Current State (n) CKEn-1
Self Refresh
CKEn CS RAS CAS WE ADDR
Action
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh --> ABI
Exit Self Refresh --> ABI
ILLEGAL
X
X
X
X
X
H
L
ILLEGAL
X
X
X
X
H
H
L
ILLEGAL
X
X
X
H
H
H
L
NOP (Maintain Self Refresh)
INVALID
Power Down
X
H
H
H
H
H
L
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
X
X
X
X
X
H
L
ILLEGAL
ILLEGAL 6
X
X
X
X
H
H
L
X
X
X
H
H
H
L
NOP (Continue power down mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
All Banks Idle 6
(ABI)
H
L
L
L
L
X
L
ILLEGAL
L
H
L
ILLEGAL
L
L
H
L
Enter Self Refresh
ILLEGAL
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
Any State Other
H
L
Refer to Operations in Table 1
Begin Clock Suspend Next Cycle
Enable Clock of Next Cycle
Continue Clock Suspension
than Listed Above
H
L
Note:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
28/28
相关型号：
MD56V62160-10TA
Synchronous DRAM, 4MX16, 9ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
OKI
MD56V62160E-10TA
Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
OKI
MD56V62160E-7TA
Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
OKI
MD56V62160H-15TA
Synchronous DRAM, 4MX16, 9ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
OKI
©2020 ICPDF网 联系我们和版权申明