ML60851A中文资料_数据手册_规格书

E2N0026-18-Y3

Preliminary

This version: Nov. 1998

ML60851A

¡ Semiconductor

ML60851A

USB Device Controller

GENERAL DESCRIPTION

TheML60851AisageneralpurposeUniversalSerialBus(USB)devicecontroller.TheML60851A

providesaUSBinterface, control/statusblock, applicationinterface, andFIFOs. TheFIFOinterface

and two types of transfer have been optimized for BulkOut devices such as printers and BulkIn

devices such as digital still cameras and image scanners. In addition, Mass Storage devices are

also applicable to this device.

FEATURES

• USB 1.0 compliant

• Built-in USB transceiver circuit

• Full-speed (12 Mb/sec) support

• Supports printer device class, image device class, and Mass Storage device class

• Supports three types of transfer; control transfer, bulk transfer, and interrupt transfer

• Built-in FIFOs for control transfer

Two 8-byte FIFOs (one for receive FIFO and the other for transmit FIFO)

• Built-in FIFOs for bulk transfer (available for either receive FIFO or transmit FIFO)

One 64-byte FIFO

Two 64-byte FIFOs

• Built-in FIFO for interrupt transfer

One 8-byte FIFO

• Supports one control endpoint, two bulk endpoint addresses, and one interrupt endpoint

address

• Two 64-byte FIFOs enable fast BulkOut transfer and BulkIn transfer

• Supports 8 bit/16 bit DMA transfer

• V is 3.0 V to 3.6 V

CC

• Supporting dual power supply enables 5 V application interface

• Built-in 48 MHz oscillator circuit

• Package options:

44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: ML60851AGA)

44-pin plastic TQFP (TQFP44-P-1010-0.80-K) (Product name: ML60851ATB)

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¡ Semiconductor

ML60851A

PIN CONFIGURATION (TOP VIEW)

D+

D–

1

2

33

32

31

30

29

28

27

26

25

24

23

DACK

A0

V_CC3

TEST1

TEST2

XIN

3

A1

4

A2

5

A3

6

A4

XOUT

CS

7

A5

8

A6

RD

9

A7

WR

10

11

ADSEL

ALE

RESET

44-Pin Plastic QFP

D+

D–

1

2

33

32

31

30

29

28

27

26

25

24

23

DACK

A0

V_CC3

TEST1

TEST2

XIN

3

A1

4

A2

5

A3

6

A4

XOUT

CS

7

A5

8

A6

RD

9

A7

WR

10

11

ADSEL

ALE

RESET

44-Pin Plastic TQFP

3/44

¡ Semiconductor

ML60851A

PIN DESCRIPTION

1, 2

Symbol

D+, D–

Type

I/O

—

Description

USB data

6, 7

XIN, XOUT

TEST1, 2

Pin for external crystal oscillator

Test Pins (normally "L")

4, 5

I

13 to 16,

19 to 22

35 to 38,

41 to 44

25 to 32

8

D15:D8

I/O

Data bus (MSB)

AD7:AD0

Data bus (LSB)/address input

A7:A0

CS

I

Address input

Chip select signal input pin. LOW active

Read signal input pin. LOW active

Write signal input pin. LOW active

Interrupt request signal output pin

DMA request output pin

9

RD

I

10

WR

I

12

INTR

DREQ

DACK

ALE

O

I

34

33

DMA acknowledge signal input pin

Address latch enable signal input pin

23

I

24

ADSEL

RESET

I

Address input mode select input pin. "H": address/data multiplex

System Reset signal input pin. LOW active

11

I

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ML60851A

INTERNAL REGISTERS

Addresses and Names of Registers

Address

Register name

Read

Write

A5:A0

A7, A6 A7, A6

00h

01h

02h

03h

04h

08h

09h

0Ah

0Bh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

11b

—

01b

—

Device Address Register

Device State Register

Packet Error Register

—

Receive FIFO Register

Transmit FIFO Register

Endpoint Packet-Ready Register

—

01b

—

Endpoint 0 Receive-Byte Count Register

Endpoint 1 Receive-Byte Count Register

Endpoint 2 Receive-Byte Count Register

Flash Transmit FIFO

—

01b

—

System Control

11b

—

bmRequestType Setup Register

bRequest Setup Register

wValue LSB Setup Register

wValue MSB Setup Register

wIndex LSB Setup Register

wIndex MSB Setup Register

wLength LSB Setup Register

wLength MSB Setup Register

Assertion Select Register

Interrupt Enable Register

Interrupt Status Register

DMA Control Register

—

01b

—

01b

—

DMA Interval Register

Reserved

11b

—

Endpoint 0 Receive Control Register

Endpoint 0 Receive General Register

Endpoint 0 Receive Payload Register

Reserved

—

01b

—

11b

—

01b

—

Endpoint 1 Control Register

Endpoint 1 General Register

Endpoint 1 Payload Register

Reserved

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ML60851A

Addresses and Names of Registers (Continued)

Address

Register name

Endpoint 0 Transmit Control Register

Read

Write

A5:A0

A7, A6 A7, A6

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

00h

01h

02h

00h

01h

02h

03h

11b

—

Endpoint 0 Transmit General Register

Endpoint 0 Transmit Payload Register

Endpoint 0 General Register

Endpoint 2 Control Register

Endpoint 2 General Register

Endpoint 2 Payload Register

Reserved

01b

—

11b

01b

—

01b

—

Endpoint 3 Control Register

Endpoint 3 General Register

Endpoint 3 Payload Register

Endpoint 0 Receive FIFO data

Endpoint 1 Receive FIFO data

Endpoint 2 Receive FIFO data

Endpoint 0 Transmit FIFO data

Endpoint 1 Transmit FIFO data

Endpoint 2 Transmit FIFO data

Endpoint 3 Transmit FIFO data

—

11b

—

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¡ Semiconductor

ML60851A

Register Description

Device Address Register (C0h, 40h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Device Address (R/W)

The local MCU writes a device address, which is given by the SET_ADDRESS command form the

host computer, into this register. Thereafter, this device processes an only token packet transmitted

to the given device address.

Device State Register (C1h, 41h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Default State (R/W)

Address State (R/W)

Configuration State (R/W)

Suspended State (R)

Remote Wakeup (R/W)

USB Bus Reset Clear (W)

Default, Address, and Configuration States: D2, D1, and D0 are set to 0, 0, and 1 (default states) by

reset respectively. Changing the values of this register gives no influence on operation of this

device.

Suspended State: This register is asserted when the device enters the suspended state.

Thisregisterisdeasertedbyresetorwhenthedeviceexitsthesuspendedstatebyaresumesignaling

from the USB bus.

Remote Wakeup: When this device signals a remote wakeup during the suspended state, this

register is asserted by a local MCU. This register is automatically deasserted when the device exits

the suspended state by a resume signaling from the USB bus.

USB Bus Reset Status Clear: Writing "1" to this bit causes the interrupt status to be cleared (the USB

bus reset interrupt status bit is "0" and the INTR pin is deasserted) while the USB bus reset interrupt

is being serviced (when D5, the USB bus reset interrupt status bit, of the interrupt status register is

"1" and the INTR pin is asserted). This bit is readable, and when read, its value will be always "0".

Packet Error Register (C2h, –)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Bit Stuff Error (R)

RFU = 0000b

Data CRC Error (R)

Address CRC Error (R)

PID Error (R)

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ML60851A

FIFO Status Register 1 (C3h, –)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Receive FIFO0 Full (R)

RFU = 0000b

Receive FIFO0 Empty (R)

FIFO1 Full (R)

FIFO1 Empty (R)

FIFO Status Register 2 (C4h, –)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Transmit FIFO0 Full (R)

Transmit FIFO0 Empty (R)

FIFO2 Full (R)

FIFO2 Empty (R)

RFU = 0000b

FIFO3 Full (R)

FIFO3 Empty (R)

Endpoint Packet-Ready Register (C8h, 48h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

EP0 Receive Packet Ready (R/Reset)

EP1 Receive Packet Ready (R/Reset)

EP2 Receive Packet Ready (R/Reset)

EP0 Transmit Packet Ready (R/Set)

EP1 Transmit Packet Ready (R/Set)

EP2 Transmit Packet Ready (R/Set)

EP3 Transmit Packet Ready (R/Set)

Receive Packet Ready: When a valid packet arrives at an endpoint, this bit is automatically set and

the endpoint is locked. When "1" is written in this register, Receiver Packet Ready is reset and the

endpoint is unlocked. (This bit also is set to "0".)

When DMA is enabled, EP1 Receive Packet Ready is automatically reset after all the data in EP1 is

read during DMA transfer.

Transmit Packet Ready: When "1" is written in this register, the Transmit Packet Readyissetand the

packet in the corresponding endpoint is transmitted. Transmit Packet Ready is automatically reset

when the ACK handshake is returned from the host.

WhenDMAisenabled, EP1TransmitPacketReadyisautomaticallysetafterthedatawritteninEP1

reaches the maximum packet size during DMA transfer.

The value of this register remains unchanged when "0" is written in this register.

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ML60851A

Endpoint 0 Receive Byte Count Register (C9h, –)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

EP0 Byte Count (R)

Endpoint 1 Receive Byte Count Register (CAh, –)

D7

D6

D5

D4

D3

D2

RFU

EP1 Byte Count (R)

Endpoint 2 Receive Byte Count Register (CBh, –)

D7

D6

D5

D4

D3

D2

RFU

EP2 Byte Count (R)

Flash Transmit FIFO (–, 4Eh)

D7

D6

D5

D4

D3

D2

D1

D0

0

In case EP1 is set as a transmission endpoint, when "1" is

written in this bit, the FIFO at EP1 is cleared and Packet

Ready at EP1 is reset by the WRITE pulse.

In case EP2 is set as a transmission endpoint, when "1" is

written in this bit, the FIFO at EP2 is cleared and Packet

Ready at EP2 is reset by the WRITE pulse.

In case EP3 is set as a transmission endpoint, when "1" is

written in this bit, the FIFO at EP3 is cleared and Packet

Ready at EP3 is reset by the WRITE pulse.

Note: Please clear all FIFOs at the same time, otherwise some of them may not be cleared.

System Control (–, 4Fh)

D7

D6

D5

D4

D3

0

D2

0

D1

0

D0

When "1" is written in this bit, the ML60851A is reset

by the WRITE pulse.

Oscillation Stop Command

Oscillation Stop Command: Writing 1010b to D7 to D4, (writing A0h into this register) causes the

oscillator circuit of the ML60851A to be deactivated and go into the standby mode.

Whenoscillationisstopped,readingandwritingintotheregisterispossiblebutreadingandwriting

into FIFO is not possible. Asserting the RESET pin restarts oscillation.

9/44

¡ Semiconductor

ML60851A

bmRequestType Setup Register (D0h, –)

D7

D6

D5

D4

D3

D2

D1

D0

Type (R)

Recipient (R)

0 = Device

1 = Interface

2 = Endpoint

3 = Others

4 to 31 = Reserved

0 = Standard

1 = Class

2 = Vendor

3 = Reserved

0 = Host to device

1 = Device to host

Data Transfer Direction (R)

bRequest Setup Register (D1h, –)

D7

D6

D5

D4

D3

D2

D1

D0

Specific Request (R)

• wValueLSB Setup Register (D2h, –)

D7:D0 = LSB of Word Size Field (R)

• wValueMSB Setup Register (D3h, –)

D7:D0 = MSB of Word Size Field (R)

• wIndexLSB Setup Register (D4h, –)

D7:D0 = LSB of Word Size Field (R)

• wIndexMSB Setup Register (D5h, –)

D7:D0 = MSB of Word Size Field (R)

• wLengthLSB Setup Register (D6h, –)

This field defines the length of data that is transferred in the second stage (data stage) of control

transfer. (R)

• wLengthMSB Setup Register (D7h, –)

This field defines the length of data that is transferred in the data stage of control transfer. (R)

10/44

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ML60851A

Assertion Select Register (DAh, 5Ah) (R/W)

D7

D6

D5

D4

D3

D2

D1

D0

Assertion

of DACK

Assertion

RFU

of DREQ

of INTR

0 = Active LOW (Initial value)

1 = Active HIGH

0 = Active LOW (Initial value)

1 = Active HIGH

0 = Active HIGH (Initial value)

1 = Active LOW

Interrupt Enable Register (DBh, 5Bh) (R/W)

D7

D6

D5

D4

D3

D2

D1

D0

Setup Ready

Interrupt Enable

EP1 Packet Ready

Interrupt Enable

EP2 Packet Ready

Interrupt Enable

EP0 Receive Packet Ready

Interrupt Enable

EP0 Transmit Packet Ready

Interrupt Enable

USB Bus Reset

Interrupt Enable

Suspended State

Interrupt Enable

EP3 Packet Ready

Interrupt Enable

Initial value of D0 is 1.

Initial values of D1 to D7 are 0.

11/44

¡ Semiconductor

ML60851A

Interrupt Status Register (DCh, 5Ch) (R)

D7

D6

D5

D4

D3

D2

D1

D0

Setup Ready

Interrupt Status (R)

EP1 Packet Ready

Interrupt Status (R)

EP2 Packet Ready

Interrupt Status (R)

EP0 Receive Packet Ready

Interrupt Status (R)

EP0 Transmit Packet Ready

Interrupt Status (R)

USB Bus Reset

Interrupt Status

Suspended State

Interrupt Status (R)

EP3 Packet Ready

Interrupt Status

SetupReadyInterruptStatus: EquivalenttoSetupReadyat(F3h)describedlaterwhenthecorresponding

Interrupt Enable bit is asserted.

EP1PacketReadyInterruptStatus: EquivalenttoEP1ReceivePacketReady(thecomplementofEP1

Transmit Packet Ready when EP1 is set for transmitter) at (C8h) described before when the

corresponding Interrupt Enable bit is asserted.

EP2PacketReadyInterruptStatus: EquivalenttoEP2ReceivePacketReady(thecomplementofEP2

Transmit Packet Ready when EP2 is set for transmitter) at (C8h) described before when the

corresponding Interrupt Enable bit is asserted.

EP0ReceivePacketReadyInterruptStatus: EquivalenttoEP0ReceivePacket Ready at (C8h) described

before when the corresponding Interrupt Enable bit is asserted.

EP0TransmitPacketReadyInterruptStatus: EquivalenttothecomplementofEP0TransmitPacket

Ready at (C8h) described before when the corresponding Interrupt Enable bit is asserted.

USB Bus Reset Interrupt Status: This bit is set to "1" at USB bus reset when the D5 bit of the interrupt

enable register (DBh) is "1". To return this bit back to "0", "1" should be written to the D5 bit of the

device states register.

SuspendedStateInterruptStatus: EquivalenttoSuspendedStateRegisterat(C1h)describedbefore

when the corresponding Interrupt Enable bit is asserted.

EP3 Packet Ready Interrupt Status: When the D7 bit of the interrupt enable register (DBh) is "1", the

complement of the D7 bit of the endpoint packet ready register (C8h) is being copied.

12/44

¡ Semiconductor

ML60851A

DMA Control Register (DDh, 5Dh) (R/W)

D7

D6

D5

D4

D3

D2

Byte

Count

D1

D0

DMA

Enable

Transfer

Mode

Transfer

Size

Address

Mode

RFU

0 = Disables DMA Transfer (Initial value)

1 = Enables DMA Transfer for EP1

0 = Single Address Mode (Initial value)

1 = Dual Address Mode

0 = (Initial value)

1 = Inserts EP1 receive byte count into the top byte or

top word of the transfer data. (Note 1)

0 = Byte (8 bits) (Initial value)

1 = Word (16 bits) (Note 2)

0 = Single Transfer Mode (Initial value)

1 = Demand Transfer Mode

(Note 1) When 16-bit mode is set, the upper byte of the top word is 00h.

(Note 2) When16-bitmodeissetandthepacketsizeisanodd-numberbyte, theupperbyteofthe

last word is 00h.

DMA Interval Register (DEh, 5Eh) (R/W)

D7

D6

D5

D4

D3

D2

D1

D0

This register specifies a DMA transfer interval between de-assertion and re-assertion of DREQ in

Single Transfer mode. The interval is specified between 0 and 255 (bit times). The initial value is 0.

1-bit time = 1/12 MHz (= 84 ns)

13/44

¡ Semiconductor

ML60851A

Endpoint 0 Receive Control Register (E0h, –)

D7

D6

0

D5

0

D4

0

D3

0

D2

0

D1

D0

RFU

Configuration Bit (R)

Transfer Type (R)

Endpoint Address (R)

Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from a host computer

to this EP is received. The packet is ignored when this bit is deasserted ("0").

This bit is deasserted by system reset and is asserted by USB reset (both D+ and D- are 0s for more

than 2.5 ms).

Endpoint 0 Receive General Register (E1h, –)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Data Sequence

Toggle Bit (R)

Endpoint 0 Receive Payload Register (E2h, 62h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Maximum Packet Size (R/W)

14/44

¡ Semiconductor

ML60851A

Endpoint 1 Control Register (E4h, 64h)

Register to set the attribute of EP1.

To use EP1, the local MCU writes EP1's attribute in this register by the request from the host

computer.

D7

D6

0

D5

0

D4

1

D3

1

D2

0

D1

D0

Configuration Bit (R/W)

Stall Bit (R/W)

10 = Bulk Transfer

Transfer Type (R)

Endpoint Address (R)

0 = Reception (OUT endpoint) (Supports printer)

Transfer Direction (R/W)

1 = Transmission (IN endpoint) (Supports scanner, DSC)

Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from the host computer

to this EP is received. The packet is ignored when this bit is deasserted ("0").

Whether or not this EP is configured can be known by referencing this bit.

Stall Bit: When this bit is asserted ("1"), a stall handshake for a packet transmitted from the host

computer to this EP is automatically returned to the host computer.

Endpoint 1 General Register (E5h, 65h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Data Sequence

Toggle Bit (R/Reset)

Data Sequence Toggle Bit: When initializing EP, PID of DATA0 is specified after resetting the Data

Packet Toggle bit by writing "1" to this bit (this bit goes to "0").

Endpoint 1 Payload Register (E6h, 66h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Maximum packet size (R/W)

15/44

¡ Semiconductor

ML60851A

Endpoint 3 Control Register (F8h, 78h)

Register to set the attribute of EP3.

To use EP3, the local MCU writes EP3's attribute in this register by the request from the host

computer.

D7

D6

0

D5

1

D4

1

D3

1

D2

1

D1

D0

Configuration Bit (R/W)

Stall Bit (R/W)

11 = Interrupt Transfer

Endpoint Address (R)

Transfer Type (R)

0 = Number

Toggle Condition (R/W)

1 = Rate Feedback Mode

Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from the host computer

to this EP is received. The packet is ignored when this bit is deasserted ("0").

Whether or not this EP is configured can be known by referencing this bit.

Stall Bit: When this bit is asserted ("1"), a stall handshake for a packet transmitted from the host

computer to this EP is automatically returned to the host computer.

Toggle Condition Bit: When this bit is "0", DATA0 and DATA1 are toggled each time ACK is

received form the host computer by the EP3. Setting this bit to "1" causes the ML60851A to go

into the rate feedback mode, in which case DATA0 and DATA1 are toggled each time the packet

ready is asserted by the local MCU.

Endpoint 3 General Register (F9h, 79h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Data Sequence

Toggle Bit (R/Reset)

Data Sequence Toggle Bit: When initializing EP, PID of DATA0 is specified after resetting the Data

Packet Toggle bit by writing "1" to this bit (this bit goes to "0").

Endpoint 3 Payload Register (FAh, 7Ah)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Maximum packet size (R/W)

16/44

¡ Semiconductor

ML60851A

Endpoint 0 Transmit Control Register (F0h, –)

D7

D6

D5

D4

D3

0

D2

0

D1

D0

RFU

Transfer Type (R)

Endpoint 0 Transmit General Register (F1h, –)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Data Sequence

Toggle Bit (R)

Endpoint 0 Transmit Payload Register (F2h, 72h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Maximum Packet Size (R/W)

Endpoint 0 Transmit General Register (F3h, 73h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Setup Ready (R/Reset)

Stall Bit (R/W)

EP0 Stage (R)

00 = Setup Stage

01 = Data Stage

10 = Status Stage

Setup Ready: When a valid setup packet has arrived at an 8-byte setup register, this register is

automaticallysetandthereceiveFIFOatendpoint0islocked. Writing"1"inthisregisterresetsSetup

Ready. When the data stage of Control Write transaction follows, Packet Ready at endpoint 0 is also

reset. Therefore, theendpoint0receiveFIFOisunlockedandreadytoreceivethepacketsinthedata

stage.

The value of this register remains unchanged when "0" is written in this register.

17/44

¡ Semiconductor

ML60851A

Endpoint 2 Control Register (F4h, 74h)

D7

D6

0

D5

1

D4

0

D3

1

D2

0

D1

D0

Configuration Bit (R/W)

Stall Bit (R/W)

10 = Bulk Transfer

Transfer Type (R)

Endpoint Address (R)

0 = Reception (OUT endpoint)

1 = Transmission (IN endpoint)

Transfer Direction (R/W)

Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from the host computer

to this EP is received. The packet is ignored when this bit is deasserted ("0").

Whether or not this EP is configured can be known by referencing this bit.

Stall Bit: When this bit is asserted ("1"), a stall handshake for a packet transmitted from the host

computer to this EP is automatically returned to the host computer.

Endpoint 2 General Register (F5h, 75h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Data Sequence

Toggle Bit (R/Reset)

Data Sequence Toggle Bit: When initializing EP, PID of DATA0 is specified after resetting the Data

Packet Toggle bit by writing "1" to this bit (this bit goes to "0").

Endpoint 2 Payload Register (F6h, 76h)

D7

D6

D5

D4

D3

D2

D1

D0

RFU

Maximum Packet Size (R/W)

18/44

¡ Semiconductor

ML60851A

Endpoint 0 Receive FIFO Data (40h, –)

D7

D6

D5

D4

D3

D2

D1

D0

Endpoint 0 Receive FIFO Data (R)

AreatostoredatatobetransmittedfromthehostcomputertothisdeviceinthedatastageofControl

Write transfer.

Endpoint 1 Receive FIFO Data (41h, –)

D7

D6

D5

D4

D3

D2

D1

D0

Endpoint 1 Receive FIFO Data (R)

AreatostoredatatobetransmittedfromthehostcomputertoEP1ofthisdeviceinBulkOuttransfer.

This register is valid only when EP1 is set for the OUT endpoint.

Endpoint 2 Receive FIFO Data (42h, –)

D7

D6

D5

D4

D3

D2

D1

D0

Endpoint 2 Receive FIFO Data (R)

AreatostoredatatobetransmittedfromthehostcomputertoEP2ofthisdeviceinBulkOuttransfer.

This register is valid only when EP2 is set for the OUT endpoint.

19/44

¡ Semiconductor

ML60851A

Endpoint 0 Transmit FIFO Data (–, C0h)

D7

D6

D5

D4

D3

D2

D1

D0

Endpoint 0 Transmit FIFO Data (W)

AreatostoredatatobetransmittedfromthisdevicetothehostcomputerinthedatastageofControl

Read transter.

Endpoint 1 Transmit FIFO Data (–, C1h)

D7

D6

D5

D4

D3

D2

D1

D0

Endpoint 1 Transmit FIFO Data (W)

Area to store data to be transmitted from EP1 of this device to the host computer in Bulk In transfer.

This register is valid only when EP1 is set for the IN endpoint.

Endpoint 2 Transmit FIFO Data (–, C2h)

D7

D6

D5

D4

D3

D2

D1

D0

Endpoint 2 Transmit FIFO Data (W)

Area to store data to be transmitted from EP2 of this device to the host computer in Bulk In transfer.

This register is valid only when EP2 is set for the IN endpoint.

Endpoint 3 Transmit FIFO Data (–, C3h)

D7

D6

D5

D4

D3

D2

D1

D0

Endpoint 3 Transmit FIFO Data (W)

Area to store data to be transmitted from EP3 of this device to the host computer in Bulk In transfer.

This register is valid only when EP3 is set for the IN endpoint.

20/44

¡ Semiconductor

ML60851A

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply 3

Symbol

V_CC3

V_CC5

V_I

Condition

Rating

–0.3 to +4.6

Unit

V

—

Power Supply 5

Input Voltage

–0.5 to +6.5

V

–0.3 to V_CC5+ 0.3

–55 to +150

V

Storage Temperature

T_STG

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply 3

Symbol

V_CC3

V_CC5

Ta

Condition

Range

3.0 to 3.6

3.0 to 5.5

0 to 70

48

Unit

V

—

Power Supply 5

V

Operating Temperature

Oscillation Frequency

°C

F_OSC

MHz

21/44

¡ Semiconductor

ML60851A

ELECTRICAL CHARACTERISTICS

DC Characteristics (1)

(V_CC5= V_CC3= 3.0 to 3.6 V, V_SS= 0 V, Ta = 0 to 70°C)

Parameter

High-level Input

Voltage

Symbol

Condition

Min.

Typ.

Max.

Unit Applicable pin

V_IH

—

2.0

—

V_CC5+ 0.3

V

Note 1

Low-level Input

Voltage

V_IL

V_IH

V_IL

—

–0.3

V_CC3¥ 0.8

–0.3

—

+0.8

V

High-level Input

Voltage

V

_CC3+ 0.3

V

XIN

Low-level Input

Voltage

V_CC3¥ 0.2

V

V_t+

V_t–

DV_t

—

0.8

1.6

1.2

0.4

—

2.0

—

V

Schmitt Trigger

Input Voltage

V

RESET

(V_t+) – (V_t–)

0.1

—

=

High-level

I_OH–100 mA

V_CC5– 0.2

2.4

—

V_OH

V_OL

I_IH

D15:D8

AD7:AD0

=

Output Voltage

Low-level

I_OH–4 mA

—

I

_OL= 100 mA

—

0.2

0.4

INTR, DREQ

Output Voltage

High-level Input

Current

I_OL= 4 mA

—

V_IH= V_CC5

V_IL= V_SS

—

–1

0.01

1

mA

Note 2

Low-level Input

Current

I_IL

–0.01

—

3-state Output

Leakage Current

Power Supply

Current (Operating)

Power Supply

Current (Standby)

I_OZH

I_OZL

V_OH= V_CC5

V_OL= V_SS

—

–1

—

0.01

–0.01

—

1

mA

D15:D8

AD7:AD0

V_CC3

—

50

5

I_CC3

I_CC5

—

V_CC5

I_CCS3

I_CCS5

Note 3

—

50

V_CC3

—

V_CC5

Notes: 1. Applied to D15:D8, AD7:AD0, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL.

foronlyXIN.

2. AppliedtoXIN,A7:A0,CS,RD,WR,DACK,ALE,andADSEL. V =V

IH

CC3

3. The XIN pin is fixed to High level or Low level in the suspend state. All the output

pins are open.

22/44

¡ Semiconductor

ML60851A

DC Characteristics (2)

(V_CC5= 4.5 to 5.5 V, V_CC3= 3.0 to 3.6 V, V_SS= 0 V, Ta = 0 to 70°C)

Parameter

High-level Input

Voltage

Symbol

Condition

Min.

Typ.

Max.

Unit Applicable pin

V_IH

—

2.2

—

V_CC5+ 0.5

V

Note 1

Low-level Input

Voltage

V_IL

—

–0.5

—

+0.8

V

V_t+

V_t–

DV_t

—

0.8

1.7

1.4

0.3

—

2.2

—

V

Schmitt Trigger

Input Voltage

V

RESET

(V_t+) – (V_t–)

0.2

—

=

High-level

I_OH–100 mA

V_CC5– 0.2

3.7

—

V_OH

V_OL

I_IH

D15:D8

AD7:AD0

=

Output Voltage

Low-level

I_OH–8 mA

—

I_OL= 100 mA

—

0.2

0.4

INTR, DREQ

Output Voltage

High-level Input

Current

I_OL= 8 mA

—

V

_IH= V_CC5

_IL= V_SS

—

0.01

10

—

mA

Note 2

Low-level Input

Current

I_IL

V

–10

–0.01

3-state Output

Leakage Current

Power Supply

Current (Operating)

Power Supply

Current (Standby)

I_OZH

I_OZL

V_OH= V_CC5

V_OL= V_SS

—

–10

—

0.01

–0.01

—

10

—

50

5

mA

D15:D8

AD7:AD0

V_CC3

I_CC3

I_CC5

—

V_CC5

I_CCS3

I_CCS5

Note 3

—

50

V_CC3

—

V_CC5

Notes: 1. Applied to D15:D8, AD7:AD0, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL. The DC

characteristics (1) applies to XIN.

2. Applied to A7:A0, CS, RD, WR, DACK, ALE, and ADSEL. The DC characteristics (1)

applies to XIN.

3. The XIN pin is fixed to High level or Low level in the suspend state. All the output

pins are open.

23/44

¡ Semiconductor

ML60851A

DC Characteristics (3) USB Port

(V_CC3= 3.0 to 3.6 V, V_SS= 0 V, Ta = 0 to 70°C)

Parameter

Differential Input

Sensitivity

Symbol

Condition

Min.

Typ.

Max.

Unit Applicable pin

V_DI

(D+) – (D–)

0.2

V

Differential Common

Mode Range

V_CM

V_SE

V_OH

Includes V_DIrange

0.8

2.8

2.5

2.0

3.6

0.3

+10

V

Single Ended

Receiver Threshold

High-level Output

Voltage

V

D+, D–

V

RL of 15 kW to V_SS

Low-level Output

Voltage

V_OLRL of 1.5 kW to 3.6 V

I_LO0 V < V_IN< 3.3 V

V

Output Leakage

Current

–10

mA

AC Characteristics USB Port

(V_CC3= 3.0 to 3.6 V, V_SS= 0 V, Ta = 0 to 70°C)

Condition

(Notes 1. and 2.)

CL = 50 pF

Parameter

Symbol

Min.

Typ.

Max.

Unit Applicable pin

Rise Transition Time

Fall Transition Time

Rise/Fall Time

Matching

t_R

t_F

4

25

ns

CL = 50 pF

t_RFM

V_CRS

Z_DRV

(t_R/t_F)

90

1.2

140

2

%

Output Signal

Crossover Voltage

Driver Output

V

W

D+, D–

Steady State Driver

28

43

Resistance

Ava. Bit

Data Rate

t_DRATE

11.97

12.03

Mbs

Rate (12 Mb/s 0.25%)

Notes: 1. 1.5 kW pull-up to 2.8 V on the D+ data line.

2. Measured from 10% to 90% of the data signal.

24/44

¡ Semiconductor

ML60851A

TIMING DIAGRAM

READ Timing (1)

(Address Separate ADSEL = 0)

Parameter

Address Setup Time (RD)

Address Setup Time (CS)

Address (CS) Hold Time

Read Data Delay Time

Read Data Hold Time

Recovery Time

Symbol

Condition

Min.

21

10

0

Max.

—

Unit

Note

t₁(RD)

ns

5

2

1

t₁(CS)

—

t₂

t₃

t₄

t₅

t₆

—

Load 20 pF

—

0

25

—

FIFO READ

63

42

—

3

4

FIFO Access Time

—

Notes: 1. t and t are defined depending upon CS or RD which becomes active last.

1

3

2. t is defined depending upon CS or RD which becomes active first.

2

3. 3-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.

4. 2-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.

5. Either of them should be met.

A7:A0

t₁

t₂

t₆

CS

RD

t₅

t₃

t₄

AD7:AD0

DATA OUT

25/44

¡ Semiconductor

ML60851A

READ Timing (2)

(Address/Data Multiplex ADSEL = 1)

Parameter

Address (CS) Setup Time

Address (CS) Hold Time

Read Data Delay Time

Read Data Hold Time

Recovery Time

Symbol

Condition

Min.

10

0

Max.

—

Unit

Note

t₁

t₂

t₃

t₄

t₅

t₆

ns

—

Load 20 pF

—

0

25

—

FIFO READ

63

42

—

1

2

FIFO Access Time

—

Notes: 1. 3-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.

2. 2-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.

ADDRESS

DATA OUT

AD7:AD0

t₁

t₂

t₄

CS

ALE

t₃

t₅

RD

t₆

26/44

¡ Semiconductor

ML60851A

WRITE Timing (1)

(Address Separate ADSEL = 0)

Parameter

Address Setup Time (WR)

Address Setup Time (CS)

Address (CS) Hold Time

CS Setup Time

Symbol

Condition

Min.

21

10

0

Max.

—

Unit

Note

t₁(WR)

ns

4

t₁(CS)

—

t₂

t₃

t₄

t₅

t₆

t₇

—

10

30

5

—

Write Data Setup Time

Write Data Hold Time

Recovery Time

—

FIFO WRITE

63

42

—

2

3

FIFO Access Time

—

Notes: 1. t is defined depending upon CS or WR which becomes active last.

1

2. 3-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.

3. 2-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.

4. Either of them should be met.

A7:A0

t₁

t₂

t₇

CS

t₃

t₆

WR

t₅

t₄

DATA IN

AD7:AD0

27/44

¡ Semiconductor

ML60851A

WRITE Timing (2)

(Address/Data Multiplex ADSEL = 1)

Parameter

Address (CS) Setup Time

Address (CS) Hold Time

Write Data Setup Time

Write Data Hold Time

Recovery Time

Symbol

Condition

Min.

10

0

Max.

—

Unit

Note

t₁

t₂

t₃

t₄

t₅

t₆

ns

—

30

5

—

FIFO WRITE

63

42

—

1

2

FIFO Access Time

—

Notes: 1. 3-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.

2. 2-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.

AD7:AD0

ADDRESS

t₁

DATA IN

t₂

t₄

CS

ALE

t₃

t₅

WR

t₆

28/44

¡ Semiconductor

ML60851A

DMA Transfer Timing (1)

ML60851A to Memory (Single Transfer, Single Address Mode)

Parameter

DREQ Disable Time

DREQ Enable Time

DACK Hold Time

Symbol

Condition

Min.

—

0

Max.

20

Unit

Note

t₁

t₂

t₃

t₄

t₅

Load 20 pF

ns

63

—

Read Data Delay Time

Data Hold Time

Load 20 pF

—

0

25

1

—

8-bit DMA

63

105

—

2

3

Recovery Time

t₆

16-bit DMA

—

Notes: 1. When in Single Address mode, CS and A7:A0 are ignored.

t is defined depending on DACK or RD which becomes active last.

4

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

DREQ

t₃

t₂

t₁

DACK

t₄

t₆

RD

t₅

DOUT

29/44

¡ Semiconductor

ML60851A

DMA Transfer Timing (2)

ML60851A to Memory (Single Transfer, Dual Address Mode)

Parameter

DREQ Disable Time

DREQ Enable Time

Read Data Delay Time

Data Hold Time

Symbol

Condition

Min.

—

Max.

20

Unit

Note

t₁

t₂

t₃

t₄

Load 20 pF

ns

—

63

Load 20 pF

—

25

1

0

—

8-bit DMA

63

—

2

3

Recovery Time

t₅

16-bit DMA

105

—

Notes: 1. When in Dual Address mode, the DACK is ignored.

t is defined depending on CS or RD which becomes active last.

3

A7:A0 specifies the FIFO address.

Refer to READ Timing (1) for Address Setup Time and Address Hold Time.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

A7:A0

DREQ

t₂

t₁

CS

t₅

t₃

RD

t₄

DOUT

30/44

¡ Semiconductor

ML60851A

DMA Transfer Timing (3)

ML60851A to Memory (Demand Transfer, Single Address Mode)

Parameter

DREQ Disable Time

DACK Hold Time

Symbol

Condition

Min.

—

0

Max.

20

Unit

Note

t₁

t₂

t₃

t₄

Load 20 pF

ns

—

Read Data Delay Time

Data Hold Time

Load 20 pF

—

0

25

1

—

8-bit DMA

63

105

—

2

3

Recovery Time

t₅

16-bit DMA

—

Notes: 1. When in Single Address mode, t is defined depending on DACK orRD which becomes

3

active last.

A7:A0 and CS are ignored.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

DREQ

t₁

DACK

t₅

t₂

RD

Last Packet Read

t₃

t₄

DOUT

31/44

¡ Semiconductor

ML60851A

DMA Transfer Timing (4)

ML60851A to Memory (Demand Transfer, Dual Address Mode)

Parameter

DREQ Disable Time

CS Hold Time

Symbol

Condition

Min.

—

0

Max.

20

Unit

Note

t₁

t₂

t₃

t₄

Load 20 pF

ns

—

Read Data Delay Time

Data Hold Time

Load 20 pF

—

0

25

1

—

8-bit DMA

63

105

—

2

3

Recovery Time

t₅

16-bit DMA

—

Notes: 1. When in Dual Address mode, the DACK is ignored.

t is defined depending on CS or RD which becomes active last.

3

A7:A0 specifies the FIFO address.

Refer to READ Timing (1) for Address Setup Time and Address Hold Time.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

A7:A0

DREQ

CS

t1

t₅

t₂

RD

t₄

Last Packet Read

t₃

DOUT

32/44

¡ Semiconductor

ML60851A

DMA Transfer Timing (5)

Memory to ML60851A (Single Transfer, Single Address Mode)

Parameter

DREQ Disable Time

DREQ Enable Time

FIFO Access Time

Symbol

Condition

Min.

—

42

0

Max.

20

Unit

Note

t₁

t₂

t₃

t₄

t₅

t₆

Load 20 pF

ns

63

FIFO WRITE

—

1

DACK Hold Time

—

Write Data Setup Time

Write Data Hold Time

30

5

—

8-bit DMA

63

105

—

2

3

Recovery Time

t₇

16-bit DMA

—

Notes: 1. When in Single Address mode, CS and A7:A0 are ignored.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

DREQ

t₄

t₂

t₁

DACK

t₃

t₇

WR

t₆

t₅

DIN

33/44

¡ Semiconductor

ML60851A

DMA Transfer Timing (6)

Memory to ML60851A (Single Transfer, Dual Address Mode)

Parameter

DREQ Disable Time

DREQ Enable Time

FIFO Access Time

Symbol

Condition

Min.

—

Max.

20

Unit

Note

t₁

t₂

t₃

t₄

t₅

Load 20 pF

ns

—

63

FIFO WRITE

42

—

1

Write Data Setup Time

Write Data Hold Time

30

—

5

—

8-bit DMA

63

—

2

3

Recovery Time

t₆

16-bit DMA

105

—

Notes: 1. When in Dual Address mode, the DACK is ignored.

Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

A7:A0

DREQ

t₂

t₁

CS

t₃

t₆

WR

t₅

t₄

DIN

34/44

¡ Semiconductor

ML60851A

DMA Transfer Timing (7)

Memory to ML60851A (Demand Transfer, Single Address Mode)

Parameter

DREQ Disable Time

FIFO Access Time

Symbol

Condition

Load 20 pF

FIFO WRITE

Min.

—

42

0

Max.

20

Unit

Note

t₁

t₂

t₃

t₄

t₅

ns

—

1

DACK Hold Time

—

Write Data Setup Time

Write Data Hold Time

30

5

—

8-bit DMA

63

105

—

2

3

Recovery Time

t₆

16-bit DMA

—

Notes: 1. When in Single Address mode, A7:A0 and CS and ignored.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

DREQ

t₁

DACK

t₂

t₆

t₃

WR

(Note)

t₄

t₅

Last Packet Write

DIN

(Note) ThelastWritetoreachthebytesize(maximumpacketsize)specifiedbytheEP1Payload

Register.

ToterminateDMAtransferbeforereachingthemaximumpacketsize,setEP1PacketReady

by writing "1" to the EP1 Transmit Packet Ready bit.

35/44

¡ Semiconductor

ML60851A

DMA Transfer Timing (8)

Memory to ML60851A (Demand Transfer, Dual Address Mode)

Parameter

DREQ Disable Time

FIFO Access Time

CS Hold Time

Symbol

Condition

Load 20 pF

FIFO WRITE

Min.

—

42

0

Max.

20

Unit

Note

t₁

t₂

t₃

t₄

t₅

ns

—

1

—

Write Data Setup Time

Write Data Hold Time

30

5

—

8-bit DMA

63

105

—

2

3

Recovery Time

t₆

16-bit DMA

—

Notes: 1. When in Dual Address mode, the DACK is ignored.

A7:A0 specifies the FIFO address.

Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

A7:A0

DREQ

CS

t₁

t₃

t₂

t₆

WR

(Note)

t₄

t₅

Last Packet Write

DIN

(Note) Refer to the previous page.

36/44

¡ Semiconductor

ML60851A

FUNCTIONAL DESCRIPTIONS

Pin Functional Description

USB Interface

Signal

Type Assertion

Description

USB data (Plus). This signal and the D– signal are the transmitted or received

data from/to USB Bus. The table below shows values and results for these signal.

D+

0

D–

0

Result

Single end 0

D+

I/O

—

0

1

Differential "0"

Differential "1"

Undefined

1

0

1

USB Data (Minus). This signal and the D+ signal are the transmitted or

received data from/to USB Bus. The table above shows values and results for

these signals.

D–

Crystal Oscillator Interface

Signal

Type Assertion

Description

For internal oscillation, connect a crystal to XIN and XOUT.

For external oscillation, supply an external 48 MHz clock signal to XIN.

Set XOUT to be open.

XIN

I

—

XOUT

O

—

37/44

¡ Semiconductor

ML60851A

Application Interface

Signal

Type Assertion

Description

Upper byte (MSB) of data bus. This data bus is used by applications to access

register files and FIFO data.

D15:D8

I/O

—

Lower byte (LSB) of data bus when ADSEL is LOW.

Address and lower byte of data bus are multiplexed when ADSEL is HIGH.

Address when ADSEL is LOW. This address signal is used by application to

access register files and FIFO data.

AD7:AD0

A7:A0

I

—

This signal is ignored (all lows or all highs) when ADSEL is HIGH.

Chip Select. When this signal is asserted LOW, the ML60851A is selected

and ready to read or write data.

CS

RD

I

LOW

Read Strobe. When this signal is asserted LOW, the Read instruction is

executed.

Write Strobe. When this signal is asserted LOW, the Write instruction is

executed.

WR

I

LOW

Interrupt Request. When this signal is asserted, the ML60851A makes an

INTR

DREQ

DACK

ALE

O

I

(Note 1) interrupt request to the application.

LOW

(Note 1)

HIGH

DMA Request. This signal requests the Endpoint FIFO to make a DMA transfer.

DMA Acknowledge Signal. This signal, when asserted, enables accessing

(Note 1) FIFOs, without address bus setting.

When ADSEL is HIGH, the address and CS on AD7:AD0 is latched at the

trailing edge of this signal. This signal is ignored when ADSEL is LOW.

I

—

When ADSEL is LOW, the address is input on A7:A0 and data i input on

D15:D8 and AD7:AD0. When ADSEL is HIGH, the lower bytes (LSB) of

address and data are multiplexed on AD7:AD0.

ADSEL

I

—

System Reset. When this signal is asserted LOW, the ML60851A is reset.

When the ML60851A is powered on, this signal must be asserted for 1 ms.

RESET

LOW

Note: 1. Initialvalueimmediatelyafterresetting. Itsassertioncanbechangedbyprogramming.

38/44

¡ Semiconductor

ML60851A

Functional Description

The ML60851A USB device controller contains the Protocol Engine, DPLL, Timer, Status/Control,

FIFO Control, Application Interface, and Remote Wakeup blocks.

• Protocol Engine

The Protocol Engine handles the USB communication protocol. It performs control of packet

transmission/reception,generation/detectionofsynchronouspatterns,CRCgeneration/checking,

NRZI data modulation, bit stuffing, and packet ID (PID) generation/checking.

• DPLL (Digital Phase Locked Loop)

The DPLL extracts clock and data from the USB differential received data (D+ and D–).

• Timer

The Timer block monitors idle time on the USB bus.

• Status/Control

The Status Control block moniors the transaction status and transmits control events to the

application through an interrupt request.

39/44

¡ Semiconductor

ML60851A

• FIFO Control

The FIFO Control block controls all FIFO operations for transmitting and receiving USB packets.

The FIFO configuration is described below.

Endpoint FIFO/8-Byte Setup Register Configuration

For Control Transfer

8-Byte

Endpoint Address 0

Setup Register

Setup Ready

8-Byte

EP0 Receive FIFO

EP0 Transmit FIFO

FIFO Rx

Packet Ready

8-Byte

Endpoint Address 0

FIFO Tx

Packet Ready

For Bulk Transfer

64-Byte

FIFO

Packet Ready

DMA Request

EP1 FIFO (128 bytes)

(Selectable for transmitter

or receiver)

64-Byte

FIFO

Endpoint Address 1

Endpoint Address 2

EP2 FIFO (64 bytes)

(Selectable for transmitter

or receiver)

64-Byte

FIFO

Packet Ready

8-Byte

FIFO

Endpoint Address 3

EP3 FIFO (8 bytes)

Packet Ready

FIFO type

Reception

Endpoint address

Program size

Function

0

1

2

3

8 Bytes

Transfer control

Bulk-In and bulk-Out

Bulk-Out and bulk-In

Interrupt

Transmission

8 Bytes

Reception/Transmission

Transmission

64 Bytes (2 levels)

64 Bytes

8 Bytes

Every FIFO has a flag that indicates a full or empty FIFO and the capability of re-transmitting and

re-receiving data. Endpoint addresses 1 and 2 can be used for either of reception and transmission

by writing the register.

The FIFO at endpoint address 1 can be used for DMA transfer.

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ML60851A

• Interrupt

Interrupt factors include Packet Ready for a transmit/receive FIFO, Setup Ready for 8-byte setup

data, and Suspend. Generation of each interrupt request can be enabled or disabled by the

Interrupt Enable register.

• DMA

8-bitand16-bitdemandtransferDMAandsingletransferDMAareenabledforbulk-transferFIFO

at endpoint address 1.

In Demand Transfer mode, DREQ is asserted when a valid packet arrives at the FIFO. When the

external DMA contoller has completed transferring all byte data of a received packet, DREQ is

deasserted. Accordingly, other devices cannot access the local bus during DMA transfer.

In Single Tranfer mode, each time transfer of one byte data is completed, DREQ is deasserted.

While DREQ is deasserted, other devices can access the local bus.

• Remote Wakeup

This functional block supports the remote wakeup function.

• USB Transfers

The ML60851A supports the two transfer types (Control Transfer and Bulk Transfer) of four

transfer types (Control, Isochronous, Interrupt, and Bulk) defined by the USB Specifications.

- TheControlTransferisrequiredfortransferofconfiguration,commands,andstatusinformation

between the host and devices.

- TheBulkTransferenablestransferofalargeamountofdatawhenthebusbandwidthisenough.

• USB Transceiver

The ML60851A contains an Oki's USB transceiver which converts internal unidirectional signals

into USB-compatible signals.

This enables the designer's application module to interface to the physical layer of the USB.

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ML60851A

EXAMPLE OF OSCILLATOR CIRCUIT

ML60851A

Rf

XIN

C2

L1

XOUT

C3

Crystal: HC-49U (KINSEKI, LTD)

C2 = 5 pF

C3 = 1000 pF

Rf = 1 MW

L1 = 2.2 mF

Note: The example indicated above is not guaranteed for circuit operation.

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¡ Semiconductor

PACKAGE DIMENSIONS

QFP44-P-910-0.80-2K

ML60851A

(Unit : mm)

Mirror finish

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

0.41 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which

are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the

product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

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¡ Semiconductor

ML60851A

(Unit : mm)

TQFP44-P-1010-0.80-K

Mirror finish

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

0.28 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which

are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the

product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

44/44

E2Y0002-28-41

NOTICE

1.

The information contained herein can change without notice owing to product and/or

technical improvements. Before using the product, please make sure that the information

being referred to is up-to-date.

2.

The outline of action and examples for application circuits described herein have been

chosen as an explanation for the standard action and performance of the product. When

planning to use the product, please ensure that the external conditions are reflected in the

actual circuit, assembly, and program designs.

3.

4.

When designing your product, please use our product below the specified maximum

ratings and within the specified operating ranges including, but not limited to, operating

voltage, power dissipation, and operating temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or

unexpected operation resulting from misuse, neglect, improper installation, repair, alteration

or accident, improper handling, or unusual physical or electrical stress including, but not

limited to, exposure to parameters beyond the specified maximum ratings or operation

outside the specified operating range.

5.

6.

Neither indemnity against nor license of a third party’s industrial and intellectual property

right, etc. is granted by us in connection with the use of the product and/or the information

and drawings contained herein. No responsibility is assumed by us for any infringement

of a third party’s right which may result from the use thereof.

The products listed in this document are intended for use in general electronics equipment

for commercial applications (e.g., office automation, communication equipment,

measurement equipment, consumer electronics, etc.). These products are not authorized

for use in any system or application that requires special or enhanced quality and reliability

characteristics nor in any system or application where the failure of such system or

application may result in the loss or damage of property, or death or injury to humans.

Such applications include, but are not limited to, traffic and automotive equipment, safety

devices, aerospace equipment, nuclear power control, medical equipment, and life-support

systems.

7.

Certain products in this document may need government approval before they can be

exported to particular countries. The purchaser assumes the responsibility of determining

thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir

own expense for these.

8.

9.

No part of the contents cotained herein may be reprinted or reproduced without our prior

permission.

MS-DOS is a registered trademark of Microsoft Corporation.

Printed in Japan

型号	制造商	描述	价格	文档
ML60851AGA	OKI	USB Device Controller	获取价格
ML60851ATB	OKI	USB Device Controller	获取价格
ML60851C	OKI	USB Device Controller	获取价格
ML60851CGA	OKI	USB Device Controller	获取价格
ML60851CTB	OKI	USB Device Controller	获取价格
ML60851D	OKI	USB Device Controller	获取价格
ML60851DGA	OKI	USB Bus Controller, CMOS, PQFP44, 0.80 MM PITCH, PLASTIC, QFP-44	获取价格
ML60851DTB	OKI	暂无描述	获取价格
ML60851E	OKI	USB Device Controller	获取价格
ML60851EGA	OKI	USB Device Controller	获取价格

ML60851A

ML60851A 概述

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