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ML7000-01MA

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品牌：OKI

描述：Single Rail CODEC

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概述
规格参数
数据手册

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ML7000-01MA 概述

Single Rail CODEC 单铁CODEC 编解码器

ML7000-01MA 规格参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	24
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	压伸定律：	A/MU-LAW
滤波器：	YES	JESD-30 代码：	R-PDSO-G24
长度：	15.95 mm	功能数量：	1
端子数量：	24	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-30 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	2.5 mm
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	PCM CODEC
温度等级：	OTHER	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.9 mm	Base Number Matches：	1

ML7000-01MA 数据手册

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E2U0062-18-84

Preliminary

This version: Aug. 1998

ML7000-01/02/03/ML7001-01/02/03

¡ Semiconductor

ML7000-01/02/03

ML7001-01/02/03

Single Rail CODEC

GENERAL DESCRIPTION

The ML7000/ML7001 are single-channel CMOS CODEC LSI devices for voice signals ranging

from 300 to 3400 Hz with filters for A/D and D/A conversion.

Designed especially for a single-power supply and low-power applications, the devices are

optimized for ISDN terminals, digital wireless systems, and digital PBXs.

The devices use the same transmission clocks as those used in the MSM7507.

With the differential analog signal outputs which can drive 60 W load, the devices can directly

drive a handset receiver.

FEATURES

• Single power supply: +5 V (ML7000-xx)

+3 V (ML7001-xx)

• Low power consumption

Operating mode:

25 mW Typ.

20 mW Typ.

= 5.0 V (ML7000-xx)

= 3.0 V (ML7001-xx)

= 5.0 V (ML7000-xx)

= 3.0 V (ML7001-xx)

Power-down mode: 0.05 mW Typ.

0.03 mW Typ.

• Conforms to ITU-T Companding law

ML7000-01/ML7001-01: m/A-law pin selectable

ML7000-02/ML7001-02: m-law

ML7000-03/ML7001-03: A-law

• Transmission characteristics conform to ITU-T G.714

• Short frame sync timing operation

• Built-in PLL eliminates a master clock

• Serial data rate: 64/96/128/192/200/256/384/512/

768/1024/1536/1544/2048 kHz

• Adjustable transmit gain

• Adjustable receive gain

• Built-in reference voltage supply

• Package options:

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: ML7000-01MA/ML7001-01MA)

(Product name: ML7000-02MA/ML7001-02MA)

(Product name: ML7000-03MA/ML7001-03MA)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: ML7000-01MB/ML7001-01MB)

(Product name: ML7000-02MB/ML7001-02MB)

(Product name: ML7000-03MB/ML7001-03MB)

1/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

BLOCK DIAGRAM

PCMOUT

TCONT

–

AIN–

AIN+

LPF

8th

BPF

A/D

CONV.

GSX

XSYNC

PLL

AUTO

ZERO

BCLK

SGC

GEN

RTIM

RSYNC

(ALAW)

5th

LPF

D/A

CONV.

–

VFRO

RCONT

PCMIN

PWI

–

AOUT–

PWD

PDN

V_DD

PWD

Logic

–

AOUT+

2/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

PIN CONFIGURATION (TOP VIEW)

SG 1

AOUT+ 2

AOUT– 3

NC 4

24 SGC

23 AIN+

22 AIN–

21 GSX

20 NC

SG 1

AOUT+ 2

AOUT– 3

PWI 4

20 SGC

19 AIN+

18 AIN–

17 GSX

PWI 5

VFRO 5

16 NC

V_DD

VFRO 6

NC 7

19 NC

15 (ALAW)*

14 AG

18 (ALAW)*

17 NC

DG 7

PDN 8

13 BCLK

12 XSYNC

11 PCMOUT

DG 9

PDN 10

16 AG

RSYNC 9

PCMIN 10

15 BCLK

14 XSYNC

13 PCMOUT

RSYNC 11

PCMIN 12

20-Pin Plastic SSOP

24-Pin Plastic SOP

* The ALAW pin is only supported by the ML7000-01MA/ML7000-01MB/ML7001-01MA/

ML7001-01MB.

NC : No connect pin

3/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

PIN FUNCTIONAL DESCRIPTION

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.

AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is

connected to the output of the op-amp.

The level adjustment should be performed using any of the methods shown below. During

power-saving and power-down modes, the GSX output is at AG voltage.

R1 : variable

R2 > 20 kW

C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

GSX

AIN–

AIN+

–

Analog input

R3 > 20 kW

AIN+

AIN–

GSX

–

Analog input

R4 > 20 kW

R5 > 50 kW

C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Analog ground.

VFRO

Receive filter output.

The output signal has an amplitude of 2.4 V for ML7000-xx and 2.0 V for ML7001-xx above

and below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMIN

and can drive a load of 20 kW or more.

For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO

and PWI.

During power-saving or power-down mode, the VFRO output is at an SG level.

Whenadjustingthereceivesignalonthebasisoffrequencycharacteristics, refertotheFrequency

Characteristics Adjustment Circuit.

4/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

PWI, AOUT+, AOUT–

PWI is connected to the inverting input of the receive driver.

The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be

adjusted with the pins VFRO, PWI, and AOUT–. During power-saving or power down-mode,

the outputs of AOUT+ and AOUT– are in a high impedance state. The output of AOUT+ is

inverted with respect to the output of AOUT–. Since these outputs provide differential drive of

an impedance of 1.2 kW, they can directly be connected to a handset using a piezoelectric

earphone or a line transformer. Refer to the application example.

R6 > 20 kW

ZL > 1.2 kW

VFRO

PWI

Receive filter

–

AOUT–

Gain = VO/VI = 2 5 R7/R6 £ 2

20 kW

AOUT+

20 kW

–

Power supply for +5 V (ML7000-xx) or +3 V (ML7001-xx)

PCMIN

PCM data input.

A serial PCM data input to this pin is converted to an analog signal in synchronization with the

RSYNC signal and BCLK signal.

The data rate of PCM is equal to the frequency of the BCLK signal.

PCM signal is shifted in at the falling edge of the BCLK signal and latched into the internal

The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signals.

The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048

kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power

saving state.

5/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

RSYNC

Receive synchronizing signal input.

Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive

synchronizing signal.

Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.

However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 6 to 9 kHz, but the electrical characteristics in this specification are not

guaranteed.

XSYNC

Transmit synchronizing signal input.

ThePCMoutputsignalfromthePCMOUTpinisoutputinsynchronizationwiththis signal. This

synchronizingsignaltriggersthePLLandsynchronizesalltimingsignalsofthetransmitsection.

This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section. However, if the frequency characteristic of

an applied system is not specified exactly, this device operates in the range of 6 to 9 kHz, but the

electrical characteristics in this specification are not guaranteed.

Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving

state.

6/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

Ground for the digital signal circuits.

This ground is separate from the analog signal ground AG. The DG pin must be connected to the

AG pin on the printed circuit board to make a common analog ground AG.

PDN

Power down control signal.

A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.

Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from

MSD in a sequential order.

MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK

and XSYNC.

This pin is in a high impedance state except during 8-bit PCM output. It is also in a high

impedance state during power saving or power down mode.

Apull-upresistormustbeconnectedtothispinbecauseitsoutputisconfiguredasanopendrain.

This device is compatible with the ITU-T recommendation on coding law and output coding

format.

The ML7000-03 (A-law) and ML7001-03 (A-law) output the character signal, inverting the even

bits.

PCMIN/PCMOUT

Input/Output Level

ML7000-02 (m-law)

ML7001-02 (m-law)

ML7000-03 (A-law)

ML7001-03 (A-law)

MSD

LSD MSD

LSD

+Full scale

–0

–Full scale

7/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

Signal ground voltage output.

The output voltage is 1/2 of the power supply voltage.

The output drive current capability is ±300 mA for ML7000-xx and ±200 mA for ML7001-xx.

This pin provides the SG level for CODEC peripherals.

This output voltage level is undefined during power-saving or power-down mode.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.

Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and

the SGC pin.

ALAW

Control signal input of the companding law selection.

Only the ML7000-01MA/ML7000-01MB/ML7001-01MA/ML7001-01MB have this pin. The

CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will operate

in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is

left open, since the pin is internally pulled down.

8/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Symbol

V_DD

Condition

Rating

Unit

—

–0.3 to +7

V_AIN

–0.3 to V_DD+ 0.3

V_DIN

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Operating Temperature

Analog Input Voltage

Symbol

V_DD

Condition

Min.

Typ.

5.00

3.00

+25

—

Max.

Unit

4.75

5.25

3.30

+85

—

2.70

–30

°C

—

2.4

V_AINConnect AIN– and GSX

V_PP

—

1.2

2.2

—

V_DD

High Level Input Voltage

Low Level Input Voltage

V_IH

XSYNC, RSYNC, BCLK,

0.45¥V_DD

—

V_DD

PCMIN, PDN, ALAW

V_IL

—

0.8

—

0.16¥V_DD

64, 96, 128, 192, 200, 256,

384, 512, 768, 1024, 1536,

1544, 2048

Clock Frequency

F_CBCLK

kHz

6.0

—

0.5

—

–10

8.0

—

9.0

10.0

Sync Pulse Frequency

F_SXSYNC, RSYNC (–40 to +75 °C)

D_CBCLK

Clock Duty Ratio

Digital Input Rise Time

Digital Input Fall Time

t_lr

t_lf

XSYNC, RSYNC, BCLK,

PCMIN, PDN

t_CXBCLKÆXSYNC, See Fig. 1

t_XCXSYNCÆBCLK, See Fig. 1

—

Transmit Sync Pulse Setting Time

—

XSYNC Setup Time

XSYNC Hold Time

t_XS

t_XH

—

t_CRBCLKÆRSYNC, See Fig. 1

t_RCRSYNCÆBCLK, See Fig. 1

—

Receive Sync Pulse Setting Time

—

RSYNC Setup Time

RSYNC Hold Time

PCMIN Setup Time

PCMIN Hold Time

t_RS

t_RH

t_DS

t_DH

—

R_DLPull-up resistor

—

Digital Output Load

C_DL

V_off

—

100

+10

+100

1000

Transmit gain stage, Gain = 0 dB

Transmit gain stage, Gain = +20 dB –100

XSYNC, RSYNC, BCLK

Analog Input Allowable DC Offset

Allowable Jitter Width

—

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

9/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

(ML7001-xx: V_DD= 2.7 V to 3.3 V, Ta = –30 to +85°C)

(ML7000-xx: V_DD= +5.0 V 5%, Ta = –30 to +85°C)

Parameter

Symbol

Condition

Min.

—

Typ.

5.0

Max.

12.0

10.0

4.0

Unit

Operating mode

No signal

V_DD= 5.0 V

V_DD= 3.0 V

I_DD1

—

6.5

Power-saving mode, PDN = 1,

XSYNC Æ OFF

—

1.5

Power Supply Current

I_DD2

I_DD3

V_IH

—

2.0

8.0

Power-down mode, PDN = 0,

BCLK OFF

—

0.01

0.05

2.2

0.45¥V_DD

0.0

—

0.2

—

V_DD

High Level Input Voltage

Low Level Input Voltage

—

0.8

V_IL

I_IH

—

0.0

0.16¥V_DD

2.0

High Level Input Leakage Current

Low Level Input Leakage Current

Digital Output Low Voltage

Digital Output Leakage Current

Input Capacitance

—

I_IH2ALAW

I_IL

—

30.0

0.5

—

V_OLPull-up resistor = 500 W

0.0

0.4

I_O

—

C_IN

—

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

10/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

Transmit Analog Interface Characteristics

(ML7001-xx: V_DD= 2.7 V to 3.3 V, Ta = –30 to +85°C)

(ML7000-xx: V_DD= +5.0 V 5%, Ta = –30 to +85°C)

Parameter

Input Resistance

Symbol

Condition

Min.

Typ.

—

Max.

—

Unit

R_INXAIN+, AIN–

R_LGXGSX with respect to SG

C_LGX

Output Load Resistance

Output Load Capacitance

—

–1.2

–0.7

–20

—

+1.2

+0.7

+20

Output Amplitude

Offset Voltage

V_OGX

V0p

—

V_OSGX

Gain = 1

—

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

Receive Analog Interface Characteristics

(ML7001-xx: V_DD= 2.7 V to 3.3 V, Ta = –30 to +85°C)

(ML7000-xx: V_DD= +5.0 V 5%, Ta = –30 to +85°C)

Parameter

Input Resistance

Symbol

Condition

Min.

Typ.

—

Max.

—

Unit

R_INPWPWI

R_LVFVFRO with respect to SG

—

Output Load Resistance

Output Load Capacitance

AOUT+, AOUT– (each) with

R_LAO

0.6

—

respect to SG

C_LVFVFRO

—

C_LAOAOUT+, AOUT–

VFRO, R_L= 20 kW with

–1.2

–1.0

–1.3

–1.0

–100

+1.2

+1.0

+1.3

+1.0

+100

V_OVF

respect to SG

Output Amplitude

Offset Voltage

V0p

AOUT+, AOUT–, R_L= 0.6 kW

V_OAO

with respect to SG

V_OSVFVFRO with respect to SG

AOUT+, AOUT–, Gain = 1 with

V_OSAO

–100

—

+100

respect to SG

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

11/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

AC Characteristics

(ML7001-xx: F_S= 8 kHz, V_DD= 2.7 V to 3.3 V, Ta = –30 to +85°C)

(ML7000-xx: F_S= 8 kHz, V_DD= +5.0 V 5%, Ta = –30 to +85°C)

Freq.

(Hz)

Level

(dBm0)

Parameter

Symbol

Condition Min.

Typ.

Max.

Unit

Loss T1

Loss T2

Loss T3

Loss T4

Loss T5

Loss T6

Loss R1

Loss R2

Loss R3

Loss R4

Loss R5

SD T1

SD T2

300

+0.07

Reference

–0.04

+0.07

0.4

—

–0.15

+0.2

1020

2020

3000

3400

300

Transmit Frequency Response

–0.15

+0.2

0.8

–0.15

–0.03

Reference

0.00

+0.2

1020

2020

3000

3400

Receive Frequency Response

–0.15

+0.2

0.8

—

+0.05

0.54

—

35.0

38.0

—

SD T3

SD T4

SD T5

–30

–40

–45

34.0

38.0

—

Transmit Signal to Distortion Ratio

1020

26.0

31.0

—

26.0

24.0

—

30.0

—

25.0

—

25.0

—

SD R1

SD R2

—

36.0

40.0

—

SD R3

SD R4

SD R5

–30

–40

–45

35.0

40.0

—

Receive Signal to Distortion Ratio

1020

25.0

32.0

—

26.0

25.0

—

32.0

—

27.0

—

27.0

—

GT T1

GT T2

GT T3

GT T4

GT T5

GT R1

GT R2

GT R3

GT R4

GT R5

–0.3

+0.01

Reference

–0.05

–0.08

–0.06

Reference

+0.08

+0.12

+0.15

+0.3

–10

–40

–50

–55

Transmit Gain Tracking

Receive Gain Tracking

1020

–0.3

–0.6

–1.2

–0.3

+0.3

+0.6

+1.2

+0.3

–10

–40

–50

–55

–0.3

–0.6

–1.2

+0.3

+0.6

+1.2

*1 Psophometric filter is used.

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

12/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

AC Characteristics (Continued)

(ML7001-xx: F_S= 8 kHz, V_DD= 2.7 V to 3.3 V, Ta = –30 to +85°C)

(ML7000-xx: F_S= 8 kHz, V_DD= +5.0 V 5%, Ta = –30 to +85°C)

Freq.

(Hz)

Level

(dBm0)

Parameter

Symbol

Condition Min.

Typ.

Max.

Unit

AIN = SG

*1 *2

—

–73.0

–69.5

–78.0

–75.0

–66.0

–65.0

–71.0

–65.0

Nidle T

NidleR

—

Idle Channel Noise

dBm0p

*1 *2

V_DD= 5.0 V,

Ta = 25°C

0.58

0.6007

0.35

0.622

0.362

AV T

AV R

V_DD= 3.0 V,

1020

Vrms

0.338

Ta = 25°C

Absolute Level (Initial Difference)

Absolute Level

0.58

0.6007

0.5

0.622

0.518

0.2

0.483

AV Tt V_DD= 5 V 5%, Ta = –30 to 85°C *3 –0.2

—

(Deviation of Temperature and Power) AV Rt V_DD= 2.7 to 3.3 V, Ta = –30 to 85°C *3 –0.2

A to A

—

0.2

Absolute Delay

1020

BCLK

—

0.6

= 64 kHz

t_GDT1

t_GDT2

t_GDT3

t_GDT4

t_GDT5

t_GDR1

500

600

—

0.19

0.11

0.02

0.05

0.07

0.00

0.09

0.12

–85

0.75

0.35

0.125

0.75

0.35

0.125

0.75

–75

Transmit Group Delay

1000

2600

2800

500

t_GDR2

600

Receive Group Delay

Crosstalk Attenuation

t_GDR3

1000

2600

2800

_GDR4

_GDR5

CR T

CR R

TRANS Æ RECV

RECV Æ TRANS

1020

–76

–70

*1 Psophometric filter is used.

*2 Input "0" code to PCMIN.

*3 AVR is defined at VFRO output.

*4 With respect to minimum value of the group delay distortion.

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

13/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

AC Characteristics (Continued)

(ML7001-xx: F_S= 8 kHz, V_DD= 2.7 V to 3.3 V, Ta = –30 to +85°C)

(ML7000-xx: F_S= 8 kHz, V_DD= +5.0 V 5%, Ta = –30 to +85°C)

Freq.

(Hz)

4.6 kHz to

72 kHz

300 to

3400

Level

(dBm0)

Parameter

Discrimination

Symbol

Condition Min.

Typ.

Max.

—

Unit

0 to

DIS

4000 Hz

4.6 kHz to

—

Out-of-band Spurious

–37.5

–52

–35

—

dBm0

100 kHz

fa = 470

fd = 320

0 to

Intermodulation Distortion

Power Supply Noise Rejection Ratio

Digital Output Delay Time

IMD

–4

2fa – fb

—

PSR T

Measured

50 mV_PP

PSR R 50 kHz

inband *5

C_L= 100 pF + 1 LSTTL

—

200

XD1

XD2

Pull-up resistor = 500 W

*5 Measured under idle channel noise.

14/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

TIMING DIAGRAM

PCM Data Input/Output Timing

Transmit Timing

BCLK

t_XSt_XH

t_CX

t_XC

t_XD1

XSYNC

t_XD2

MSD D2 D3 D4 D5 D6 D7 D8

PCMOUT

Receive Timing

BCLK

t_RSt_RH

t_CR

t_RC

RSYNC

t_DS

t_DH

MSD

PCMIN

Figure 1 Basic Timing

15/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

APPLICATION CIRCUIT

+ 5V

1 kW

ML7000-01

0.1 mF

51 kW

AIN–

PCMOUT

PCM signal output

XSYNC

8 kHz SYNC signal input

600 W

600:600

GSX

RSYNC

BCLK

AIN+

PCM shift clock input

PCM signal input

PCMIN

300 W

AOUT+

ALAW

Control of companding law

1: A-law

0: m-law

300 W

AOUT–

PWI

VFRO

0.1 mF

51 kW

PDN

Power down control input

1: Normal operation

0: Power down

SGC

10 mF

0 V

1 mF

+5 V

V_DD

0 to 20 W

+3 V

1 kW

ML7001-01

0.1 mF

51 kW

AIN–

PCMOUT

XSYNC

PCM signal output

8 kHz SYNC signal input

600 W

600:600

GSX

RSYNC

BCLK

AIN+

PCM shift clock input

PCM signal input

PCMIN

300 W

AOUT+

ALAW

Control of companding law

1: A-law

0: m-law

300 W

AOUT–

PWI

VFRO

51 kW 0.1 mF

1 mF

PDN

Power down control input

1: Normal operation

0: Power down

SGC

10 mF

0 V

+3 V

V_DD

0 to 20 W

16/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

NOTES ON USE

• Toensureproperelectricalcharacteristics,usebypasscapacitorswithexcellenthighfrequency

characteristics for the power supply and keep them as close as possible to the device pins.

• Connect the AG pin and the DG pin as closely as possible. Connect to the system ground with

low impedance.

• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the

use of IC socket is unavoidable, use the short lead type socket.

• When mounted on a frame, use electromagnetic shielding if any electromagnetic wave

sources such as power supply transformers surrounds the device.

• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-

up that may otherwise occur when power is turned on.

• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)

powersupplytoavoiderroneousoperationandthedegradationofthecharacteristicsofthese

devices.

17/19

¡ Semiconductor

PACKAGE DIMENSIONS

SOP24-P-430-1.27-K

ML7000-01/02/03/ML7001-01/02/03

(Unit : mm)

Mirror finish

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

0.58 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which

are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the

product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

18/19

¡ Semiconductor

ML7000-01/02/03/ML7001-01/02/03

(Unit : mm)

SSOP20-P-250-0.95-K

Mirror finish

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

0.18 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which

are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the

product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

19/19

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