ML7000-01MA [OKI]

Single Rail CODEC; 单铁CODEC
ML7000-01MA
元器件型号: ML7000-01MA
生产厂家: OKI ELECTRONIC COMPONETS    OKI ELECTRONIC COMPONETS
描述和应用:

Single Rail CODEC
单铁CODEC

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型号参数:ML7000-01MA参数
生命周期Obsolete
零件包装代码SOIC
包装说明SOP,
针数24
Reach Compliance Codeunknown
HTS代码8542.39.00.01
风险等级5.84
压伸定律A/MU-LAW
滤波器YES
JESD-30 代码R-PDSO-G24
长度15.95 mm
功能数量1
端子数量24
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-30 °C
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE
认证状态Not Qualified
座面最大高度2.5 mm
标称供电电压5 V
表面贴装YES
技术CMOS
电信集成电路类型PCM CODEC
温度等级OTHER
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
宽度7.9 mm
Base Number Matches1
MAX34334CSE前5页PDF页面详情预览
E2U0062-18-84
¡ Semiconductor
ML7000-01/02/03
ML7001-01/02/03
¡ Semiconductor
Single Rail CODEC
This version: Aug. 1998
ML7000-01/02/03/ML7001-01/02/03
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Pr
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GENERAL DESCRIPTION
The ML7000/ML7001 are single-channel CMOS CODEC LSI devices for voice signals ranging
from 300 to 3400 Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the devices are
optimized for ISDN terminals, digital wireless systems, and digital PBXs.
The devices use the same transmission clocks as those used in the MSM7507.
With the differential analog signal outputs which can drive 60
W
load, the devices can directly
drive a handset receiver.
FEATURES
• Single power supply: +5 V (ML7000-xx)
+3 V (ML7001-xx)
• Low power consumption
Operating mode:
25 mW Typ. V
DD
= 5.0 V (ML7000-xx)
20 mW Typ. V
DD
= 3.0 V (ML7001-xx)
Power-down mode: 0.05 mW Typ. V
DD
= 5.0 V (ML7000-xx)
0.03 mW Typ. V
DD
= 3.0 V (ML7001-xx)
• Conforms to ITU-T Companding law
ML7000-01/ML7001-01:
m/A-law
pin selectable
ML7000-02/ML7001-02:
m-law
ML7000-03/ML7001-03: A-law
• Transmission characteristics conform to ITU-T G.714
• Short frame sync timing operation
• Built-in PLL eliminates a master clock
• Serial data rate: 64/96/128/192/200/256/384/512/
768/1024/1536/1544/2048 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: ML7000-01MA/ML7001-01MA)
(Product name: ML7000-02MA/ML7001-02MA)
(Product name: ML7000-03MA/ML7001-03MA)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: ML7000-01MB/ML7001-01MB)
(Product name: ML7000-02MB/ML7001-02MB)
(Product name: ML7000-03MB/ML7001-03MB)
1/19
¡ Semiconductor
ML7000-01/02/03/ML7001-01/02/03
BLOCK DIAGRAM
AIN–
AIN+
GSX
+
RC
LPF
8th
BPF
A/D
CONV.
AUTO
ZERO
PCMOUT
TCONT
PLL
XSYNC
BCLK
SGC
SG
SG
GEN
VR
GEN
RTIM
RSYNC
(ALAW)
VFRO
PWI
AOUT–
+
5th
LPF
D/A
CONV.
RCONT
PCMIN
+
PWD
+
PWD
Logic
PDN
V
DD
AG
DG
AOUT+
2/19
¡ Semiconductor
ML7000-01/02/03/ML7001-01/02/03
PIN CONFIGURATION (TOP VIEW)
SG 1
AOUT+ 2
AOUT– 3
NC 4
PWI 5
VFRO 6
NC 7
V
DD
8
DG 9
PDN 10
RSYNC 11
PCMIN 12
* The ALAW pin is only supported by the ML7000-01MA/ML7000-01MB/ML7001-01MA/
ML7001-01MB.
NC : No connect pin


24 SGC
SG 1
20 SGC
23 AIN+
22 AIN–
21 GSX
20 NC
AOUT+ 2
AOUT– 3
PWI 4
19 AIN+
18 AIN–
17 GSX
16 NC
VFRO 5
V
DD
6
DG 7
19 NC
15 (ALAW)*
14 AG
18 (ALAW)*
17 NC
PDN 8
13 BCLK
16 AG
RSYNC 9
12 XSYNC
15 BCLK
PCMIN 10
11 PCMOUT
14 XSYNC
13 PCMOUT
20-Pin Plastic SSOP
24-Pin Plastic SOP
3/19
¡ Semiconductor
ML7000-01/02/03/ML7001-01/02/03
PIN FUNCTIONAL DESCRIPTION
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp.
The level adjustment should be performed using any of the methods shown below. During
power-saving and power-down modes, the GSX output is at AG voltage.
C1
Analog input
R1
R2
GSX
AIN–
AIN+
SG
+
R1 : variable
R2 > 20 kW
C1 > 1/(2
¥
3.14
¥
30
¥
R1)
C2
Analog input
R5
R4
R3
AIN+
AIN–
GSX
SG
+
R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2
¥
3.14
¥
30
¥
R5)
AG
Analog ground.
VFRO
Receive filter output.
The output signal has an amplitude of 2.4 V
PP
for ML7000-xx and 2.0 V
PP
for ML7001-xx above
and below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMIN
and can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
During power-saving or power-down mode, the VFRO output is at an SG level.
When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency
Characteristics Adjustment Circuit.
4/19
¡ Semiconductor
PWI, AOUT+, AOUT–
ML7000-01/02/03/ML7001-01/02/03
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. During power-saving or power down-mode,
the outputs of AOUT+ and AOUT– are in a high impedance state. The output of AOUT+ is
inverted with respect to the output of AOUT–. Since these outputs provide differential drive of
an impedance of 1.2 kW, they can directly be connected to a handset using a piezoelectric
earphone or a line transformer. Refer to the application example.
VI
VFRO
PWI
SG
20 kW
SG
+
AOUT–
20 kW
+
AOUT+
VO ZL
R6
R7
R6 > 20 kW
ZL > 1.2 kW
Receive filter
Gain = VO/VI = 2
5
R7/R6
£
2
V
DD
Power supply for +5 V (ML7000-xx) or +3 V (ML7001-xx)
PCMIN
PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
5/19
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