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ML9041-01ACVWA [OKI]

Dot Matrix LCD Driver, 17 X 100 Dots, CMOS, 10.62 X 2.55 MM, GOLD BUMP, DIE-189;
ML9041-01ACVWA
型号： ML9041-01ACVWA
厂家： OKI ELECTRONIC COMPONETS    OKI ELECTRONIC COMPONETS
描述：

Dot Matrix LCD Driver, 17 X 100 Dots, CMOS, 10.62 X 2.55 MM, GOLD BUMP, DIE-189

CD
文件： 总60页 (文件大小：538K)
中文：  中文翻译
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PEDL9041-03  
This version:  
Previous version: Dec. 1999  
Mar. 2001  
1
Semiconductor  
ML9041-xxA/xxB  
Preliminary  
DOT MATRIX LCD CONTROLLER DRIVER  
GENERAL DESCRIPTION  
The ML9041 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type  
dot matrix LCD.  
FEATURES  
•
•
•
•
•
•
Easy interfacing with 8-bit or 4-bit microcontroller  
Switchable between serial and parallel interfaces  
Dot-matrix LCD controller/driver for a small (5 × 7 dots) or large (5 × 10 dots) font  
Built-in circuit allowing automatic resetting at power-on  
Built-in 17 common signal drivers and 100 segment signal drivers  
Built-in character generation ROM capable of generating 160 small characters (5 × 7 dots) or 32 large  
characters (5 × 10 dots)  
•
Creation of character patterns by programming: up to 8 small character patterns (5 × 8 dots) or up to 4 large  
character patterns (5 × 11 dots)  
•
•
Built-in RC oscillation circuit using external or internal resistors  
Program-selectable duties: 1/9 duty (1 line: 5 × 7 dots + cursor + arbitrator), 1/12 duty (1 line: 5 × 10 dots +  
cursor + arbitrator), or 1/17 duty (2 lines: 5 × 7 dots + cursor + arbitrator)  
Built-in bias dividing resistors to drive the LCD  
Bi-directional transfer of segment outputs  
Bi-directional transfer of common outputs  
Equipped with a 100-dot arbitrator  
Display shifting on each line  
Built-in contrast control circuit  
Built-in voltage multiplier circuit  
•
•
•
•
•
•
•
•
Chip (Gold Bump)  
Product name: ML9041-xxA/xxB CVWA  
xxA: With dummy bumps on both sides of the chip  
xxB: Without dummy bumps on both sides of the chip  
*xx indicates a code number.  
*01A and 01B are general code numbers.  
1/60  
PEDL9041-03  
1
Semiconductor  
ML9041-xxA/xxB  
BLOCK DIAGRAM  
Segment Signal - driver  
100-bit latch  
100-bit shift register  
Parallel-  
serial  
converter  
2/60  
PEDL9041-03  
1
Semiconductor  
ML9041-xxA/xxB  
I/O CIRCUITS  
VDD  
P
VDD  
VDD  
VDD  
P
P
N
N
N
Applied to pins SSR, CSR,  
P
/S, and BEB  
Applied to pins T1, T2, and T3  
W
Applied to pins R/ , RS1, and RS0  
CS  
: 1 (  
: 0 (  
: 0  
= 0)  
= 1)  
: 0  
: 1  
At serial I/F  
At parallel I/F  
At serial I/F  
CS  
At parallel I/F  
Applied to pin E  
Applied to pin SI  
CS  
: 1 (  
CS  
: 0 (  
: 1  
= 1)  
= 0)  
At serial I/F  
: 0  
: 1  
At serial I/F  
At parallel I/F  
At parallel I/F  
SHT  
CS  
Applied to pin  
Applied to pin  
VDD  
VDD  
P
P
VDD  
N
P
N
Output Enable signal  
Applied to pins DB0 to DB7  
VDD  
VDD  
P
P
N
Output Enable signal  
Applied to pin SO  
3/60  
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ML9041-xxA/xxB  
PIN DESCRIPTIONS  
Symbol  
Description  
The input pin with a pull-up resistor to select Read (“H”) or Write (“L”) in the Parallel I/F  
Mode.  
W
R/  
This pin should be open in the Serial l/F Mode.  
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.  
RS1  
H
RS0  
H
Name of register  
Data register  
RS0, RS1  
H
L
Instruction register  
L
L
Expansion Instruction register  
This pin should be open in the Serial I/F Mode.  
The input pin for data input/output between the CPU and the ML9041 and for  
activating instructions in the Parallel l/F Mode.  
E
This pin should be open in the Serial l/F Mode.  
The input/output pins to transfer data of lower-order 4 bits between the CPU and the  
ML9041 in the Parallel l/F Mode. The pins are not used for the 4-bit interface and  
serial interface.  
DB0 to DB3  
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.  
The input/output pins to transfer data of upper 4 bits between the CPU and the  
ML9041 in the Parallel l/F Mode. The pins are not used for the serial interface.  
DB4 to DB7  
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F  
Mode when not used.  
The clock oscillation pins required for LCD drive signals and the operation of the  
ML9041 by instructions sent from the CPU.  
To input external clock, the OSC1 pin should be used. The OSCR and the OSC2 pins  
should be open.  
OSC1  
OSC2  
OSCR  
To start oscillation with an external resistor, the resistor should be connected between  
the OSC1 and OSC2 pins. The OSCR pin should be open.  
To start oscillation with an internal resistor, the OSC2 and OSCR pins should be  
short-circuited outside the ML9041. The OSC1 pin should be open.  
The LCD common signal output pins.  
COM1 to COM17  
SEG1 to SEG100  
For 1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For  
1/12 duty, non-selectable voltage waveforms are output via COM13 to COM17.  
The LCD segment signal output pins.  
4/60  
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ML9041-xxA/xxB  
Symbol  
CSR  
Description  
The input pin to select the transfer direction of the common signal output data.  
At 1/n duty, data is transferred from COM1 to COMn when “L” is applied to this pin and  
transferred from COMn to COM1 when “H” is applied to this pin.  
The input pin to select the transfer direction of the segment signal output data.  
“L”: Data transfer from SEG1 to SEG100  
SSR  
“H”: Data transfer from SEG100 to SEG1  
The pins to output bias voltages to the LCD.  
V1 , V2, V3A, V3B, V4  
For 1/4 bias : The V2 and V3B pins are shorted.  
For 1/5 bias : The V3A and V3B pins are shorted.  
The input pin to enable or disable the voltage multiplier circuit.  
"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.  
BEB  
VIN  
The voltage multiplier circuit doubles the input voltage VMUL and the multiplied voltage  
referenced to VDD is output to the V5IN pin. The voltage multiplier circuit can be used  
only when generating a level lower than GND.  
The pin to input voltage to the voltage multiplier.  
The pins to supply the LCD drive voltage.  
The LCD drive voltage is supplied to the V5 pin when the voltage multiplier is not used  
(BEB = 0) and the internal contrast adjusting circuit is also not used. At this time, the  
V5IN pin should be open.  
The LCD drive voltage is supplied to the V5IN pin when the voltage multiplier is not used  
(BEB = 0) but the internal contrast adjusting circuit is used. At this time, the V5 pin  
should be open.  
V5, V5IN  
When the voltage multiplier is used (BEB = 1), the V5 pin should be open (the  
multiplied voltage is output to the V5IN pin). In this case, the internal contrast adjusting  
circuit must be used. Capacitors for the voltage multiplier should be connected  
between the VDD pin and the V5IN pin.  
VC  
The pin to connect the positive pin of the capacitor for the voltage multiplier.  
The pin to connect the negative pin of the capacitor used for the voltage multiplier.  
VCC  
5/60  
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ML9041-xxA/xxB  
Symbol  
Description  
The input pins for test circuits (normally open). Each of these pins is equipped with a  
pull-down resistor, so this pin should be left open.  
T1, T2, T3  
VDD  
The power supply pin.  
GND  
The ground level input pin.  
The input pin to select the parallel or serial interface.  
“L” selects the parallel interface.  
“H” selects the serial interface.  
P
/S  
The pin to enable this IC in the serial l/F mode.  
“L” enables this IC.  
CS  
“H” disables this IC.  
This pin should be open in the parallel l/F mode.  
The pin to input shift clock in the serial l/F mode.  
Data inputting to the SI pin is carried out synchronizing with the rising edge of this  
clock signal.  
SHT  
Data outputting from the SO pin is carried out synchronizing with the falling edge of  
this clock signal.  
This pin should be open in the parallel l/F mode.  
The pin to input DATA in the serial l/F mode.  
SHT  
Data inputting to this pin is carried out synchronizing with the rising edge of the  
signal.  
Sl  
This pin should be open in the parallel l/F mode.  
The pin to output DATA in the serial l/F mode.  
SHT  
Data inputting to this pin is carried out synchronizing with the falling edge of the  
signal.  
SO  
This pin should be open in the parallel l/F mode.  
6/60  
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1
Semiconductor  
ML9041-xxA/xxB  
ABSOLUTE MAXIMUM RATINGS  
(GND = 0 V)  
Applicable pins  
VDD–GND  
Parameter  
Symbol  
VDD  
Condition  
Ta = 25°C  
Rating  
Unit  
V
Supply Voltage  
–0.3 to +6.5  
V1, V2, V3,  
V4, V5  
LCD Driving Voltage  
Ta = 25°C VDD–7.5 to VDD+0.3  
V
V1, V4, V5, V5IN, V2, V3A, V3B  
W
SHT  
P
R/ , E,  
SSR, Sl, RS0, RS1, BEB,  
T1 to T3, DB0 to DB7, VIN  
, CSR, /S,  
CS  
Input Voltage  
VI  
Ta = 25°C  
—
–0.3 to VDD+0.3  
–55 to +150  
V
,
Storage Temperature  
TSTG  
°C  
—
RECOMMENDED OPERATING CONDITIONS  
(GND = 0 V)  
Applicable pins  
VDD–GND  
DD–V5  
(V5IN  
Parameter  
Symbol  
VDD  
Condition  
—
Range  
Unit  
V
Supply Voltage  
2.5 to 5.5  
VDD–V5  
(See Note)  
V
LCD Driving Voltage  
—
2.8 to 7.0  
V
)
Voltage Multipler  
V
DD–1.40 to  
DD–3.5  
–40 to +85  
VMUL  
Top  
BEB = 1  
—
V
VDD–VIN  
V
Operating Voltage  
Operating Temperature  
°C  
—
Note: This voltage should be applied across VDD and V5. The following voltages are output to the V1, V2,  
V3A (V3B) and V4 pins:  
•
1/4 bias  
V1 = {VDD – (VDD – V5)/4} ±0.15 V  
V2 = V3B = {VDD – (VDD – V5)/2} ±0.15 V  
×
V4 = {VDD – 3 (VDD – V5)/4 } ±0.15 V  
•
1/5 bias  
V1 = {VDD – (VDD – V5)/5} ±0.15 V  
×
V2 = {VDD – 2 (VDD – V5)/5} ±0.15 V  
×
V3A = V3B = {VDD – 3 (VDD – V5)/5} ±0.15 V  
×
V4 = {VDD – 4 (VDD – V5)/5} ±0.15 V  
The voltages at the V1, V2, V3A (V3B), V4 and V5 pins should satisfy  
VDD > V1 > V2 > V3A (V3B) > V4 > V5.  
←
→
Lower)  
(Higher  
* Do not apply short-circuiting across output pins and across an output pin and an input/output  
pin or the power supply pin in the output mode.  
7/60  
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Semiconductor  
ML9041-xxA/xxB  
ELECTRICAL CHARACTERISTICS  
DC Characteristics  
(GND = 0 V, VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)  
Parameter  
Symbol  
VIH1  
Condition  
—
Min.  
Typ. Max. Unit Applicable pin  
W
“H” Input Voltage 1  
0.8VDD  
—
VDD  
R/ , RS0, RS1,  
E, DB0 to DB7,  
V
SHT P  
, /S, Sl,  
“L” Input Voltage 1  
VIL1  
–0.3  
—
0.2VDD  
CS  
“H” Input Voltage 2  
“L” Input Voltage 2  
“H” Output Voltage 1  
“L” Output Voltage 1  
“H” Output Voltage 2  
“L” Output Voltage 2  
VIH2  
VIL2  
0.8VDD  
—
—
—
—
—
—
VDD  
0.2VDD  
—
OSC1, SSR,  
CSR, BEB  
—
V
V
V
–0.3  
VOH1 IOH = –0.1 mA  
VOL1 IOL = +0.1 mA  
0.75VDD  
DB0 to DB7, SO  
OSC2  
—
0.9VDD  
0.2VDD  
—
µ
VOH2 IOH = –13 A  
µ
VOL2 IOL = +13 A  
—
0.1VDD  
VDD  
µ
VCH lOCH = –4 A  
VDD–0.3  
µ
VCMH lOCMH = ±4 A  
V
DD –V5 = 5 V V1–0.3  
V1+0.3  
V4+0.3  
V5+0.3  
VDD  
COM1 to  
COM17  
COM Voltage Drop  
V
V
Note 1  
V4–0.3  
µ
VCML lOCML = ±4 A  
µ
VCL  
lOCL = +4 A  
V5  
VDD–0.3  
µ
VSH lOSH = –4 A  
µ
VSMH lOSMH = ±4 A  
VDD –V5 = 5 V V2–0.3  
V2+0.3  
V3+0.3  
V5+0.3  
SEG1 to  
SEG100  
SEG Voltage Drop  
Note 1  
V3–0.3  
µ
VSML lOSML = ±4 A  
µ
VSL  
lOSL = +4 A  
V5  
E, SSR, CSR,  
SHT P  
µ
A
BEB,  
CS, Sl  
, /S,  
Input Leakage Current  
| IIL | VDD = 5 V, VIN = 5 V or 0 V  
VDD = 5 V, VIN = GND  
—
—
1.0  
61  
10  
25  
VDD = 5 V, VIN = VDD  
,
W
R/ , RS0, RS1,  
DB0 to DB7, SO  
µ
µ
Input Current 1  
Input Current 2  
| II1 |  
A
Excluding current flowing  
through the pull-up resistor  
and the output driving MOS  
—
—
2.0  
VDD = 5 V, VIN = VDD  
15  
—
—
45  
—
105  
2.0  
1.2  
VDD = 5 V, VIN = VDD  
,
| II2 |  
A
T1, T2, T3  
Excluding current flowing  
through the pull-down resistor  
Supply Current  
lDD  
VDD = 5 V  
Note 2  
—
mA VDD–GND  
DD, V1, V2,  
V3A, V3B, V4, V5  
V
Ω
k
LCD Bias Resistor  
RLB  
4.0  
Oscillation Frequency  
of External Resistor Rf  
Ω
fosc1 Rf = 180 k ±2%  
Note 3  
Note 4  
175  
140  
270  
270  
400  
480  
kHz OSC1, OSC2  
OSC1: Open  
Oscillation Frequency  
of Internal Resistor Rf  
OSC1, OSC2,  
fosc2  
kHz  
OSC2 and OSCR: Short-  
OSCR  
circuited  
OSC2, OSCR: Open  
Input from OSC1  
Clock Input  
Frequency  
fin  
fduty  
frf  
125  
45  
—
480  
55  
kHz  
Input Clock Duty  
Note 5  
Note 6  
Note 6  
50  
—
—
%
OSC1  
Input Clock Rise  
Time  
µ
0.2  
0.2  
s
s
µ
Input Clock Fall Time  
fff  
—
8/60  
PEDL9041-03  
1
Semiconductor  
ML9041-xxA/xxB  
(GND = 0 V, VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)  
Applicable  
Parameter  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
pins  
VDD = 5 V, 1/5 bias  
Maximum and  
minimum LCD  
drive voltages  
when internal  
variable resistors  
are used.  
VLCD  
MAX  
V5IN = 0 V,  
4.6  
—
V
VDD–V5  
Contrast data: 1F  
VDD = 5 V, 1/5 bias  
VLCD  
MIN  
V5IN = 0 V,  
—
3.4  
V
V
Contrast data: 00  
Bias Voltage for  
Driving LCD by  
External Input  
VLCD1  
VLCD2  
1/5 bias  
2.8  
2.8  
—
—
7.0  
7.0  
V5  
VDD–V5  
Note 7  
1/4 bias  
VDD = 3 V, VIN = 0 V  
f = 270 kHz  
Voltage Multiplier  
Output Voltage  
A capacitor for the voltage VDD–(VDD–VIN)  
VDD–(VDD–  
×
VIN) 2+1.2 V  
V5OUT  
—
V
V
V5, V5IN  
µ
×
multiplier = 4.7 F  
2–0.1  
No load  
BEB = H  
Voltage Multiplier  
Input Voltage  
VIN  
VDD–3.5 V  
VDD/2  
VIN  
Note 1: Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and any of the  
µ
common pins (COM1 to COM17) when the current of 4 A flows in or flows out at one common  
pin.  
Also applied to the voltage drop occurring between any of the VDD, V2, V3A (V3B) and V5 pins and  
µ
any of the segment pins (SEG1 to SEG100) when the current of 4 A flows in or flows out at one  
common pin.  
µ
The current of 4 A flows out when the output level is VDD or flows in when the output level is  
V5.  
Note 2: Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is  
fed to the internal Rf oscillation or OSC1 under the following conditions:  
VDD = 5 V  
GND = V5 = 0 V,  
V1, V2, V3A (V3B) and V4: Open  
E, SSR, CSR, and BEB: “L” (fixed)  
Other input pins: “L” or “H” (fixed)  
Other output pins: No load  
9/60  
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Semiconductor  
ML9041-xxA/xxB  
Note 3:  
Note 4:  
OSC1  
OSC1  
OSCR  
OSC2  
OSCR  
OSC2  
Ω±  
Rf = 180 k 2%  
The wire between OSC1 and Rf and the wire between  
OSC2 and Rf should be as short as possible.  
Keep OSCR open.  
The wire between OSC2 and OSCR should be as short  
as possible. Keep OSC1 open.  
Note 5:  
tHW  
tLW  
VDD  
2
VDD  
VDD  
2
2
fIN  
waveform  
Applied to the pulses entering from the OSC1 pin  
fduty = tHW/(tHW + tLW) ×100 (%)  
Note 6:  
0.7VDD  
0.3VDD  
0.7VDD  
0.3VDD  
trf  
tff  
Applied to the pulses entering from the OSC1 pin  
Note 7: For 1/4 bias, V2 and V3B pins are short-circuited. V3A pin is open.  
For 1/5 bias, V3A and V3B pins are short-circuited. V2 pin is open.  
10/60  
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Semiconductor  
ML9041-xxA/xxB  
Switching Characteristics (The following ratings are subject to change after ES evaluation.)  
Parallel Interface Mode  
•
The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2) are as shown below:  
1) WRITE MODE (Timing for input from the CPU)  
(VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)  
Parameter  
Symbol  
Min.  
40  
Typ.  
—
—
—
—
—
—
—
—
—
Max.  
—
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
W
R/ , RS0, RS1 Setup Time  
E Pulse Width  
tB  
tW  
tA  
tr  
450  
10  
—
W
R/ , RS0, RS1 Hold Time  
—
E Rise Time  
—
25  
25  
—
E Fall Time  
tf  
—
E Pulse Width  
tL  
tC  
tI  
430  
1000  
195  
10  
E Cycle Time  
—
DB0 to DB7 Input Data Hold Time  
DB0 to DB7 Input Data Setup Time  
—
tH  
—
VIH  
VIL  
VIH  
VIL  
RS1, RS0  
W
R/  
VIL  
tA  
VIL  
tr  
tf  
tB  
tW  
tL  
VIH  
VIH  
E
VIL  
VIL  
VIL  
tH  
tI  
Input  
Data  
VIH  
VIL  
VIH  
VIL  
DB0 to DB7  
tC  
11/60  
PEDL9041-03  
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Semiconductor  
ML9041-xxA/xxB  
2) READ MODE (Timing for output to the CPU)  
(VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)  
Parameter  
Symbol  
Min.  
40  
Typ.  
—
—
—
—
—
—
—
—
—
Max.  
—
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
W
R/ , RS1, RS0 Setup Time  
tB  
tW  
tA  
tr  
E Pulse Width  
450  
10  
—
W
R/ , RS1, RS0 Hold Time  
—
E Rise Time  
—
25  
25  
—
E Fall Time  
tf  
—
E Pulse Width  
tL  
tC  
tD  
tO  
430  
1000  
—
E Cycle Time  
—
DB0 to DB7 Output Data Delay Time  
DB0 to DB7 Output Data Hold Time  
350  
—
20  
VIH  
VIL  
VIH  
VIL  
RS1, RS0  
VIH  
VIH  
W
R/  
tr  
tf  
tB  
tW  
tA  
tL  
VIH  
tD  
VIH  
E
VIL  
tO  
VIL  
VIL  
VOH  
VOL  
VOH  
VOL  
Output  
Data  
DB0 to DB7  
tC  
12/60  
PEDL9041-03  
1
Semiconductor  
ML9041-xxA/xxB  
•
Serial Interface Mode  
Parameter  
(VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)  
Symbol  
tSCY  
tCSU  
tCH  
Min.  
500  
100  
100  
60  
Typ.  
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.  
—
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SHT  
CS  
CS  
SHT  
SHT  
SHT  
SHT  
SHT  
SHT  
Cycle Time  
Setup Time  
Hold Time  
—
—
Setup Time  
Hold Time  
tSSU  
tSH  
—
200  
200  
200  
—
—
“H” Pulse Width  
“L” Pulse Width  
Rise Time  
tSWH  
tSWL  
tSR  
—
—
50  
50  
—
Fall Time  
tSF  
—
Sl Setup Time  
tDISU  
tDIH  
tDOD  
tCDH  
100  
100  
—
Sl Hold Time  
—
Data Output Delay Time  
Data Output Hold Time  
160  
—
0
tSCY  
CS  
VIL  
tSR  
tSF  
tCSU  
tCH  
tSSU  
tSH  
VIH  
tSWL  
tSWH  
VIH  
SHT  
VIH  
tDIH  
VIH  
VIL  
VIL  
tDISU  
VIH  
VIL  
VIH  
VIL  
SI  
tDOD  
tDOD  
tCDH  
VOH  
VOH  
SO  
VOL  
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FUNCTIONAL DESCRIPTION  
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)  
These registers are selected by setting the level of the Register Selection input pins RS0 and RS1. The DR is  
selected when both RS0 and RS1 are “H”. The IR is selected when RS0 is “L” and RS1 is “H”. The ER is selected  
when both RS0 and RS1 are “L”. (When RS0 is “H” and RS1 is “L”, the ML9041 is not selected.)  
The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character  
generator RAM (CGRAM).  
The microcontroller (CPU) can write to the IR but cannot read from the IR.  
The ER stores a contrast adjusting code and sets the address code of the arbitrator RAM (ABRAM).  
The CPU can write to or read from the ER.  
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the  
DDRAM, AMRAM and CGRAM.  
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM.  
When an address code is written in the IR or ER, the data of the specified address is automatically transferred from  
the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked  
by allowing the CPU to read the data stored in the DR.  
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected  
to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next  
address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.  
Writing in or reading from these 3 registers is controlled by changing the status of the R/W (Read/Write) pin.  
Table 1 R/W pin status and register operation  
W
L
R/  
RS0  
L
RS1  
H
Operation  
Writing in the IR  
H
L
L
H
Reading the Busy flag (BF) and the address counter (ADC)  
Writing in the DR  
H
H
L
H
H
L
H
Reading from the DR  
L
Writing in the ER  
H
L
L
Reading the contrast code  
Busy Flag (BF)  
The status “1” of the Busy Flag (BF) indicates that the ML9041 is carrying out internal operation.  
When the BF is “1”, any new instruction is ignored.  
When R/W = “H”, RS0 = “L” and RS1 = “H”, the data in the BF is output to the DB7.  
New instructions should be input when the BF is “0”.  
When the BF is “1”, the output code of the address counter (ADC) is undefined.  
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Address Counter (ADC)  
The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a  
cursor display address.  
When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to the pre-defined  
register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the  
ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is  
written in or read from the DDRAM, ABRAM or CGRAM.  
The data in the ADC is output to DB0 to DB6 when R/W = “H”, RS0 = “L”, RS1 = “H” and BF = “0”.  
Timing Generator  
The timing generator generates timing signals for the internal operation of the ML9041 activated by the instruction  
sent from the CPU or for the operation of the internal circuits of the ML9041 such as DDRAM, ABRAM,  
CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for LCD displaying  
will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU  
writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.  
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Display Data RAM (DDRAM)  
This RAM stores the display data represented in 8-bit character coding (see Table 2).  
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM  
addresses (to be set in the ADC) are represented in hexadecimal.  
DB6 DB5 DB4 DB3 DB2 DB1 DB0  
ADC  
MSB  
LSB  
Hexadecimal  
Hexadecimal  
(Example) Representation of DDRAM address = 12  
ADC  
0
0
1
0
0
1
0
1
2
1) Relationship between DDRAM addresses and display positions (1-line display mode)  
Digit  
1
Display position  
2
3
4
5
19 20  
12 13  
DD RAM address (hexadecimal)  
00 01 02 03 04  
Left  
end  
Right  
end  
In the 1-line display mode, the ML9041 can display up to 20 characters from digit 1 to digit 20. While the  
DDRAM has addresses “00” to “4F” for up to 80 character codes, the area not used for display can be used as a  
RAM area for general data. When the display is shifted by instruction, the relationship between the LCD  
display and the DDRAM address changes as shown below:  
Digit  
1
2
3
4
19 20  
11 12  
(Display shifted to the right)  
4F 00 01 02  
Digit  
1
2
3
4
5
19 20  
13 14  
(Display shifted to the left) 01 02 03 04 05  
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2) Relationship between DDRAM addresses and display positions (2-line display mode)  
In the 2-line mode, the ML9041 can display up to 40 characters (20 characters per line) from digit 1 to digit 20.  
Digit  
1
2
3
4
5
19 20  
12 13  
Display position  
DD RAM  
Line 1  
Line 2  
00 01 02 03 04  
address (hexadecimal)  
40 41 42 43 44  
52 53  
Note: The DDRAM address at digit 20 in the first line is not consecutive to the DDRAM address at  
digit 1 in the second line.  
When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address  
changes as shown below:  
Digit  
1
2
3
4
5
19 20  
11 12  
Line 1  
Line 2  
27 00 01 02 03  
(Display shifted to the right)  
(Display shifted to the left)  
67 40 41 42 43  
51 52  
Digit  
1
2
3
4
5
19 20  
13 14  
Line 1  
Line 2  
01 02 03 04 05  
41 42 43 44 45  
53 54  
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Character Generator ROM (CGROM)  
The CGROM generates small character patterns (5 × 7 dots, 160 patterns) or large character patterns (5 × 10 dots,  
32 patterns) from the 8-bit character code signals in the DDRAM.  
When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the  
character pattern is displayed in the display position specified by the DDRAM address.  
Character codes 20 to 7F and A0 to FF are contained in the character code area in the CG ROM.  
Character codes 20 to 7F and A0 to DF are contained in the character code area for the 5 × 7-dot character patterns.  
Character codes E0 to FF are contained in the ROM area for 5 × 10-dot character patterns.  
The general character generator ROM codes are 01A/01B.  
The relationship between character codes and general purpose character patterns are indicated in Table2.  
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Character Generator RAM (CGRAM)  
The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes =  
512 bits) can store up to 8 small character patterns (5 × 8 dots) or up to 4 large character patterns (5 × 11 dots).  
When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F;  
hex.) assigned in Table 2 to the DDRAM. This enables outputting the character pattern to the LCD display  
position corresponding to the DDRAM address.  
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the  
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.  
The following describes how character patterns are written in and read from the CGRAM.  
1) Small character patterns (5 × 8 dots) (See Table 3-1.)  
(1) A method of writing character patterns to the CGRAM from the CPU  
The three CGRAM address bits 0 to 2 select one of the lines constituting a character pattern.  
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.  
Write each line of the character pattern code in the CGRAM through DB0 to DB7.  
The data lines DB0 to DB7 correspond to the CGRAM data bits 0 to 7, respectively (see Table 3-1). Input  
data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since the ADC is  
automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary  
to set the CGRAM address again.  
The bottom line of a character pattern (the CGRAM address bits 0 to 2 are all “1”, which means 7 in  
hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for  
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display  
the cursor.  
Whereas the data given by the CGRAM data bits 0 to 4 is output to the LCD as display data, the data given  
by the CGRAM data bits 5 to 7 is not. Therefore, the CGRAM data bits 5 to 7 can be used as a RAM area.  
(2) A method of displaying CGRAM character patterns on the LCD  
The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit 3 of a  
character code is not used, the character pattern “0” in Table 3-1 can be selected using the character code  
“00” or “08” in hexadecimal.  
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the  
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.  
(The DDRAM data bits 0 to 2 correspond to the CGRAM address bits 3 to 5, respectively.)  
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2) Large character patterns (5 × 11 dots) (See Table 3-2.)  
(1) A method of writing character patterns to the CGRAM from the CPU  
The four CGRAM address bits 0 to 3 select one of the lines constituting a character pattern.  
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.  
Write each line of the character pattern code in the CGRAM through DB0 to DB7.  
The data lines DB0 to DB7 correspond to the CGRAM data bits 0 to 7, respectively (see Table 3-2). Input  
data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since the ADC is  
automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary  
to set the CGRAM address again.  
The bottom line of a character pattern (the CGRAM address bits 0 to 3 are all “1”, which means A in  
hexadecimal) is a cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for  
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display  
the cursor.  
Whereas the data given by the CGRAM data bits 0 to 4 with the CGRAM addresses 0 to A in hexadecimal  
(set by the CGRAM address bits 0 to 3) is output as display data to the LCD, the data given by the  
CGRAM data bits 5 to 7 or the CGRAM addresses B to F in hexadecimal is not. These bits can be written  
and read as a RAM area.  
(2) A method of displaying CGRAM character patterns on the LCD  
The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bits 0 and 3  
of a character code are not used, the character pattern “β” in Table 3-2 can be selected with a character  
code “00”, “01”, “08” or “09” in hexadecimal.  
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the  
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.  
(The DDRAM data bits 1 and 2 correspond to the CGRAM address bits 4 and 5, respectively.)  
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Arbitrator RAM (ABRAM)  
The arbitrator RAM (ABRAM) stores arbitrator display data.  
The ABRAM address is set at the ADC with the relationship illustrated below. Its valid address area is 00 to 19  
(00H to 13H).  
Although an address exceeding 19 (13H) can be set or the address already set may exceed it due to automatic  
increment or decrement processing, any address out of the valid address area is ignored.  
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the  
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.  
DB6 DB5 DB4 DB3 DB2 DB1 DB0  
MSB  
ADC  
LSB  
Hexadecimal  
Hexadecimal  
The arbitrator RAM can store a maximum of 100 dots of the arbitrator Display-ON data in units of 5 dots.  
The arbitrator display is not shifted by any instructions and has the following relationship with the LCD display  
positions.  
Relationship between display-ON  
data and segment pins  
Configuration of input display data  
Input data  
5XSn+1  
5XSn+5  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
*
*
*
E4 E3 E2 E1 E0  
* Don’t Care  
E4  
E4  
Display - ON data  
Sn = AB RAM address (0 to 19)  
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Table 2 Relationship between Character Codes and Character Patterns of the ML9041-01A/01B  
(General Character Codes)  
The character code area in the CG ROM: Character codes 20H to 7FH, A0H to FFH.  
×
5 7-dot ROM area: 20H to 7FH, A0H to DFH  
×
5 10-dot ROM area: E0H to FFH  
The CG RAM area  
: Character codes 00H to 0FH  
00H:  
20H:  
28H: (  
29H: )  
2AH: *  
2BH: +  
2CH: ,  
2DH: -  
2EH: .  
2FH: /  
30H: 0  
31H: 1  
32H: 2  
33H: 3  
34H: 4  
35H: 5  
36H: 6  
37H: 7  
38H: 8  
39H: 9  
3AH: :  
3BH: ;  
3CH: <  
3DH: =  
3EH: >  
3FH: ?  
40H: @  
41H: A  
42H: B  
43H: C  
44H: D  
45H: E  
46H: F  
47H: G  
48H: H  
50H: P  
51H: Q  
52H: R  
53H: S  
54H: T  
55H: U  
56H: V  
57H: W  
08H:  
CG RAM(1) CG RAM(1)  
49H: I  
01H:  
09H:  
21H: !  
22H: "  
23H: #  
24H: $  
25H: %  
26H: &  
27H: '  
CG RAM(2) CG RAM(2)  
02H:  
0AH:  
4AH: J  
4BH: K  
4CH: L  
4DH: M  
4EH: N  
4FH: O  
CG RAM(3) CG RAM(3)  
03H:  
0BH:  
CG RAM(4) CG RAM(4)  
04H:  
0CH:  
CG RAM(5) CG RAM(5)  
05H:  
0DH:  
CG RAM(6) CG RAM(6)  
06H:  
0EH:  
CG RAM(7) CG RAM(7)  
07H:  
0FH:  
CG RAM(8) CG RAM(8)  
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Table 3-1 Relationship between CGRAM address bits, CGRAM data bits (character pattern)  
and DDRAM data bits (character code) in 5 × 7 dot character mode. (Examples)  
CG RAM  
address  
CG RAM data  
DD RAM data  
(Character pattern) (Character code)  
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  
5 4 3 2 1 0  
MSB  
LSB MSB  
LSB MSB  
0 1 1 1 0  
LSB  
×××  
0 0 0 0 0 0  
1 0 0 0 1  
1 0 0 0 1  
1 0 0 0 1  
1 0 0 0 1  
1 0 0 0 1  
0 1 1 1 0  
0 0 0 0 0  
1 0 0 0 1  
1 0 0 1 0  
1 0 1 0 0  
1 1 0 0 0  
1 0 1 0 0  
1 0 0 1 0  
1 0 0 0 1  
0 0 0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
×
0 0 0 0 0 0 0  
1 0 1  
1 1 0  
1 1 1  
×××  
0 0 1 0 0 0  
0 0 1  
0 1 0  
0 1 1  
0 0 0 0 0 0 1  
×
1 0 0  
1 0 1  
1 1 0  
1 1 1  
1 1 1 0 0 0 ×××  
0 0 1  
0 1 1 1 0  
0 0 1 0 0  
0 0 1 0 0  
0 0 1 0 0  
0 0 1 0 0  
0 0 1 0 0  
0 1 1 1 0  
0 0 0 0 0  
0 1 0  
0 1 1  
1 0 0  
0 0 0 0 × 1 1 1  
1 0 1  
1 1 0  
1 1 1  
×: Don’t Care  
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Table 3-2 Relationship between CGRAM address bits, CGRAM data bits (character pattern)  
and DDRAM data bits (character code) in 5 × 10 dot character mode (Examples)  
CG RAM CG RAM data  
address (Character pattern)  
DD RAM data  
(Character code)  
5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  
MSB  
LSB  
LSB MSB  
LSB MSB  
0 0 0 0 0 0 × × × 0 1 0 0 0  
0 0 0 1  
0 0 1 0  
0 0 1 1  
0 1 0 0  
0 1 0 1  
0 1 1 0  
0 1 1 1  
1 0 0 0  
1 0 0 1  
1 0 1 0  
1 0 1 1  
1 1 0 0  
1 1 0 1  
1 1 1 0  
1 1 1 1  
0 1 1 1 1  
1 0 0 1 0  
0 1 1 1 1  
0 1 0 1 0  
1 1 1 1 1  
0 0 0 1 0  
0 0 0 0 0  
0 0 0 0 0  
0 0 0 0 0  
0 0 0 0 0  
× × × × ×  
0 0 0 0 × 0 0 ×  
× × × 0 0 0 0 0  
0 0 0 0 0  
0 1 1 1 1  
1 0 0 0 1  
1 0 0 0 1  
1 0 0 0 1  
0 1 0 0 0 0  
0 0 0 1  
0 0 1 0  
0 0 1 1  
0 1 0 0  
0 1 0 1  
0 1 1 0  
0 1 1 1  
1 0 0 0  
1 0 0 1  
1 0 1 0  
1 0 1 1  
1 1 0 0  
1 1 0 1  
1 1 1 0  
1 1 1 1  
0 0 0 0 × 0 1 ×  
0 1 1 1 1  
0 0 0 0 1  
0 0 0 0 1  
0 1 1 1 0  
0 0 0 0 0  
× × × × ×  
1 1 0 0 0 0 × × × 0 0 0 0 0  
0 0 0 1  
0 0 1 0  
0 0 1 1  
0 1 0 0  
0 1 0 1  
0 1 1 0  
0 1 1 1  
1 0 0 0  
1 0 0 1  
1 0 1 0  
1 0 1 1  
1 1 0 0  
1 1 0 1  
1 1 1 0  
1 1 1 1  
0 0 0 0 0  
1 1 0 1 1  
0 1 0 1 0  
1 0 0 0 1  
1 0 0 0 1  
0 1 1 1 0  
0 0 0 0 0  
0 0 0 0 0  
0 0 0 0 0  
0 0 0 0 0  
× × × × ×  
0 0 0 0 × 1 1 ×  
×: Don’t Care  
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Cursor/Blink Control Circuit  
This circuit generates the cursor and blink of the LCD.  
The operation of this circuit is controlled by the program of the CPU.  
The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC  
(Address Counter).  
For example, when the ADC stores a value of “07” (hexadecimal), the cursor or blink is displayed as follows:  
DB6  
0
DB0  
1
ADC  
0
0
0
1
1
7
6
0
Digit  
1
2
3
4
5
7
8
9
19 20  
12 13  
In 1-line display mode  
00 01 02 03 04 05 06 07 08  
Cursor/blink position  
Digit  
1
2
3
4
5
6
7
8
9
19 20  
12 13  
First line  
00 01 02 03 04 05 06 07 08  
In 2-line display mode  
Second line 40 41 42 43 44 45 46 47 48  
52 53  
Cursor/blink position  
Note: The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in  
the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is  
holding a CGRAM or ABRAM address.  
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LCD Display Circuit (COM1 to COM17, SEG1 to SEG100, SSR and CSR)  
The ML9041 has 17 common signal outputs and 100 segment signal outputs to display 20 characters (in the 1-line  
display mode) or 40 characters (in the 2-line display mode).  
The character pattern is converted into serial data and transferred in series through the shift register.  
The transfer direction of serial data is determined by the SSR pin. The shift direction of common signals is  
determined by the CSR pin. The following tables show the transfer and shift directions:  
SSR  
L
Transfer direction  
→
SEG1  
SEG100  
→
H
SEG100  
SEG1  
CSR  
L
duty  
1/9  
AS bit  
Shift Direction  
Arbitrator’s common pin  
COM9  
→
L
H
L
COM1  
COM9  
→
L
1/9  
COM2  
COM9, COM1  
COM1  
→
L
1/12  
1/12  
1/17  
1/17  
1/9  
COM1  
COM12  
COM12  
COM1  
→
L
H
L
COM2  
COM12, COM1  
→
L
COM1  
COM17  
COM17  
COM1  
→
L
H
L
COM2  
COM17, COM1  
→
H
H
H
H
H
H
COM9  
COM1  
COM1  
→
1/9  
H
L
COM8  
COM1, COM9  
COM9  
→
1/12  
1/12  
1/17  
1/17  
COM12  
COM1  
COM1  
→
H
L
COM11  
COM1, COM12  
COM12  
COM1  
→
COM17  
COM1  
→
H
COM16  
COM1, COM17  
COM17  
* Refer to the Expansion Instruction Codes section about the AS bit.  
Signals to be input to the SSR and CSR pins should be determined at power-on and be kept unchanged.  
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Built-in Reset Circuit  
The ML9041 is automatically initialized when the power is turned on.  
During initialization, the Busy Flag (BF) is “1” and the ML9041 does not accept any instruction from the CPU  
(other than the Read BF instruction).  
The Busy Flag is “1” for about 15 ms after the VDD becomes 2.5 V or higher.  
During this initialization, the ML9041 performs the following instructions:  
1) Display clearing  
2) CPU interface data length = 8 bits  
3) 1-line LCD display  
4) Font size = 5 × 7 dots  
5) ADC counting = Increment  
6) Display shifting = None  
7) Display = Off  
8) Cursor = Off  
9) Blinking = Off  
10) Arbitrator = Displayed in the lower line  
11) Setting 1FH (hexadecimal) to the Contrast Data  
(DL = “1”)  
(N = “0”)  
(F = “0”)  
(I/D = “1”)  
(S = “0”)  
(D = “0”)  
(C = “0”)  
(B = “0”)  
(AS = “0”)  
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the  
built-in reset circuit may not work properly. In such a case, initialize the ML9041 with the instructions from the  
CPU. The use of a battery always requires such initialization from the CPU. (See “Initial Setting of Instructions”)  
2.5 V  
0.2 V  
0.2 V  
0.2 V  
tON  
tOFF  
≤
1 ms tOFF  
≤
≤
0.1 ms tON 100 ms  
Figure 1 Power-on and Power-off Waveform  
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I/F with CPU  
Parallel interface mode  
The ML9041 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit  
microcontroller (CPU).  
1) 8-bit interface data length  
The ML9041 uses all of the 8 data bus lines DB0 to DB7 at a time to transfer data to and from the CPU.  
2) 4-bit interface data length  
The ML9041 uses only the higher-order 4 data bus lines DB4 to DB7 twice to transfer 8-bit data to and from the  
CPU.  
The ML9041 first transfers the higher-order 4 bits of 8-bit data (DB4 to DB7 in the case of 8-bit interface data  
length) and then the lower-order 4 bits of the data (DB0 to DB3 in the case of 8-bit interface data length).  
The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4  
bits of data is required. (Example: Reading the Busy Flag)  
Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is  
made, the following data transfer cannot be completed properly.  
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RS1  
RS0  
W
R/  
E
Busy  
(Internal operation)  
No  
Busy  
DR7  
IR7  
IR6  
IR5  
IR4  
IR3  
IR2  
DB7  
Busy  
ADC6  
ADC5  
ADC4  
ADC3  
ADC2  
DR6  
DR5  
DR4  
DR3  
DR2  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1  
DB0  
ADC1  
ADC0  
IR1  
IR0  
DR1  
DR0  
Writing In IR  
(Instruction  
Register)  
Reading BF (Busy Flag)  
and ADC (Address Counter)  
Writing In DR  
(Data Register)  
Figure 2 8-Bit Data Transfer  
RS1  
RS0  
W
R/  
E
Busy  
(Internal operation)  
DB7  
No  
Busy  
IR7  
IR6  
IR5  
IR4  
IR3  
ADC3  
DR7  
DR6  
DR3  
DR2  
Busy  
ADC6  
ADC5  
ADC4  
IR2  
IR1  
IR0  
ADC2  
ADC1  
ADC0  
DB6  
DB5  
DB4  
DR5  
DR4  
DR1  
DR0  
Writing In IR  
(Instruction  
Register)  
Reading BF (Busy Flag)  
and ADC (Address Counter)  
Writing In DR  
(Data Register)  
Figure 3 4-Bit Data Transfer  
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Serial Interface Mode  
In the Serial I/F Mode, the ML9041 interfaces with the CPU via the CS, SHT, SI and SO pins.  
Writing and reading operations are executed in units of 16 bits after the CS signal falls down. If the CS signal rises  
up before the completion of 16-bit unit access, this access is ignored.  
When the BF bit is “1”, the ML9041 cannot accept any other instructions. Before inputting a new instruction,  
check that the BF bit is “0”. Any access when the BF bit is “1” is ignored.  
Data format is LSB-first.  
Examples of Access in the Serial I/F Mode  
1) WRITE MODE  
CS  
1
1
2
1
3
1
4
1
5
1
6
7
8
9
10 11 12 13 14 15 16  
SHT  
SI  
RS0 RS1 D0 D1 D2 D3 D4 D5 D6 D7  
W
R/  
SO  
2) READ MODE  
CS  
1
1
2
1
3
1
4
1
5
1
6
7
8
9
10 11 12 13 14 15 16  
SHT  
SI  
RS0 RS1  
W
R/  
D0 D1 D2 D3 D4 D5 D6 D7  
SO  
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Instruction Codes  
Table of Instruction Codes  
Execution  
Time  
f = 270 kHz  
Code  
Instruction  
Function  
RS1 RS0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
Clears all the displayed digits of the  
LCD and sets the DDRAM address 0 in  
the address counter. The arbitrator  
data is cleared.  
Display Clear  
Cursor Home  
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
S
1.52 ms  
1.52 ms  
37 µs  
Sets the DDRAM address 0 in the  
address counter and shifts the display  
back to the original. The content of the  
DDRAM remains unchanged.  
Determines the direction of movement  
of the cursor and whether or not to shift  
the display. This instruction is  
Entry Mode  
Setting  
0
1
1
I/D  
executed when data is written or read.  
Sets LCD display ON/OFF (D), cursor  
ON/OFF or cursor-position character  
blinking ON/OFF.  
Display  
ON/OFF Control  
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
1
D
C
X
X
B
X
X
37 µs  
37 µs  
37 µs  
37 µs  
37 µs  
0 µs  
Moves the cursor or shifts the display  
without changing the content of the  
DDRAM.  
Cursor/Display  
Shift  
S/C R/L  
Sets the interface data length (DL), the  
number of display lines (N) or the type  
of character font (F).  
Function Setting  
0
DL  
N
F
Sets on CGRAM address. After that,  
CGRAM data is transferred to and from  
the CPU.  
CGRAM  
Address Setting  
0
ACG  
Sets a DDRAM address. After that,  
DDRAM data is transferred to and from  
the CPU.  
DDRAM  
Address Setting  
1
ADD  
ADC  
Reads the Busy Flag (indicating that  
the ML9041 is operating) and the  
content of the address counter.  
Busy Flag/  
Address Read  
BF  
Writes data in DDRAM, ABRAM or  
CGRAM.  
RAM Data Write  
RAM Data Read  
1
1
0
0
0
1
1
0
0
0
0
1
0
0
1
WRITE DATA  
READ DATA  
37 µs  
37 µs  
37 µs  
37 µs  
37 µs  
Reads data from DDRAM, ABRAM or  
CGRAM.  
Arbitrator  
Display Line Set  
0
0
0
0
0
0
0
1
0
0
0
0
1
AS Sets the arbitrator display line.  
Contrast Control  
Data Write  
WRITE (Contrast Data) Writes data to control the contrast of  
DATA the LCD.  
READ (Contrast Data) Reads data to control the contrast of  
Contrast Control  
Data Read  
DATA  
the LCD.  
Sets an ABRAM address. After that,  
ABRAM data is transferred to and from  
the CPU.  
ABRAM  
Address Setting  
0
0
0
0
1
1
AAB  
37 µs  
I/D = “1” (Increment)  
I/D = “0” (Decrement)  
DD RAM: Display data RAM  
The  
S = “1” (Shifts the display.)  
S/C = “1”(Shifts display.)  
R/L = “1” (Right shift)  
D/L = “1” (8-bit data)  
N = “1” (2 lines)  
execution  
time is  
dependent  
upon  
frequen-  
cies.  
CG RAM: Character generator RAM  
ABRAM: Arbitrator data RAM  
S/C = “0” (Moves the cursor.)  
R/L = “0” (Left shift)  
DL = “0” (4-bit data)  
N = “0” (1 line)  
F = “0” (5 x 7 dots)  
BF = “0” (Ready to accept  
an instruction)  
ACG:  
ADD:  
CGRAM address  
DDRAM address  
(Corresponds to the cursor  
address)  
F = “1” (5 x 10 dots)  
BF = “1” (Busy)  
—
AAB:  
ADC:  
ABRAM address  
B = “1” (Enables blinking)  
C = “1” (Displays the cursor.)  
D = “1” (Displays a character pattern.)  
AS = “1” (Arbitrator Displays AS = “0” (Arbitrator Displays  
Address counter (Used by  
DDRAM, ABRAM and  
CGRAM)  
arbitrator on the  
upper line)  
arbitrator on the  
lower line)  
×: Don't Care  
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Instruction Codes  
An instruction code is a signal sent from the CPU to access the ML9041. The ML9041 starts operation as  
instructed by the code received. The busy status of the ML9041 is rather longer than the cycle time of the CPU,  
since the internal processing of the ML9041 starts at a timing which does not affect the display on the LCD. In the  
busy status (Busy Flag is “1”), the ML9041 executes the Busy Flag Read instruction only. Therefore, the CPU  
should ensure that the Busy Flag is “0” before sending an instruction code to the ML9041.  
1) Display Clear  
RS1  
1
RS0  
0
R/W  
DB7  
0
DB6  
0
DB5  
0
DB4  
0
DB3  
0
DB2  
0
DB1  
0
DB0  
1
0
Instruction Code:  
When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry  
mode is set to “Increment”. The value of “S” (Display shifting) remains unchanged. The position of the cursor  
or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display  
mode).  
Note: All DDRAM and ABRAM data turn to “20” and “00” in hexadecimal, respectively. The value of the  
address counter (ADC) turns to the one corresponding to the address “00” (hexadecimal) of the  
DDRAM.  
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.  
2) Cursor Home  
RS1  
1
RS0  
0
R/W  
DB7  
0
DB6  
0
DB5  
0
DB4  
0
DB3  
0
DB2  
0
DB1  
1
DB0  
0
×
Instruction code:  
×
: Don’t Care  
When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end  
of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display  
position before shifting.  
Note: The value of the address counter (ADC) goes to the one corresponding to the address “00”  
(hexadecimal) of the DDRAM).  
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.  
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3) Entry Mode Setting  
RS1  
1
RS0  
0
R/W  
DB7  
0
DB6  
0
DB5  
0
DB4  
0
DB3  
0
DB2  
1
DB1  
I/D  
DB0  
S
0
Instruction code:  
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= “1”; increment) or to  
the left by 1 character position (I/D= “0”; decrement) after an 8-bit character code is written to or read  
from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D =  
“1”; increment) or decremented by 1 (when I/D = “0”; decrement). After a character pattern code is  
written to or read from the CGRAM, the address counter (ADC) is incremented by 1 (when I/D = “1”;  
increment) or decremented by 1 (when I/D = “0”; decrement).  
Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented by 1  
(when I/D = “1”; increment) or decremented by 1 (when I/D = “0”; decrement).  
(2) When S = “1”, the cursor or blink stops and the entire display shifts to the left (I/D = “1”) or to the right  
(I/D = “0”) by 1 character position after a character code is written to the DDRAM.  
In the case of S = “1”, when a character code is read from the DDRAM, when a character pattern data is  
written to or read from the CGRAM or when data is written to or read from the ABRAM, normal  
read/write is carried out without shifting of the entire display. (The entire display does not shift, but the  
cursor or blink shifts to the right (I/D = “1”) or to the left (I/D = “0”) by 1 character position.)  
When S = “0”, the display does not shift, but normal write/read is performed.  
Note: The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of  
270 kHz.  
4) Display Mode Setting  
RS1  
1
RS0  
0
R/W  
DB7  
0
DB6  
0
DB5  
0
DB4  
0
DB3  
1
DB2  
D
DB1  
C
DB0  
B
0
Instruction code:  
(1) The “D” bit (DB2) of this instruction determines whether or not to display character patterns on the LCD.  
When the “D” bit is “1”, character patterns are displayed on the LCD.  
When the “D” bit is “0”, character patterns are not displayed on the LCD and the cursor/blink setting is  
also canceled.  
Note: Unlike the Display Clear instruction, this instruction does not change the character code in the  
DDRAM and ABRAM.  
(2) When the “C” bit (DB1) is “0”, the cursor turns off. When both the “C” and “D” bits are “1”, the cursor  
turns on.  
(3) When the “B” bit (DB0) is “0”, blinking is canceled. When both the “B” and “D” bits are “1”, blinking is  
performed.  
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are  
alternately displayed.  
Note: The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of  
270 kHz.  
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5) Cursor/Display Shift  
RS1  
1
RS0  
0
R/W  
DB7  
0
DB6  
0
DB5  
0
DB4  
1
DB3  
S/C  
DB2  
R/L  
DB1  
DB0  
0
×
×
Instruction code:  
×
: Don’t Care  
S/C = “0”, R/L = “0”  
S/C = “0”, R/L = “1”  
S/C = “1”, R/L = “0”  
This instruction shifts left the cursor and blink positions by 1 (decrements the  
content of the ADC by 1).  
This instruction shifts right the cursor and blink positions by 1 (increments the  
content of the ADC by 1).  
This instruction shifts left the entire display by 1 character position. The cursor  
and blink positions move to the left together with the entire display.  
The Arbitrator display is not shifted.  
(The content of the ADC remains unchanged.)  
S/C = “1”, R/L = “1”  
This instruction shifts right the entire display by 1 character position. The cursor  
and blink positions move to the right together with the entire display.  
The Arbitrator display is not shifted.  
(The content of the ADC remains unchanged.)  
In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40  
(27; hex) of the first line is shifted right.  
When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from  
line 1 to line 2 or vice versa).  
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.  
6) Function Setting  
RS1  
1
RS0  
0
R/W  
DB7  
0
DB6  
0
DB5  
1
DB4  
DL  
DB3  
N
DB2  
F
DB1  
DB0  
0
×
×
Instruction code:  
×
: Don’t Care  
(1) When the “DL” bit (DB4) of this instruction is “1”, the data transfer to and from the CPU is performed  
once by the use of 8 bits DB7 to DB0.  
When the “DL” bit (DB4) of this instruction is “0”, the data transfer to and from the CPU is performed  
twice by the use of 4 bits DB7 to DB4.  
(2) The 2-line display mode is selected when the “N” bit (DB3) of this instruction is “1”. The 1-line display  
mode is selected when the “N” bit is “0”.  
(3) The character font represented by 5 × 7 dots is selected when the “F” bit (DB2) of this instruction is “1”.  
The character font represented by 5 × 10 dots is selected when the “F” bit is “1” and the “N” bit is “0”.  
After the ML9041 is powered on, this initial setting should be carried out before execution of any  
instruction except the Busy Flag Read. After this initial setting, no instructions other than the DL Set  
instruction can be executed. In the Serial I/F Mode, DL setting is ignored.  
Number of  
display lines  
Number of  
biases  
Number of  
common signals  
N
F
Font size  
Duty  
×
0
0
1
1
0
1
0
1
1
1
2
2
5
7
10  
7
1/9  
4
4
5
5
9
×
5
1/12  
1/17  
1/17  
12  
17  
17  
×
×
5
5
7
µ
Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of  
270 kHz.  
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7) CGRAM Address Setting  
RS1  
RS0  
0
R/W  
DB7  
0
DB6  
1
DB5  
C5  
DB4  
C4  
DB3  
C3  
DB2  
C2  
DB1  
C1  
DB0  
C0  
1
0
Instruction code:  
This instruction sets the character data corresponding to the CGRAM address represented by the bits C5 to C0  
(binary).  
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.  
The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to  
C0 set in the instruction code at that time.  
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.  
8) DDRAM Address Setting  
RS1  
1
RS0  
0
R/W  
DB7  
1
DB6  
D6  
DB5  
D5  
DB4  
D4  
DB3  
D3  
DB2  
D2  
DB1  
D1  
DB0  
D0  
0
Instruction code:  
This instruction sets the character data corresponding to the DDRAM address represented by the bits D6 to D0  
(binary).  
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.  
The CPU writes or reads character patterns starting from the one represented by the DDRAM address bits D6 to  
D0 set in the instruction code at that time.  
In the 1-line mode (the “N” bit is “1”), the DDRAM address represented by bits D6 to D0 (binary) should be in  
the range “00” to “4F” in hexadecimal.  
In the 2-line mode (the “N” bit is “2”), the DDRAM address represented by bits D6 to D0 (binary) should be in  
the range “00” to “27” or “40” to “67” in hexadecimal.  
If an address other than above is input, the ML9041 cannot properly write a character code in or read it from the  
DDRAM.  
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.  
9) DDRAM/ABRAM/CGRAM Data Write  
RS1  
1
RS0  
1
R/W  
DB7  
E7  
DB6  
E6  
DB5  
E5  
DB4  
E4  
DB3  
E3  
DB2  
E2  
DB1  
E1  
DB0  
E0  
0
Instruction code:  
This instruction writes data represented by bits E7 to E0 (binary) to DDRAM, ABRAM or CGRAM.  
After data is written, the cursor, blink or display shifts according to the Cursor/Display Shift instruction (see  
5)).  
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.  
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10) Busy Flag/Address Counter Read (Execution time: 1 µs)  
RS1  
1
RS0  
0
R/W  
DB7  
BF  
DB6  
O6  
DB5  
O5  
DB4  
O4  
DB3  
O3  
DB2  
O2  
DB1  
O1  
DB0  
O0  
1
Instruction code:  
The “BF” bit (DB7) of this instruction tells whether the ML9041 is busy in internal operation (BF = “1”) or not  
(BF = “0”).  
When the “BF” bit is “1”, the ML9041 cannot accept any other instructions. Before inputting a new instruction,  
check that the “BF” bit is “0”.  
When the “BF” bit is “0”, the ML9041 outputs the correct value of the address counter. The value of the  
address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and  
CGRAM addresses is set in the counter is determined by the preceding address setting.  
When the “BF” bit is “1”, the value of the address counter is not always correct because it may have been  
incremented or decremented by 1 during internal operation.  
11) DDRAM/ABRAM/CGRAM Data Read  
RS1  
1
RS0  
1
R/W  
DB7  
P7  
DB6  
P6  
DB5  
P5  
DB4  
P4  
DB3  
P3  
DB2  
P2  
DB1  
P1  
DB0  
P0  
1
Instruction code:  
A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a  
character pattern (P7 to P0) from the CGRAM.  
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.  
After data is read, the address counter (ADC) is incremented or decremented as set by the Transfer Mode  
Setting instruction (see 3).  
Note: Conditions for reading correct data  
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.  
(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input  
before this Data Read instruction is input.  
(3) When two or more consecutive RAM Data Read instructions are executed, the following read data is  
correct.  
Correct data is not output under conditions other than the cases (1), (2) and (3) above.  
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.  
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Expansion Instruction Codes  
The busy status of the ML9041 is rather longer than the cycle time of the CPU, since the internal processing of the  
ML9041 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is “1”), the  
ML9041 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is  
“0” before sending an expansion instruction code to the ML9041.  
1) Arbitrator Display Line Set  
RS1  
0
RS0  
0
R/W  
DB7  
0
DB6  
0
DB5  
0
DB4  
0
DB3  
0
DB2  
0
DB1  
1
DB0  
AS  
0
Expansion instruction code:  
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit  
and the common outputs is as follows:  
For display examples, refer to LCD Drive Waveforms section.  
CSR  
L
duty  
1/9  
AS bit  
Shift direction  
Arbitrator’s common pin  
COM9  
→
COM1 COM9  
L
H
L
→
L
1/9  
COM2 COM9, COM1  
COM1  
→
L
1/12  
1/12  
1/17  
1/17  
1/9  
COM1 COM12  
COM12  
COM1  
→
COM2 COM12, COM1  
L
H
L
→
L
COM1 COM17  
COM17  
COM1  
→
COM2 COM17, COM1  
L
H
L
→
H
H
H
H
H
H
COM9 COM1  
COM1  
→
1/9  
H
L
COM8 COM1, COM9  
COM9  
→
1/12  
1/12  
1/17  
1/17  
COM12 COM1  
COM1  
→
H
L
COM11 COM1, COM12  
COM12  
COM1  
→
COM17 COM1  
→
H
COM16 COM1, COM17  
COM17  
2) Contrast Adjusting Data Write  
RS1  
RS0  
0
R/W  
DB7  
0
DB6  
0
DB5  
1
DB4  
F4  
DB3  
F3  
DB2  
F2  
DB1  
F1  
DB0  
F0  
0
0
Expansion instruction code:  
This instruction writes contrast adjusting data (F4 to F0) to the contrast register.  
After contrast adjusting data is written in the register, the potential (VLCD) output to the V5 pin varies  
according to the data written.  
The VLCD becomes maximum when the content of the contrast register is “1F” (hexadecimal) and becomes  
minimum when it is “00” (hexadecimal).  
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.  
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3) Contrast Adjusting Data Read  
RS1  
RS0  
0
R/W  
DB7  
0
DB6  
0
DB5  
0
DB4  
G4  
DB3  
G3  
DB2  
G2  
DB1  
G1  
DB0  
G0  
0
1
Expansion instruction code:  
This instruction reads contrast adjusting data (G4 to G0) from the contrast register.  
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.  
4) ABRAM Address Setting  
RS1  
0
RS0  
0
R/W  
DB7  
0
DB6  
1
DB5  
1
DB4  
H4  
DB3  
H3  
DB2  
H2  
DB1  
H1  
DB0  
H0  
1
Expansion instruction code:  
This instruction sets the character data corresponding to the ABRAM address represented by the bits H4 to H0  
(binary).  
The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.  
The CPU writes or reads character patterns starting from the one represented by the ABRAM address bits H4 to  
H0 set in the instruction code at that time.  
The ABRAM address represented by bits H4 to H0 (binary) should be in the range “00” to “13” in hexadecimal.  
If an address other than above is input, the ML9041 cannot properly write a character code in or read it from the  
DDRAM.  
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.  
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LCD Drive Waveforms  
The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/9, 1/12 and 1/17  
duties). See 1) to 3) below.  
The relationship between the duty ratio and the frame frequency is as follows:  
Duty ratio  
1/9  
Frame Frequency  
75.0 Hz  
1/12  
56.3 Hz  
1/17  
79.4 Hz  
Note:  
At an oscillation frequency (OSC) of 270 kHz  
(1) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and the character  
font of 5 × 7 dots  
(1/9 duty, AS = 0, CSR = L, SSR = H)  
COM1  
Character  
COM8  
COM9  
Cursor  
Arbitrator  
SEG100  
ML9041  
SEG1  
•
COM10 to COM17 output Display-OFF common signals.  
(1/9 duty, AS = 1, CSR = L, SSR = H)  
COM1  
COM2  
Arbitrator  
Character  
Cursor  
COM9  
SEG100  
ML9041  
SEG1  
•
COM10 to COM17 output Display-OFF common signals.  
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(1/9 duty, AS = 0, CSR = H, SSR = L)  
ML9041  
SEG100  
SEG1  
COM9  
Character  
COM2  
COM1  
Cursor  
Arbitrator  
•
COM10 to COM17 output Display-OFF common signals.  
(1/9 duty, AS = 1, CSR = H, SSR = L)  
ML9041  
SEG100  
SEG1  
Arbitrator  
COM9  
COM8  
Character  
Cursor  
COM1  
•
COM10 to COM17 output Display-OFF common signals.  
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(2) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and the character  
font of 5 × 10 dots  
(1/12 duty, AS = 0, CSR = L, SSH = H)  
COM1  
Character  
COM11  
COM12  
Cursor  
Arbitrator  
SEG100  
ML9041  
SEG1  
•
COM13 to COM17 output Display-OFF common signals.  
(1/12 duty, AS = 1, CSR = L, SSR = H)  
COM1  
COM2  
Arbitrator  
Character  
COM12  
Cursor  
SEG100  
SEG1  
ML9041  
•
COM13 to COM17 output Display-OFF common signals.  
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(1/12 duty, AS = 0, CSR = H, SSR = L)  
ML9041  
SEG100  
SEG1  
COM12  
Character  
COM2  
COM1  
Cursor  
Arbitrator  
•
COM13 to COM17 output Display-OFF common signals.  
(1/12 duty, AS = 1, CSR = H, SSR = L)  
ML9041  
SEG100  
SEG1  
Arbitrator  
Character  
COM12  
COM11  
COM1  
Cursor  
•
COM13 to COM17 output Display-OFF common signals.  
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(3) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and the character  
font of 5 × 7 dots  
(1/17 duty, AS = 0, CSR = L, SSR = H)  
COM1  
Character  
COM8  
COM9  
Cursor  
Character  
COM16  
COM17  
Cursor  
Arbitrator  
SEG100  
ML9041  
SEG1  
(1/17 duty, AS = 1, CSR = L, SSR = H)  
COM1  
COM2  
Arbitrator  
Character  
COM9  
Cursor  
COM10  
Character  
COM17  
Cursor  
SEG100  
SEG1  
ML9041  
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(1/17 duty, AS = 0, CSR = H, SSR = L)  
ML9041  
SEG100  
SEG1  
COM17  
Character  
Cursor  
COM10  
COM9  
Character  
Cursor  
COM2  
COM1  
Arbitrator  
(1/17 duty, AS = 1, CSR = H, SSR = L)  
ML9041  
SEG100  
SEG1  
Arbitrator  
Character  
Cursor  
COM17  
COM16  
COM9  
COM8  
Character  
Cursor  
COM1  
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EXAMPLES OF VLCD GENERATION CIRCUITS  
•
With 1/4bias, a built-in contrast adjusting circuit and a voltage multiplier  
VDD  
V1  
V2  
V3A  
V3B  
V4  
ML9041  
V5  
V5IN  
VC  
VCC  
VIN  
Reference potential for  
voltage multiplier  
BEB  
•
With 1/4 bias, a built-in contrast adjusting circuit  
and the V5 level input from an external circuit  
•
With 1/4 bias, no built-in contrast adjusting circuit  
and the V5 level input from an external circuit  
VDD  
V1  
VDD  
V1  
V2  
V2  
V3A  
V3A  
V3B  
V4  
V3B  
V4  
ML9041  
ML9041  
V5 level  
V5  
V5  
V5IN  
V5IN  
V5 level  
VC  
VCC  
VC  
VCC  
VIN  
VIN  
BEB  
BEB  
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•
With 1/5 bias, a built-in contrast adjusting circuit and a voltage multiplier  
VDD  
V1  
V2  
V3A  
V3B  
V4  
ML9041  
V5  
V5IN  
VC  
VCC  
VIN  
Reference potential for  
voltage multiplier  
BEB  
•
With 1/5 bias, a built-in contrast adjusting circuit  
and the V5 level input from an external circuit  
•
With 1/5 bias, no built-in contrast adjusting circuit  
and the V5 level input from an external circuit  
VDD  
V1  
VDD  
V1  
V2  
V2  
V3A  
V3A  
V3B  
V4  
V3B  
V4  
ML9041  
ML9041  
V5 level  
V5  
V5  
V5IN  
V5IN  
V5 level  
VC  
VCC  
VC  
VCC  
VIN  
VIN  
BEB  
BEB  
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1) COM and SEG Waveforms on 1/9 Duty  
8
9
1
2
3
4
7
8
9
1
2
3
4
7
···  
8
9
1
2
···  
COM1 (CSR = L, AS = L)  
COM2 (CSR = L, AS = H)  
COM9 (CSR = H, AS = L)  
COM8 (CSR = H, AS = H)  
(first character line)  
VDD  
V1  
V2, V3B  
V4  
V5  
1 frame  
COM2 (CSR = L, AS = L)  
COM3 (CSR = L, AS = H)  
COM8 (CSR = H, AS = L)  
COM7 (CSR = H, AS = H)  
(second character line)  
VDD  
V1  
V2, V3B  
V4  
V5  
COM8 (CSR = L, AS = L)  
COM9 (CSR = L, AS = H)  
COM2 (CSR = H, AS = L)  
COM1 (CSR = H, AS = H)  
(cursor line)  
VDD  
V1  
V2, V3B  
V4  
V5  
COM9 (CSR = L, AS = L)  
COM1 (CSR = L, AS = H)  
COM1 (CSR = H, AS = L)  
COM9 (CSR = H, AS = H)  
(arbitrator line)  
VDD  
V1  
V2, V3B  
V4  
V5  
VDD  
V1  
V2, V3B  
V4  
COM10 to  
COM17  
V5  
Display  
turning-off  
waveform  
VDD  
V1  
SEG  
V2, V3B  
V4  
V5  
Display  
turning-on  
waveform  
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2) COM and SEG Waveforms on 1/12 Duty  
11 12 1  
2
3
4
5
6
9 10 11 12 1 2 3 4 5 6  
···  
···  
COM1 (CSR = L, AS = L)  
COM2 (CSR = L, AS = H)  
COM12 (CSR = H, AS = L)  
COM11 (CSR = H, AS = H)  
(first character line)  
VDD  
V1  
V2, V3B  
V4  
V5  
1 frame  
COM2 (CSR = L, AS = L)  
COM3 (CSR = L, AS = H)  
COM11 (CSR = H, AS = L)  
COM10 (CSR = H, AS = H)  
(second character line)  
VDD  
V1  
V2, V3B  
V4  
V5  
COM11 (CSR = L, AS = L)  
COM12 (CSR = L, AS = H)  
COM2 (CSR = H, AS = L)  
COM1 (CSR = H, AS = H)  
(cursor line)  
VDD  
V1  
V2, V3B  
V4  
V5  
COM12 (CSR = L, AS = L)  
COM1 (CSR = L, AS = H)  
COM1 (CSR = H, AS = L)  
COM12 (CSR = H, AS = H)  
(arbitrator line)  
VDD  
V1  
V2, V3B  
V4  
V5  
VDD  
V1  
V2, V3B  
COM13 to  
COM17  
V4  
V5  
Display  
turning-off  
waveform  
VDD  
V1  
SEG  
V2, V3B  
V4  
V5  
Display  
turning-on  
waveform  
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3) COM and SEG Waveforms on 1/17 Duty  
16 17 1  
2
3
4
5
6
7
8
9 10 11 12 13  
16 17 1 2 3 4  
···  
VDD  
V1  
V2  
COM1 (CSR = L, AS = L)  
COM2 (CSR = L, AS = H)  
COM17 (CSR = H, AS = L)  
COM16 (CSR = H, AS = H)  
V3A (V3B  
)
V4  
V5  
(first character line)  
1 frame  
VDD  
V1  
V2  
COM2 (CSR = L, AS = L)  
COM3 (CSR = L, AS = H)  
COM16 (CSR = H, AS = L)  
COM15 (CSR = H, AS = H)  
V3A (V3B  
)
V4  
V5  
(second character line)  
VDD  
V1  
V2  
COM16 (CSR = L, AS = L)  
COM17 (CSR = L, AS = H)  
COM2 (CSR = H, AS = L)  
COM1 (CSR = H, AS = H)  
V3A (V3B  
)
V4  
V5  
(cursor line)  
VDD  
V1  
V2  
COM17 (CSR = L, AS = L)  
COM1 (CSR = L, AS = H)  
COM1 (CSR = H, AS = L)  
COM17 (CSR = H, AS = H)  
V3A (V3B  
)
V4  
V5  
(arbitrator line)  
Display  
turning-off  
waveform  
VDD  
V1  
V2  
SEG  
V3A (V3B  
)
V4  
V5  
Display  
turning-on  
waveform  
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Initial Setting of Instructions  
(a) Data transfer from and to the CPU using 8 bits of DB0 to DB7  
1) Turn on the power.  
2) Wait for 15 ms or more after VDD has reached 2.5 V or higher.  
3) Set “8 bits” with the Function Setting instruction.  
4) Wait for 4.1 ms or more.  
5) Set “8 bits” with the Function Setting instruction.  
6) Wait for 100 µs or more.  
7) Set “8 bits” with the Function Setting instruction.  
8) Check the Busy Flag for No Busy (or wait for 100 µs or more).  
9) Set “8 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction.  
(After this, the number of LCD lines and the font size cannot be changed.)  
10) Check the Busy Flag for No Busy.  
11) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode Setting  
instruction and Arbitrator Display Line Setting Instruction.  
12) Check the Busy Flag for No Busy.  
13) Initialization is completed.  
An example of instruction code for 3), 5) and 7)  
W
RS1  
1
RS0  
0
R/  
DB7  
0
DB6  
0
DB5  
1
DB4  
1
DB3  
DB2  
DB1  
DB0  
0
×
×
×
×
×
: Don’t Care  
(b) Data transfer from and to the CPU using 8 bits of DB4 to DB7  
1) Turn on the power.  
2) Wait for 15 ms or more after VDD has reached 2.5 V or higher.  
3) Set “8 bits” with the Function Setting instruction.  
4) Wait for 4.1 ms or more.  
5) Set “8 bits” with the Function Setting instruction.  
6) Wait for 100 µs or more.  
7) Set “8 bits” with the Function Setting instruction.  
8) Check the Busy Flag for No Busy (or wait for 100 µs or longer).  
9) Set “4 bits” with the Function Setting instruction.  
10) Wait for 100 µs or longer.  
11) Set “4 bits”, “Number of LCD lines” and “Font size” with the Initial Setting instruction. (After this, the  
number of LCD lines and the font size cannot be changed.)  
12) Check the Busy Flag for No Busy.  
13) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode Setting  
instruction and Arbitrator Display Line Setting Instruction.  
14) Check the Busy Flag for No Busy.  
15) Initialization is completed.  
An example of instruction code for 3), 5) and 7)  
W
RS1  
1
RS0  
0
R/  
DB7  
0
DB6  
0
DB5  
1
DB4  
1
0
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An example of instruction code for 9)  
W
RS1  
1
RS0  
0
R/  
DB7  
0
DB6  
0
DB5  
1
DB4  
0
0
*: In 13), check the Busy Flag for No Busy before executing each instruction.  
(c) Data transfer from and to the CPU using the serial I/F  
1) Turn on the power.  
2) Wait for 15 ms or more after VDD has reached 2.5 V or higher.  
3) Set “Number of LCD lines” and “Font size” with the Function Setting Instruction.  
4) Execute the Display Mode Setting Instruction, the Display Clear Instruction, the Entry Mode  
Instruction and the Arbitrator Display Line Setting Instruction.  
5) Check the busy flag for No Busy.  
6) Initialization is completed.  
*: In 3) and 4), check the Busy Flag for No Busy before executing each instruction.  
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ML9041-xxA CVWA PAD CONFIGURATION  
Pad Layout  
Chip Size:  
10.62 × 2.55 mm  
Chip Thickness: 625±20 µm  
Bump Size (1):  
Bump Size (2):  
72 × 72 µm  
(PAD No. 1-62, 183-189)  
54 × 96 µm  
(PAD No. 63-182)  
Y
182  
63  
62  
X
183  
189  
56  
1
55  
Pad Coordinates  
µ
µ
µ
µ
Pad  
1
Symbol  
X ( m)  
Y ( m)  
Pad  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
Symbol  
DB3  
DB2  
DB1  
DB0  
E
X ( m)  
Y ( m)  
V1  
V2  
–5103  
–4914  
–4725  
–4536  
–4347  
–4158  
–3969  
–3780  
–3591  
–3402  
–3213  
–3024  
–2835  
–2646  
–2457  
–2268  
–2079  
–1890  
–1701  
–1512  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1323  
–1134  
–945  
–756  
–567  
–378  
–189  
0
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
2
3
V3A  
V3B  
V4  
4
5
W
6
V5  
R/  
7
V5IN  
VCC  
VC  
RS0  
RS1  
SO  
8
9
189  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
VlN  
Sl  
378  
SHT  
CS  
OSC2  
OSCR  
OSC1  
T3  
BEB  
VDD  
CSR  
SSR  
567  
756  
945  
1134  
1323  
1512  
1701  
1890  
2079  
2268  
P
/S  
VSS  
DB7  
DB6  
DB5  
DB4  
T2  
T1  
COM1  
COM2  
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µ
µ
µ
µ
Pad  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
Symbol  
COM3  
X ( m)  
Y ( m)  
Pad  
81  
Symbol  
SEG92  
SEG91  
SEG90  
SEG89  
SEG88  
SEG87  
SEG86  
SEG85  
SEG84  
SEG83  
SEG82  
SEG81  
SEG80  
SEG79  
SEG78  
SEG77  
SEG76  
SEG75  
SEG74  
SEG73  
SEG72  
SEG71  
SEG70  
SEG69  
SEG68  
SEG67  
SEG66  
SEG65  
SEG64  
SEG63  
SEG62  
SEG61  
SEG60  
SEG59  
SEG58  
SEG57  
SEG56  
SEG55  
SEG54  
SEG53  
X ( m)  
Y ( m)  
2457  
2646  
2835  
3024  
3213  
3402  
3591  
3780  
3969  
4158  
4347  
4536  
4725  
4914  
5103  
5184  
5184  
5184  
5184  
5184  
5184  
5184  
4998  
4914  
4830  
4746  
4662  
4578  
4494  
4410  
4326  
4242  
4158  
4074  
3990  
3906  
3822  
3738  
3654  
3570  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–720  
–480  
–240  
0
3486  
3402  
3318  
3234  
3150  
3066  
2982  
2898  
2814  
2730  
2646  
2562  
2478  
2394  
2310  
2226  
2142  
2058  
1974  
1890  
1806  
1722  
1638  
1554  
1470  
1386  
1302  
1218  
1134  
1050  
966  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
COM4  
82  
COM5  
83  
COM6  
84  
COM7  
85  
COM8  
86  
COM9  
87  
COM10  
COM11  
COM12  
COM13  
COM14  
COM15  
COM16  
COM17  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
SEG100  
SEG99  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
240  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
480  
720  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
882  
798  
714  
SEG98  
630  
SEG97  
546  
SEG96  
462  
SEG95  
378  
SEG94  
294  
SEG93  
210  
55/60  
PEDL9041-03  
1
Semiconductor  
ML9041-xxA/xxB  
µ
µ
µ
µ
Pad  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
Symbol  
SEG52  
SEG51  
SEG50  
SEG49  
SEG48  
SEG47  
SEG46  
SEG45  
SEG44  
SEG43  
SEG42  
SEG41  
SEG40  
SEG39  
SEG38  
SEG37  
SEG36  
SEG35  
SEG34  
SEG33  
SEG32  
SEG31  
SEG30  
SEG29  
SEG28  
SEG27  
SEG26  
SEG25  
SEG24  
SEG23  
SEG22  
SEG21  
SEG20  
SEG19  
SEG18  
X ( m)  
Y ( m)  
Pad  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
Symbol  
SEG17  
X ( m)  
Y ( m)  
126  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
–2814  
–2898  
–2982  
–3066  
–3150  
–3234  
–3318  
–3402  
–3486  
–3570  
–3654  
–3738  
–3822  
–3906  
–3990  
–4074  
–4158  
–4242  
–4326  
–4410  
–4494  
–4578  
–4662  
–4746  
–4830  
–4914  
–4998  
–5184  
–5184  
–5184  
–5184  
–5184  
–5184  
–5184  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
720  
42  
SEG16  
–42  
SEG15  
–126  
SEG14  
–210  
SEG13  
–294  
SEG12  
–378  
SEG11  
–462  
SEG10  
–546  
SEG9  
–630  
SEG8  
–714  
SEG7  
–798  
SEG6  
–882  
SEG5  
–966  
SEG4  
–1050  
–1134  
–1218  
–1302  
–1386  
–1470  
–1554  
–1638  
–1722  
–1806  
–1890  
–1974  
–2058  
–2142  
–2226  
–2310  
–2394  
–2478  
–2562  
–2646  
–2730  
SEG3  
SEG2  
SEG1  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
480  
240  
0
–240  
–480  
–720  
56/60  
PEDL9041-03  
1
Semiconductor  
ML9041-xxA/xxB  
ML9041-xxB CVWA PAD CONFIGURATION  
Pad Layout  
Chip Size:  
10.62 × 2.55 mm  
Chip Thickness: 625±20 µm  
Bump Size (1):  
Bump Size (2):  
72 × 72 µm  
(PAD No. 1-55)  
54 × 96 µm  
Y
(PAD No. 56-175)  
175  
56  
X
1
55  
Pad Coordinates  
Note: The ML9041-xxB does not have the dummy pads corresponding to the pad numbers 56 to 62 and 183 to  
189 for the ML9041-xxA.  
µ
µ
µ
µ
Pad  
1
Symbol  
V1  
X ( m)  
Y ( m)  
Pad  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
Symbol  
DB3  
DB2  
DB1  
DB0  
E
X ( m)  
Y ( m)  
–5103  
–4914  
–4725  
–4536  
–4347  
–4158  
–3969  
–3780  
–3591  
–3402  
–3213  
–3024  
–2835  
–2646  
–2457  
–2268  
–2079  
–1890  
–1701  
–1512  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1323  
–1134  
–945  
–756  
–567  
–378  
–189  
0
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
2
V2  
3
V3A  
V3B  
V4  
4
5
W
6
V5  
R/  
7
V5IN  
VCC  
VC  
RS0  
RS1  
SO  
8
9
189  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
VlN  
Sl  
378  
SHT  
CS  
OSC2  
OSCR  
OSC1  
T3  
BEB  
VDD  
CSR  
SSR  
567  
756  
945  
1134  
1323  
1512  
1701  
1890  
2079  
2268  
P
/S  
VSS  
DB7  
DB6  
DB5  
DB4  
T2  
T1  
COM1  
COM2  
57/60  
PEDL9041-03  
1
Semiconductor  
ML9041-xxA/xxB  
µ
µ
µ
µ
Pad  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
Symbol  
COM3  
X ( m)  
Y ( m)  
Pad  
81  
Symbol  
SEG85  
SEG84  
SEG83  
SEG82  
SEG81  
SEG80  
SEG79  
SEG78  
SEG77  
SEG76  
SEG75  
SEG74  
SEG73  
SEG72  
SEG71  
SEG70  
SEG69  
SEG68  
SEG67  
SEG66  
SEG65  
SEG64  
SEG63  
SEG62  
SEG61  
SEG60  
SEG59  
SEG58  
SEG57  
SEG56  
SEG55  
SEG54  
SEG53  
SEG52  
SEG51  
SEG50  
SEG49  
SEG48  
SEG47  
SEG46  
X ( m)  
Y ( m)  
2457  
2646  
2835  
3024  
3213  
3402  
3591  
3780  
3969  
4158  
4347  
4536  
4725  
4914  
5103  
4998  
4914  
4830  
4746  
4662  
4578  
4494  
4410  
4326  
4242  
4158  
4074  
3990  
3906  
3822  
3738  
3654  
3570  
3486  
3402  
3318  
3234  
3150  
3066  
2982  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
–1100  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
2898  
2814  
2730  
2646  
2562  
2478  
2394  
2310  
2226  
2142  
2058  
1974  
1890  
1806  
1722  
1638  
1554  
1470  
1386  
1302  
1218  
1134  
1050  
966  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
COM4  
82  
COM5  
83  
COM6  
84  
COM7  
85  
COM8  
86  
COM9  
87  
COM10  
COM11  
COM12  
COM13  
COM14  
COM15  
COM16  
COM17  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
SEG100  
SEG99  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
882  
798  
714  
SEG98  
630  
SEG97  
546  
SEG96  
462  
SEG95  
378  
SEG94  
294  
SEG93  
210  
SEG92  
126  
SEG91  
42  
SEG90  
–42  
SEG89  
–126  
–210  
–294  
–378  
SEG88  
SEG87  
SEG86  
58/60  
PEDL9041-03  
1
Semiconductor  
ML9041-xxA/xxB  
µ
µ
µ
µ
Pad  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
Symbol  
SEG45  
SEG44  
SEG43  
SEG42  
SEG41  
SEG40  
SEG39  
SEG38  
SEG37  
SEG36  
SEG35  
SEG34  
SEG33  
SEG32  
SEG31  
SEG30  
SEG29  
SEG28  
SEG27  
SEG26  
SEG25  
SEG24  
SEG23  
SEG22  
SEG21  
SEG20  
SEG19  
SEG18  
X ( m)  
Y ( m)  
Pad  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
Symbol  
SEG17  
SEG16  
SEG15  
SEG14  
SEG13  
SEG12  
SEG11  
SEG10  
SEG9  
X ( m)  
Y ( m)  
–462  
–546  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
–2814  
–2898  
–2982  
–3066  
–3150  
–3234  
–3318  
–3402  
–3486  
–3570  
–3654  
–3738  
–3822  
–3906  
–3990  
–4074  
–4158  
–4242  
–4326  
–4410  
–4494  
–4578  
–4662  
–4746  
–4830  
–4914  
–4998  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
1088  
–630  
–714  
–798  
–882  
–966  
–1050  
–1134  
–1218  
–1302  
–1386  
–1470  
–1554  
–1638  
–1722  
–1806  
–1890  
–1974  
–2058  
–2142  
–2226  
–2310  
–2394  
–2478  
–2562  
–2646  
–2730  
SEG8  
SEG7  
SEG6  
SEG5  
SEG4  
SEG3  
SEG2  
SEG1  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
DUMMY  
59/60  
PEDL9041-03  
1
Semiconductor  
ML9041-xxA/xxB  
NOTICE  
1. The information contained herein can change without notice owing to product and/or technical improvements.  
Before using the product, please make sure that the information being referred to is up-to-date.  
2. The outline of action and examples for application circuits described herein have been chosen as an  
explanation for the standard action and performance of the product. When planning to use the product, please  
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.  
3. When designing your product, please use our product below the specified maximum ratings and within the  
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating  
temperature.  
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation  
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or  
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified  
maximum ratings or operation outside the specified operating range.  
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is  
granted by us in connection with the use of the product and/or the information and drawings contained herein.  
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use  
thereof.  
6. The products listed in this document are intended for use in general electronics equipment for commercial  
applications (e.g., office automation, communication equipment, measurement equipment, consumer  
electronics, etc.). These products are not authorized for use in any system or application that requires special  
or enhanced quality and reliability characteristics nor in any system or application where the failure of such  
system or application may result in the loss or damage of property, or death or injury to humans.  
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace  
equipment, nuclear power control, medical equipment, and life-support systems.  
7. Certain products in this document may need government approval before they can be exported to particular  
countries. The purchaser assumes the responsibility of determining the legality of export of these products  
and will take appropriate and necessary steps at their own expense for these.  
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.  
Copyright 2001 Oki Electric Industry Co., Ltd.  
60/60  

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