ML9042-XXCVWA [OKI]
Dot Matrix LCD Driver, 17 X 100 Dots, CMOS, DIE-233;
| 型号： | ML9042-XXCVWA |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Dot Matrix LCD Driver, 17 X 100 Dots, CMOS, DIE-233 时钟 驱动 CD 外围集成电路 |
| 文件： | 总58页 (文件大小：558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL9042-01
Issue Date: Nov. 19, 2003
OKI Semiconductor
ML9042-xx
DOT MATRIX LCD CONTROLLER DRIVER
GENERAL DESCRIPTION
The ML9042 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type
dot matrix LCD.
FEATURES
•
•
•
•
•
•
Easy interfacing with an 8-bit or 4-bit microcontroller
Switchable between serial and parallel interfaces
Dot-matrix LCD controller driver for a 5 × 8 dot font
Built-in circuit allowing automatic resetting at power-on
Built-in 17 common signal drivers and 100 segment signal drivers
Two built-in character generator ROMs each capable of generating 240 characters (5 × 8 dots)
The character generator ROM can be selected by bank switching (ROM1S) pin.
Creation of character patterns by programming: up to 8 character patterns (5 × 8 dots)
Built-in RC oscillation circuit using external or internal resistors
Program-selectable duties
•
•
•
When ABE bit is “L”: 1/8 duty (1 line: 5 × 8 dots), or 1/16 duty (2 lines: 5 × 8 dots)
When ABE bit is “H”: 1/9 duty (1 line: 5 × 8 dots + arbitrator), or 1/17 duty (2 lines: 5 × 8 dots + arbitrator)
Cursor display
Built-in bias dividing resistors to drive the LCD
Bi-directional transfer of segment outputs
Bi-directional transfer of common outputs
100-dot arbitrator display
Line display shifting
Built-in voltage multiplier circuit
•
•
•
•
•
•
•
•
Gold Bump Chip
ML9042-xx CVWA/DVWA
*xx indicates a character generator ROM code number.
*01, 11 and 21 indicate general character generator ROM code numbers.
CVWA indicates a bump chip with high hardness, and DVWA indicates a bump chip with low
hardness.
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BLOCK DIAGRAM
Segment Signal driver
100-bit latch
100-bit bi-directional shift register
Parallel-
serial converter
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I/O CIRCUITS
VDD
VDD
VDD
P
P
N
N
Applied to pins T1, T2, and T3
Applied to pins RW/SI, RS1, and
RS0/CSB
Applied to pins E/SHTB, SP, ROM1S, and BE
VDD
VDD
P
P
VDD
N
P
N
Output Enable signal
Applied to pins DB0(SO) to DB7
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PIN DESCRIPTIONS
Symbol
RW/SI
Description
The input pin with a pull-up resistor to select Read (“H”) or Write (“L”) in the Parallel I/F
Mode.
The pin to input data in the Serial l/F Mode. Each instruction code and each data are
read in by the rising edge of the E/SHTB signal.
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.
RS1
H
RS0/CSB
Name of register
Data register
H
L
L
RS0/CSB, RS1
H
Instruction register
L
Expansion Instruction register
The RSo/CSB pin is configured as a chip enable input in the Serial I/F Mode. Setting
the RSo/CSB pin to “L” allows the I/F to be provided.
The input pin for data input/output between the CPU and the ML9042 and for
activating instructions in the Parallel l/F Mode.
E/SHTB
This pin is configured as a shift clock input in the Serial I/F Mode. The data input to the
PW/SI pin is synchronized to the rising edge of the clock, and the data output from the
DB0(SO) pin is synchronized to the falling edge of the shift clock.
The input/output pins to transfer data of lower-order 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the 4-bit interface.
Only the DB0(SO) pin is configured as a data output in the Serial I/F Mode. Busy flag
& address and data are output synchronized to the falling edge of the E/SHTB signal.
These pins remain pulled up when data is not output.
DB0(SO) to DB3
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.
The input/output pins to transfer data of upper 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the serial interface.
DB4 to DB7
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F
Mode when not used.
The clock oscillation pins required for LCD drive signals and the operation of the
ML9042 by instructions sent from the CPU.
To input external clock, the OSC1 pin should be used. The OSCR3, OSCR5, and OSC2
pins should be open.
OSC1
OSC2
To start oscillation with an external resistor, the resistor should be connected between
the OSC1 and OSC2 pins. The OSCR3 and OSCR5 pins should be open.
OSCR3
OSCR5
To start oscillation at 5 V using an internal resistor, the OSC2 and OSCR5 pins should
be short-circuited outside the ML9042. The OSC1 and OSCR3 pins should be open.
To start oscillation at 3 V using an internal resistor, the OSC2 and OSCR3 pins should
be short-circuited outside the ML9042. The OSC1 and OSCR5 pins should be open.
(The OSC2, OSCR3, and OSCR5 pins can also be short-circuited outside the ML9042,
and the OSC1 pin can be open.)
The LCD common signal output pins.
For 1/8 duty, non-selectable voltage waveforms are output via COM9 to COM17. For
1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For 1/16
duty, a non-selectable voltage waveform is output via COM17.
COM1 to COM17
SEG1 to SEG100
The LCD segment signal output pins.
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Symbol
ROM1S
Description
The input pin to switch the ROM bank. “H” selects ROM1 and “L” selects ROM0.
Switching after power-on is prohibited.
The pins to output bias voltages to the LCD.
V1 , V2, V3A, V3B, V4
For 1/4 bias : The V2 and V3B pins are shorted.
For 1/5 bias : The V3A and V3B pins are shorted.
The input pin to enable or disable the voltage multiplier circuit.
"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.
The voltage multiplier circuit doubles the input voltage between the VIN pin and the
GND pin, and the multiplied voltage referenced to the GND is output to the VOUT pin.
The voltage multiplier circuit can be used only when generating a level higher than the
BE
VDD
.
TESTIN
TESTOUT
VIN
The input pin for test circuits. Normally connect this pin to VDD.
The output pin for the test circuits. Normally leave this pin open.
The pin to input voltage to the voltage multiplier.
The pins to supply the LCD drive voltage.
The same potential as the VDD potential is supplied to the VOUT and V0 pins when the
voltage multiplier is not used (BE = “0” or BE = “1”, and the capacitor is not connected
to the VC and VCC pins)
V0, VOUT
When the voltage multiplier is used (BE = “1”), the multiplied voltage is output to the
VOUT pin, so that the VOUT pin and V0 pin should be connected.
Capacitors for the voltage multiplier should be connected between the GND and the
VOUT pin.
The pin to connect the negative pin of the capacitor for the voltage multiplier. Leave the
pin open when the voltage multiplier circuit is not used.
VC
VCC
The pin to connect the positive pin of the capacitor used for the voltage multiplier.
Leave the pin open when the voltage multiplier circuit is not used.
The input pins for test circuits (normally open). Each of these pins is equipped with a
pull-down resistor, so this pin should be left open.
T1, T2, T3
VDD
The power supply pin.
GND
The ground level input pin.
The input pin to select the serial or parallel interface.
“L” selects the parallel interface.
“H” selects the serial interface.
SP
The output pin to fix the adjacent input pin to the VDD level. Use this pin only for this
purpose.
DUMMYVDD
The output pin to fix the adjacent input pin to the GND level. Use this pin only for this
purpose.
DUMMYGND
DUMMY
NC (No Connection) pin.
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ABSOLUTE MAXIMUM RATINGS
(GND = 0 V)
Parameter
Symbol
VDD
Condition
Rating
Unit
V
Applicable pins
Supply Voltage
Ta = 25°C
–0.3 to +6.5
VDD
V0, V1, V2,
V3, V4,
V
GND
OUT, V0, V1, V2, V3A, V3B, V4,
LCD Driving Voltage
Ta = 25°C
–0.3 to +6.5
V
RW/SI, E/SHTB, SP,
RS0/CSB, RS1, BE,
ROM1S, T1 to T3, DB0(SO)
to DB7, VIN
Input Voltage
VI
Ta = 25°C
–0.3 to VDD+0.3
–55 to +150
V
Storage Temperature
TSTG
—
°C
—
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V)
Applicable pins
VDD
Parameter
Symbol
VDD
Condition
—
Range
Unit
V
Supply Voltage
2.7 to 5.5
V0
LCD Driving Voltage
—
2.7 to 5.5
V
VOUT, V0
(See Note)
Voltage Multipler
Input Voltage
VMUL
Top
BE = “1”
—
1.8 to 2.75
–40 to +85
V
VIN
—
Operating Temperature
°C
Note: This voltage should be applied across V0 and GND. The following voltages are output to the V1,
V2, V3A (V3B) and V4 pins:
• 1/4 bias (V2 and V3B are short-circuited)
V1 =3 V0/4 ±0.15 V
V2 = V3B = V0/2 ±0.15 V
V4 = V0/4 ±0.15 V
• 1/5 bias (V3A and V3B are short-circuited)
V1 = 4 V0/5 ±0.15 V
V2 = 3 V0/5 ±0.15 V
V3A = V3B = 2 V0/5 ±0.15 V
V4 = V0/5 ±0.15 V
The voltages at the V0, V1, V2, V3A (V3B), V4 and GND pins should satisfy
V0 > V1 > V2 > V3A (V3B) > V4 > GND
(Higher ←
→ Lower)
* If the chip is attached on a substrate using COG technology, the chip tends to be susceptible
to electrical characteristics of the chip due to trace resistance on the glass substrate. It is
recommended to use the chip by confirming that it operates on the glass substrate properly.
Trace resistance, especially, VDD and VSS trace resistance, between the chip on the LCD
panel and the flexible cable should be designed as low as possible. Trace resistance that
cannot be very well decreased, larger size of the LCD panel, or greater trace capacitance
between the microcontroller and the ML9042 device can cause device malfunction. In order
to avoid the device malfunction, power noise should be reduced by serial interfacing of the
microcontroller and the ML9042 device.
* Do not apply short-circuiting across output pins and across an output pin and an input/output
pin or the power supply pin in the output mode.
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Parameter
Symbol
VIH
Condition
Min.
Typ. Max. Unit Applicable pin
RW/SI,
“H” Input Voltage
0.8VDD
—
VDD
RS0/CSB, RS1,
E/SHTB,
—
V
DB0(SO) to
DB7, SP,
OSC1, BE,
ROM1S
“L” Input Voltage
VIL
0
—
0.2VDD
“H” Output Voltage 1
“L” Output Voltage 1
“H” Output Voltage 2
“L” Output Voltage 2
VOH1 IOH = –0.1 mA
VOL1 IOL = +0.1 mA
VOH2 IOH = –13 µA
VOL2 IOL = +13 µA
0.9VDD
—
—
—
—
—
—
DB0(SO) to
DB7
V
V
0.1VDD
—
0.9VDD
—
OSC2
0.1VDD
V0–
VCH lOCH = –4 µA
VCMH lOCMH = ±4 µA
VCML lOCML = ±4 µA
VCL lOCL = +4 µA
VSH lOSH = –4 µA
VSMH lOSMH = ±4 µA
VSML lOSML = ±4 µA
VSL lOSL = +4 µA
V0–0.3
V1–0.3
V4–0.3
GND
V0
0.012
V1±
V1+0.3
V4+0.3
GND+0.3
V0
V0 –GND = 5 V
Note 1
0.012
COM1 to
COM17
COM Voltage Drop
V
V4±
0.012
GND+
0.012
V0–
V0–0.3
V2–0.3
V3–0.3
GND
0.012
V2±
V2+0.3
V3+0.3
GND+0.3
V0 –GND = 5 V
Note 1
0.012
SEG1 to
SEG100
SEG Voltage Drop
V
V3±
0.012
GND+
0.012
E/SHTB, BE,
SP, VIN
Input Leakage Current
Input Current 1
| IIL | VDD = 5 V, VI = 5 V or 0 V
VDD = 5 V, VI = GND
—
—
1.0
61
µA
µA
10
25
RW/SI,
VDD = 5 V, VI = VDD,
RS0/CSB, RS1,
DB0(SO) to
DB7
| II1 |
Excluding current flowing
through the pull-up resistor
and the output driving MOS
—
—
2.0
VDD = 5 V, VI = VDD
15
—
45
—
105
2.0
VDD = 5 V, VI = GND
Excluding current flowing
through the pull-down resistor
Input Current 2
Supply Current
| II2 |
lDD
µA T1, T2, T3
VDD = 5 V
Note 2
—
—
1.2
mA VDD–GND
Oscillation Frequency
of External Resistor Rf
fosc1 Rf = 85 kΩ±2%
Note 3
175
270
400
kHz OSC1, OSC2
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VDD = 4.0 to 5.5 V
Ta = -20 to 75°C
OSC1, OSC2,
OSCR5
200
200
270
280
351
364
kHz
kHz
OSC1 and OSCR3: Open
OSC2 and OSCR5:
Short-circuited
Note 4
Oscillation Frequency of
Internal Resistor Rf
fosc2
VDD = 2.7 to 3.6 V
Ta = -20 to 75°C
OSC1 and OSCR5: Open
OSC2 and OSCR3:
OSC1, OSC2,
OSCR3
Short-circuited
Note 4
OSC2, OSCR: Open
Input from OSC1
Clock Input
Frequency
fin
fduty
frf
175
45
—
50
—
400
55
kHz
%
Input Clock Duty
Note 5
Note 6
Note 6
OSC1
Input Clock Rise
Time
—
0.2
0.2
2.6
µs
Input Clock Fall Time
fff
—
—
µs
V0, V1, V2, V3A,
V3B, V4, GND
-0x code
-1x code
-2x code
1.4
2.0
kΩ
V0, V1, V2, V3A,
V3B, V4, GND
LCD Bias Resistor
RLB
2.8
7.0
4.0
5.2
kΩ
kΩ
V0, V1, V2, V3A,
V3B, V4, GND
10.0
13.0
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(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Applicable
Parameter
Symbol
VMUL
Condition
Min.
1.8
Typ.
—
Max.
2.75
Unit
V
pins
Voltage Multiplier
Input Voltage
Note 7
VIN
VDD = 2.7 V, VIN = 2.25 V
f = 175 kHz
1/5
bias
(VDD–VIN)
4.3
—
× 2
A capacitor for the voltage
multiplier = 1 to 4.7 µF
Voltage Multiplier
Output Voltage
VOUT
V
VOUT
VOUT load current = 54 µA
1/4
bias
(VDD–VIN)
BE = “H”
4.3
—
× 2
Applied to LCD bias
resistance of 10 kΩ (TYP)
only
1/5
bias
VLCD1
VLCD2
2.7
2.7
—
—
5.5
5.5
Bias Voltage for
Driving LCD
V0–GND
Note 8
V
V0
1/4
bias
Note 1: Applied to the voltage drop occurring between any of the V0, V1, V4 and GND pins and any of
the common pins (COM1 to COM17) when the current of 4 µA flows in or flows out at one
common pin.
Also applied to the voltage drop occurring between any of the V0, V2, V3A (V3B) and GND pins
and any of the segment pins (SEG1 to SEG100) when the current of 4 µA flows in or flows out at
one segment pin.
The current of 4 µA flows out when the output level is VDD or flows in when the output level is
V5.
Note 2: Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is
fed to the internal Rf oscillation or OSC1 under the following conditions:
VDD = V0 = 5 V
GND = 0 V,
V1, V2, V3A (V3B) and V4: Open
E/SHTB and BE: “L” (fixed)
Other input pins: “L” or “H” (fixed)
Other output pins: No load
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Note 3:
Note 4:
OSC1
OSC1
OSC1
OSCR3
OSCR5
OSC2
OSCR3
OSCR5
OSC2
OSCR3
OSCR5
OSC2
Rf = 85 kΩ±2%
The wire between OSC1 and Rf and the wire between The wire between OSCR3 and OSC2, or between OSCR5
OSC2 and Rf should be as short as possible.
Keep OSCR3 and OSCR5 open.
and OSC2 should be as short as possible. Keep open
between OSC1 and OSCR3, or between OSC1 and OSCR5.
Note 5:
tHW
tLW
VDD
2
VDD
2
VDD
2
fIN
waveform
Applied to the pulses entering from the OSC1 pin
fduty = tHW/(tHW + tLW) ×100 (%)
Note 6:
0.8VDD
0.2VDD
0.8VDD
0.2VDD
trf
tff
Applied to the pulses entering from the OSC1 pin
Note 7: The maximum value of the voltage multiplier input voltage should be set at 2.75 V, and the
minimum value of the voltage multiplier input voltage should be set by monitoring the voltage
of V0 in actual use so that the voltage multiplier output voltage meets the specification for the
bias voltage for driving LCD after contrast adjustment.
Note 8: For 1/4 bias, V2 and V3B pins are short-circuited. V3A pin is open.
For 1/5 bias, V3A and V3B pins are short-circuited. V2 pin is open.
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I/O Characteristics
•
Parallel Interface Mode
The timing for the input from the CPU and the timing for the output to the CPU are as shown below:
1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.7 to 4.5 V, Ta = –40 to +85°C)
Parameter
RW/SI, RS0/CSB, RS1 Setup Time
E/SHTB Pulse Width
Symbol
Min.
40
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tB
tW
tA
tr
450
10
—
RW/SI, RS0/CSB, RS1 Hold Time
E/SHTB Rise Time
—
—
125
125
—
E/SHTB Fall Time
tf
—
E/SHTB Pulse Width
tL
tC
tI
430
1000
195
10
E/SHTB Cycle Time
—
DB0(SO) to DB7 Input Data Setup Time
DB0(SO) to DB7 Input Data Hold Time
—
tH
—
(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)
Parameter
RW/SI, RS0/CSB, RS1 Setup Time
E/SHTB Pulse Width
Symbol
Min.
40
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tB
tW
tA
tr
220
10
—
RW/SI, RS0/CSB, RS1 Hold Time
E/SHTB Rise Time
—
—
125
125
—
E/SHTB Fall Time
tf
—
E/SHTB Pulse Width
tL
tC
tI
220
500
60
E/SHTB Cycle Time
—
DB0(SO) to DB7 Input Data Setup Time
DB0(SO) to DB7 Input Data Hold Time
—
tH
10
—
VIH
VIL
VIH
RS1, RS0/CSB
VIL
RW/SI
VIL
tA
VIL
tr
tf
tB
tW
tL
VIH
VIH
E/SHTB
VIL
VIL
VIL
tH
tI
Input
Data
VIH
VIL
VIH
VIL
DB0(SO) to DB7
tC
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2) READ MODE (Timing for output to the CPU)
(VDD = 2.7 to 4.5 V, Ta = –40 to +85°C)
Parameter
RW/SI, RS1, RS0/CSB Setup Time
E/SHTB Pulse Width
Symbol
Min.
40
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tB
tW
tA
tr
450
10
—
RW/SI, RS1, RS0/CSB Hold Time
E/SHTB Rise Time
—
—
125
125
—
E/SHTB Fall Time
tf
—
E/SHTB Pulse Width
tL
tC
tD
tO
430
1000
—
E/SHTB Cycle Time
—
DB0(SO) to DB7 Output Data Delay Time
DB0(SO) to DB7 Output Data Hold Time
350
—
20
Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.
(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)
Parameter
RW/SI, RS1, RS0/CSB Setup Time
E/SHTB Pulse Width
Symbol
Min.
40
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tB
tW
tA
tr
220
10
—
RW/SI, RS1, RS0/CSB Hold Time
E/SHTB Rise Time
—
—
125
125
—
E/SHTB Fall Time
tf
—
E/SHTB Pulse Width
tL
tC
tD
tO
220
500
—
E/SHTB Cycle Time
—
DB0(SO) to DB7 Output Data Delay Time
DB0(SO) to DB7 Output Data Hold Time
250
—
20
Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.
VIH
VIL
VIH
RS1, RS0/CSB
VIL
VIH
VIH
RW/SI
tr
tf
tB
tW
tA
tL
VIH
VIH
E/SHTB
VIL
tO
VIL
VIL
tD
0.8VDD
0.8VDD
0.2VDD
Output
Data
DB0(SO) to DB7
0.2VDD
tC
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ML9042-xx
•
Serial Interface Mode
(VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Parameter
Symbol
tSCY
tCSU
tCH
Min.
500
100
100
200
60
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
E/SHTB Cycle Time
RS0/CSB Setup Time
RS0/CSB Hold Time
—
—
RS0/CSB “H” Pulse Width
E/SHTB Setup Time
tCSWH
tSSU
tSH
—
—
E/SHTB Hold Time
200
200
200
—
—
E/SHTB “H” Pulse Width
E/SHTB “L” Pulse Width
E/SHTB Rise Time
tSWH
tSWL
tSR
—
—
125
125
—
E/SHTB Fall Time
tSF
—
RW/Sl Setup Time
tDISU
tDIH
tDOD
tCDH
100
100
—
RW/Sl Hold Time
—
DB0(SO) Output Data Delay Time
DB0(SO) Output Data Hold Time
160
—
0
tCSWH
tSCY
VIH
VIH
VIH
RS0/CSB
VIL
VIL
tSSU
tSR
tSF
tSH
VIH
tSWL
tSWH
tCH
VIH
tCSU
VIH
E/SHTB
RW/SI
VIH
tDIH
VIH
VIL
tDISU
VIL
VIH
VIL
VIH
VIL
tDOD
tDOD
tCDH
VOH
VOH
DB0(SO)
VOL
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FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS0/CSB and RS1. The DR is
selected when both RS0/CSB and RS1 are “H”. The IR is selected when RS0/CSB is “L” and RS1 is “H”. The ER
is selected when both RS0/CSB and RS1 are “L”. (When RS0/CSB is “H” and RS1 is “L”, the ML9042 is not
selected.)
The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character
generator RAM (CGRAM).
The microcontroller (CPU) can write but cannot read the instruction code.
The ER sets the display positions of the arbitrator and the address code of the arbitrator RAM (ABRAM).
The CPU can write but cannot read the display positions of the arbitrator.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the
DDRAM, ABRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically transferred from
the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked
by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected
to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next
address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the RW/SI pin.
Table 1 RW/SI pin status and register operation
RW/SI RS0/CSB RS1
Operation
L
H
L
L
L
H
H
H
H
L
Writing in the IR
Reading the Busy flag (BF) and the address counter (ADC)
Writing in the DR
H
H
L
H
L
Reading from the DR
Writing in the ER
Disabled (Not in a busy state, not performing the reads.
Note that the data bus goes into a high impedance state.)
H
L
L
H
H
L
L
L
Disabled (Not in a busy state, not performing the writes)
Disabled (Not in a busy state, not performing the reads.
Note that the data bus goes into a high impedance state.)
H
Busy Flag (BF)
The status “1” of the Busy Flag (BF) indicates that the ML9042 is carrying out internal operation.
When the BF is “1”, any new instruction is ignored.
When RW/SI = “H”, RS0/CSB = “L” and RS1 = “H”, the data in the BF is output to the DB7.
New instructions should be input when the BF is “0”.
When the BF is “1”, the output code of the address counter (ADC) is undefined.
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Address Counter (ADC)
The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a
cursor display address.
When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to the pre-defined
register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the
ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is
written in or read from the DDRAM, ABRAM or CGRAM.
The data in the ADC is output to DB0(SO) to DB6 when RW/SI = “H”, RS0/CSB = “L”, RS1 = “H” and BF = “0”.
Timing Generator
The timing generator generates timing signals for the internal operation of the ML9042 activated by the instruction
sent from the CPU or for the operation of the internal circuits of the ML9042 such as DDRAM, ABRAM,
CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for LCD displaying
will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU
writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.
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Display Data RAM (DDRAM)
This RAM stores the 8-bit character codes (see Table 2).
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM
addresses (to be set in the ADC) are represented in hexadecimal.
DB6 DB5 DB4 DB3 DB2 DB1 DB0
ADC
MSB
LSB
Hexadecimal
Hexadecimal
(Example) Representation of DDRAM address = 12
ADC
0
0
1
0
0
1
0
1
2
1) Relationship between DDRAM addresses and display positions (1-line display mode)
Digit
1
Display position
2
3
4
5
19 20
12 13
DD RAM address (hexadecimal)
00 01 02 03 04
Left
end
Right
end
In the 1-line display mode, the ML9042 can display up to 20 characters from digit 1 to digit 20. While the
DDRAM has addresses “00” to “4F” for up to 80 character codes, the area not used for display can be used as a
RAM area for general data. When the display is shifted by instruction, the relationship between the LCD
display position and the DDRAM address changes as shown below:
Digit
1
2
3
4
19 20
11 12
(Display shifted to the right)
4F 00 01 02
Digit
1
2
3
4
5
19 20
13 14
(Display shifted to the left) 01 02 03 04 05
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2) Relationship between DDRAM addresses and display positions (2-line display mode)
In the 2-line mode, the ML9042 can display up to 40 characters (20 characters per line) from digit 1 to digit 20.
Digit
1
2
3
4
5
19 20
12 13
Display position
DD RAM
Line 1
Line 2
00 01 02 03 04
address (hexadecimal)
40 41 42 43 44
52 53
Note: The DDRAM address at digit 20 in the first line is not consecutive to the DDRAM address at
digit 1 in the second line.
When the display is shifted by instruction, the relationship between the LCD display position and the DDRAM
address changes as shown below:
Digit
1
2
3
4
5
19 20
11 12
Line 1
Line 2
27 00 01 02 03
(Display shifted to the right)
(Display shifted to the left)
67 40 41 42 43
51 52
Digit
1
2
3
4
5
19 20
13 14
Line 1
Line 2
01 02 03 04 05
41 42 43 44 45
53 54
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Character Generator ROM (CGROM)
The CGROM generates character patterns (5 × 8 dots, 240 patterns) from the 8-bit character code signals in the
DDRAM. The bank switching pin (ROM1S) can switch to the other ROM that generates character patterns (5 × 8
dots, 240 patterns), allowing a total of 480 characters to be controlled.
When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the
character pattern is displayed in the display position specified by the DDRAM address.
Character codes 10 to FF are contained in the ROM area in the CG ROM.
The general character generator ROM codes are 01/11/21.
The relationship between character codes and general purpose character patterns in Bank0 (ROM0) and Bank1
(ROM1) are indicated in Table 2-1 and Table 2-2, respectively.
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Character Generator RAM (CGRAM)
The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes =
512 bits) can store up to 8 character patterns (5 × 8 dots) .
When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F;
hex.) to the DDRAM. This enables outputting the character pattern to the LCD display position corresponding to
the DDRAM address.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
The following describes how character patterns are written in and read from the CGRAM. (See Tables 2-1 and
2-2.)
(1) A method of writing character patterns to the CGRAM from the CPU
The three CGRAM address bit weights 0 to 2 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern in the CGRAM through DB0(SO) to DB7.
The data lines DB0(SO) to DB7 correspond to the CGRAM data bit weights 0 to 7, respectively (see Table
3-1). Input data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since the
ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not
necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bit weights 0 to 2 are all “1”, which means 7
in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display
the cursor.
Whereas the data given by the CGRAM data bit weights 0 to 4 is output to the LCD as display data, the
data given by the CGRAM data bit weights 5 to 7 is not. Therefore, the CGRAM data bit weights 5 to 7
can be used as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit weight 3
of a character code is not used, the character pattern “0” in Table 3-1 can be selected using the character
code “00” or “08” in hexadecimal.
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
(The DDRAM data bit weights 0 to 2 correspond to the CGRAM address bit weights 3 to 5, respectively.)
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Arbitrator RAM (ABRAM)
The arbitrator RAM (ABRAM) stores arbitrator display data.
100 dots can be displayed in both 1-line and 2-line display modes. The arbitrator RAM has the addresses
(hexadecimal) from “00” to “1F” and the valid display address area is from 00 to 19 (0H to 13H). The area of 20 to
31 (14H to 1FH) not used for display can be used as a data RAM area for general data. Even if the display is shifted
by instruction, the arbitrator display is not shifted.
A capacity of 8 bits by 32 addresses (= 256 bits) is available for data write.
First set the mode to increment or decrement from the CPU, and then input the ABRAM address.
Write Display-ON data in the ABRAM through DB0(SO) to DB7.
DB0(SO) to DB7 correspond to the ABRAM data bit weights 0 to 7 respectively. Input data “1” represents the ON
status of an LCD dot and “0” represents the OFF status.
Since ADC is automatically incremented or decremented by 1 after the data is written to the ABRAM, it is not
necessary to set the ABRAM address again.
Whereas ABRAM data bit weights 0 to 4 are output as display data to the LCD, the ABRAM data bit weights 5 to
7 are not. These bits can be used as a RAM area.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
DB6 DB5 DB4 DB3 DB2 DB1 DB0
MSB
ADC
LSB
Hexadecimal
Hexadecimal
The arbitrator RAM can store a maximum of 100 dots of the arbitrator Display-ON data in units of 5 dots.
The relationship with the LCD display positions is shown below.
Relationship between display-ON
data and segment pins
Configuration of input display data
Input data
5XSn+1
5XSn+5
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
*
*
*
E4 E3 E2 E1 E0
* Don’t Care
E4
E0
Display - ON data
Sn = ABRAM address (0 to 19)
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Note: The same CGRAM character patterns are displayed in Bank0 and Bank1.
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Table 3-1 Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 × 7 dot character mode. (Examples)
CG RAM
address
CG RAM data
(Character pattern)
DD RAM data
(Character code)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
5 4 3 2 1 0
MSB
LSB MSB
LSB MSB
0 1 1 1 0
LSB
× ××
0 0 0 0 0 0
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
0 1 1 1 0
0 0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
0 0 0 0 × 0 0 0
1 0 1
1 1 0
1 1 1
××× 1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 0 1 0 0
1 0 0 1 0
1 0 0 0 1
0 0 0 0 0
0 0 1 0 0 0
0 0 1
0 1 0
0 1 1
0 0 0 0 × 0 0 1
1 0 0
1 0 1
1 1 0
1 1 1
1 1 1 0 0 0 × ××
0 0 1
0 1 1 1 0
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 1 1 1 0
0 0 0 0 0
0 1 0
0 1 1
1 0 0
0 0 0 0 × 1 1 1
1 0 1
1 1 0
1 1 1
×: Don’t Care
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Cursor/Blink Control Circuit
This circuit generates the cursor and blink of the LCD.
The operation of this circuit is controlled by the program of the CPU.
The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC
(Address Counter).
For example, when the ADC stores a value of “07” (hexadecimal), the cursor or blink is displayed as follows:
DB6
0
DB0
1
ADC
0
0
2
0
0
1
1
7
Digit
1
3
4
5
6
7
8
9
19 20
12 13
In 1-line display mode
00 01 02 03 04 05 06 07 08
Cursor/blink position
Digit
1
2
3
4
5
6
7
8
9
19 20
12 13
First line
00 01 02 03 04 05 06 07 08
In 2-line display mode
Second line 40 41 42 43 44 45 46 47 48
52 53
Cursor/blink position
Note: The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in
the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is
holding a CGRAM or ABRAM address.
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LCD Display Circuit (COM1 to COM17, SEG1 to SEG100, SSR and CSR)
The ML9042 has 17 common signal outputs and 100 segment signal outputs to display 20 characters (in the 1-line
display mode) or 40 characters (in the 2-line display mode).
The character pattern is converted into serial data and transferred in series through the shift register.
The transfer direction of serial data is determined by the SSR bit. The shift direction of common signals is
determined by the CSR bit. The following tables show the transfer and shift directions:
SSR bit
Transfer direction
SEG1 → SEG100
SEG100 → SEG1
L
H
ABE bit
CSR bit
duty
1/8
AS bit
L
Shift Direction
COM1→COM8
COM1→COM8
COM1→COM16
COM1→COM16
COM8→COM1
COM8→COM1
COM16→COM1
COM16→COM1
COM1→COM9
COM1→COM9
COM1→COM17
COM1→COM17
COM9→COM1
COM9→COM1
COM17→COM1
COM17→COM1
Arbitrator’s common pin
None
L
L
L
L
1/8
H
L
None
L
L
1/16
1/16
1/8
None
L
L
H
L
None
L
H
H
H
H
L
None
L
1/8
H
L
None
L
1/16
1/16
1/9
None
L
H
L
None
H
H
H
H
H
H
H
H
COM9
COM1
COM17
COM1
COM1
COM9
COM1
COM17
L
1/9
H
L
L
1/17
1/17
1/9
L
H
L
H
H
H
H
1/9
H
L
1/17
1/17
H
* Refer to the Expansion Instruction Codes section about the ABE bit, SSR bit, CSR bit, and AS bit.
Signals to be input to the SSR bit, CSR bit, ABE bit, and AS bit should be initially determined at power-on and be
kept unchanged.
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Built-in Reset Circuit
The ML9042 is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is “1” and the ML9042 does not accept any instruction from the CPU
(other than the Read BF instruction).
The Busy Flag is “1” for about 15 ms after the VDD becomes 2.7 V or higher.
During this initialization, the ML9042 performs the following instructions:
1) Display clearing
2) CPU interface data length = 8 bits
3) 1-line LCD display
(DL = “1”)
(N = “0”)
4) ADC counting = Increment
5) Display shifting = None
(I/D = “1”)
(S = “0”)
6) Display = Off
(D = “0”)
7) Cursor = Off
(C = “0”)
8) Blinking = Off
(B = “0”)
9) Arbitrator = Displayed in the lower line
10) Arbitrator = Not displayed
11) Segment shift direction = SEG1 → SEG100
12) Common shift direction = COM1 → COM17
(AS = “0”)
(ABE = “0”)
(SSR = “0”)
(CSR = “0”)
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the
built-in reset circuit may not work properly. In such a case, initialize the ML9042 with the instructions from the
CPU. The use of a battery always requires such initialization from the CPU. (See “Initial Setting of Instructions”)
2.7 V
0.2 V
0.2 V
0.2 V
tON
tOFF
1 ms ≤ tOFF
0.1 ms ≤ tON ≤100 ms
Figure 1 Power-on and Power-off Waveform
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I/F with CPU
Parallel interface mode
The ML9042 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit
microcontroller (CPU).
1) 8-bit interface data length
The ML9042 uses all of the 8 data bus lines DB0(SO) to DB7 at a time to transfer data to and from the CPU.
2) 4-bit interface data length
The ML9042 uses only the higher-order 4 data bus lines DB4 to DB7 twice to transfer 8-bit data to and from the
CPU.
The ML9042 first transfers the higher-order 4 bits of 8-bit data (DB4 to DB7 in the case of 8-bit interface data
length) and then the lower-order 4 bits of the data (DB0(SO) to DB3 in the case of 8-bit interface data length).
The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4
bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is
made, the following data transfer cannot be completed properly.
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RS1
RS0/CSB
RWB/SI
E/SHTB
Busy
(Internal operation)
No
Busy
DR7
IR7
IR6
IR5
IR4
IR3
IR2
DB7
Busy
ADC6
ADC5
ADC4
ADC3
ADC2
DR6
DR5
DR4
DR3
DR2
DB6
DB5
DB4
DB3
DB2
ADC1
ADC0
IR1
IR0
DR1
DR0
DB1
DB0/(SO)
Writing In IR
(Instruction
Register)
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 2 8-Bit Data Transfer
RS1
RS0/CSB
RWB/SI
E/SHTB
Busy
(Internal operation)
No
Busy
IR7
IR6
IR5
IR4
IR3
ADC3
DR7
DR3
DR2
DB7
DB6
DB5
DB4
Busy
ADC6
ADC5
ADC4
IR2
IR1
IR0
ADC2
ADC1
ADC0
DR6
DR5
DR4
DR1
DR0
Writing In IR
(Instruction
Register)
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 3 4-Bit Data Transfer
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Serial Interface Mode
In the Serial I/F Mode, the ML9042 interfaces with the CPU via the RS0/CSB, E/SHTB, RW/SI, and DB0(SO)
pins.
Writing and reading operations are executed in units of 16 bits after the RS0/CSB signal falls down. If the RS0/CSB
signal rises up before the completion of 16-bit unit access, this access is ignored.
When the BF bit is “1”, the ML9042 cannot accept any other instructions. Before inputting a new instruction,
check that the BF bit is “0”. Any access when the BF bit is “1” is ignored.
Data format is LSB-first.
Examples of Access in the Serial I/F Mode
1) WRITE MODE
RS0/CSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
E/SHTB
BUSY
(Internal operation)
D0
D1
D2
D3
D4
D5
D6
D7
1
1
1
1
1
RS0 RS1
1
R/W
RWB/SI
DB(SO)
2) READ MODE
RS0/CSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
E/SHTB
BUSY
(Internal operation)
1
1
1
1
1
RS0 RS1
1
R/W
RWB/SI
DB(SO)
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: Higher 5 bits of each instruction must be input at a “H” level.
Note 2: Lower 8 bits are “don’t care” when the instructions in the READ MODE are set.
Note 3: After one instruction is input, the next instruction must be input after the RS0/CSB pin is pulled at a “H”
level.
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Instruction Codes
Table of Instruction Codes
Code
Execution
Time
f = 270 kHz
Instruction
RS0/ RW/
Function
DB0
RS1
DB7 DB6 DB5 DB4 DB3 DB2 DB1
CSB SI
(SO)
Clears all the displayed digits of the
LCD and sets the DDRAM address 00
in the address counter. The arbitrator
data is cleared.
Display Clear
Cursor Home
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
S
1.52 ms
1.52 ms
37 µs
Sets the DDRAM address 00 in the
address counter and shifts the display
back to the original. The content of the
DDRAM remains unchanged.
Determines the direction of movement
of the cursor and whether or not to shift
the display. This instruction is
Entry Mode
Setting
0
1
1
I/D
executed when data is written or read.
Sets LCD display ON/OFF (D), cursor
ON/OFF (C) or cursor-position
character blinking ON/OFF (B).
Display
ON/OFF Control
1
1
0
0
0
0
0
0
0
0
0
0
0
1
D
C
X
B
X
37 µs
37 µs
Moves the cursor or shifts the display
without changing the content of the
DDRAM.
Cursor/Display
Shift
S/C R/L
Sets the interface data length (DL), the
number of display lines (N), the
ABE SSR CSR arbitrator display (ABE), the segment
data shift direction (SSR), or the
Function Setting
1
0
0
0
0
1
1
DL
N
37 µs
common data shift direction (CSR).
Sets on CGRAM address. After that,
CGRAM data is transferred to and from
the CPU.
CGRAM
Address Setting
1
1
1
0
0
0
0
0
1
0
1
ACG
37 µs
37 µs
0 µs
Sets a DDRAM address. After that,
DDRAM data is transferred to and from
the CPU.
DDRAM
Address Setting
ADD
ADC
Reads the Busy Flag (indicating that
the ML9042 is operating) and the
content of the address counter.
Busy Flag/
Address Read
BF
Writes data in DDRAM, ABRAM or
CGRAM.
RAM Data Write
RAM Data Read
1
1
0
1
1
0
0
1
0
WRITE DATA
READ DATA
37 µs
37 µs
37 µs
Reads data from DDRAM, ABRAM or
CGRAM.
Arbitrator
Display Line Set
0
0
0
1
0
1
0
0
0
1
AS Sets the arbitrator display line.
Sets an ABRAM address. After that,
ABRAM data is transferred to and from
the CPU.
ABRAM
Address Setting
0
0
0
AAB
37 µs
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I/D = “1” (Increment)
I/D = “0” (Decrement)
DD RAM: Display data RAM
The
S = “1” (Shifts the display.)
S/C = “1” (Shifts display.)
R/L = “1” (Right shift)
D/L = “1” (8-bit data)
N = “1” (2 lines)
execution
time is
dependent
upon
frequen-
cies.
CG RAM: Character generator RAM
ABRAM: Arbitrator data RAM
S/C = “0” (Moves the cursor.)
R/L = “0” (Left shift)
DL = “0” (4-bit data)
N = “0” (1 line)
ACG:
ADD:
CGRAM address
DDRAM address
(Corresponds to the cursor
address)
ABE = “1” (Arbitrator displayed)
ABE = “0” (Arbitrator not displayed)
SSR = “1” (Transfer direction: SEG100 → SEG1)
AAB:
ADC:
ABRAM address
SSR = “0” (Transfer direction: SEG1 → SEG100
)
Address counter (Used by
DDRAM, ABRAM and
CGRAM)
—
CSR = “1” (Transfer direction: COMn → COM1)
CSR = “0” (Transfer direction: COM1 → COMn)
BF = “1” (Busy)
BF = “0” (Ready to accept
an instruction)
B = “1” (Enables blinking)
C = “1” (Displays the cursor.)
D = “1” (Displays a character pattern.)
AS = “1” (Arbitrator Displays AS = “0” (Arbitrator Displays
arbitrator on the
upper line)
arbitrator on the
lower line)
×: Don't Care
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Instruction Codes
An instruction code is a signal sent from the CPU to access the ML9042. The ML9042 starts operation as
instructed by the code received. The busy status of the ML9042 is rather longer than the cycle time of the CPU,
since the internal processing of the ML9042 starts at a timing which does not affect the display on the LCD. In the
busy status (Busy Flag is “1”), the ML9042 cannot input the Busy Flag Read instruction only. Therefore, the CPU
should ensure that the Busy Flag is “0” before sending an instruction code to the ML9042.
1) Display Clear
RS1
1
RS0
0
R/W
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
1
0
Instruction Code:
When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry
mode is set to “Increment”. The value of “S” (Display shifting) remains unchanged. The position of the cursor
or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display
mode).
Note: All DDRAM and ABRAM data turn to “20” and “00” in hexadecimal, respectively. The value of the
address counter (ADC) turns to the one corresponding to the address “00” (hexadecimal) of the
DDRAM.
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
2) Cursor Home
RS1
1
RS0
0
R/W
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
1
DB0
0
×
Instruction code:
×: Don’t Care
When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end
of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display
position before shifting.
Note: The value of the address counter (ADC) goes to the one corresponding to the address “00”
(hexadecimal) of the DDRAM).
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
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3) Entry Mode Setting
RS1
1
RS0
0
R/W
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
1
DB1
I/D
DB0
S
0
Instruction code:
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= “1”; increment) or to
the left by 1 character position (I/D= “0”; decrement) after an 8-bit character code is written to or read
from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D =
“1”; increment) or decremented by 1 (when I/D = “0”; decrement). After a character pattern is written to
or read from the CGRAM, the address counter (ADC) is incremented by 1 (when I/D = “1”; increment) or
decremented by 1 (when I/D = “0”; decrement).
Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented by 1
(when I/D = “1”; increment) or decremented by 1 (when I/D = “0”; decrement).
(2) When S = “1”, the cursor or blink stops and the entire display shifts to the left (I/D = “1”) or to the right
(I/D = “0”) by 1 character position after a character code is written to the DDRAM.
In the case of S = “1”, when a character code is read from the DDRAM, when a character pattern is
written to or read from the CGRAM or when data is written to or read from the ABRAM, normal
read/write is carried out without shifting of the entire display. (The entire display does not shift, but the
cursor or blink shifts to the right (I/D = “1”) or to the left (I/D = “0”) by 1 character position.)
When S = “0”, the display does not shift, but normal write/read is performed.
Note: The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of
270 kHz.
4) Display ON/OFF Control
RS1
1
RS0
0
R/W
DB7
0
DB6
0
DB5
0
DB4
0
DB3
1
DB2
D
DB1
C
DB0
B
0
Instruction code:
(1) The “D” bit (DB2) of this instruction determines whether or not to display character patterns on the LCD.
When the “D” bit is “1”, character patterns are displayed on the LCD.
When the “D” bit is “0”, character patterns are not displayed on the LCD and the cursor/blinking also
disappear.
Note: Unlike the Display Clear instruction, this instruction does not change the character code in the
DDRAM .
(2) When the “C” bit (DB1) is “0”, the cursor turns off. When both the “C” and “D” bits are “1”, the cursor
turns on.
(3) When the “B” bit (DB0) is “0”, blinking is canceled. When both the “B” and “D” bits are “1”, blinking is
performed.
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are
alternately displayed.
Note: The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of
270 kHz.
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5) Cursor/Display Shift
RS1
1
RS0
0
R/W
DB7
0
DB6
0
DB5
0
DB4
1
DB3
S/C
DB2
R/L
DB1
DB0
0
×
×
Instruction code:
×: Don’t Care
S/C = “0”, R/L = “0”
S/C = “0”, R/L = “1”
S/C = “1”, R/L = “0”
This instruction shifts left the cursor and blink positions by 1 (decrements the
content of the ADC by 1).
This instruction shifts right the cursor and blink positions by 1 (increments the
content of the ADC by 1).
This instruction shifts left the entire display by 1 character position. The cursor
and blink positions move to the left together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
S/C = “1”, R/L = “1”
This instruction shifts right the entire display by 1 character position. The cursor
and blink positions move to the right together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40
(27; hex) of the first line is shifted right.
When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from
line 1 to line 2 or vice versa).
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
6) Function Setting
RS1
1
RS0
0
R/W
DB7
0
DB6
0
DB5
1
DB4
DL
DB3
N
DB2
DB1
DB0
0
ABE
SSR
CSR
Instruction code:
×: Don’t Care
(1) When the “DL” bit (DB4) of this instruction is “1”, the data transfer to and from the CPU is performed
once by the use of 8 bits DB7 to DB0.
When the “DL” bit (DB4) of this instruction is “0”, the data transfer to and from the CPU is performed
twice by the use of 4 bits DB7 to DB4.
(2) The 2-line display mode is selected when the “N” bit (DB3) of this instruction is “1”. The 1-line display
mode is selected when the “N” bit is “0”.
The arbitrator is displayed when the “ABE” bit (DB2) of this instruction is “1”.
The arbitrator is not displayed when the “ABE” bit (DB2) of this instruction is “0”.
(3) The transfer direction of the segment signal output data is controlled.
When the “SSR” bit (DB1) of this instruction is “1”, the data is transferred from SEG100 to SEG1
.
When the “SSR” bit (DB1) of this instruction is “0”, the data is transferred from SEG1 to SEG100
.
The transfer direction of the common signal output data is controlled.
At 1/n duty,
When the “CSR” bit (DB0) of this instruction is “1”, the data is transferred from COMn to COM1.
When the “CSR” bit (DB0) of this instruction is “0”, the data is transferred from COM1 to COMn.
After the ML9042 is powered on, this function setting should be carried out before execution of any
instruction except the Busy Flag Read. After this function setting, no instructions other than the DL Set
instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
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Number of
display lines
Number of
biases
Number of
common signals
N
ABE
Font size
Duty
0
0
1
1
0
1
0
1
1
1
2
2
5 × 8
5 × 8
5 × 8
5 × 8
1/8
1/9
4
4
5
5
8
9
1/16
1/17
16
17
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270
kHz.
7) CGRAM Address Setting
RS1
RS0
0
R/W
DB7
0
DB6
1
DB5
C5
DB4
C4
DB3
C3
DB2
C2
DB1
C1
DB0
C0
1
0
Instruction code:
This instruction sets the CGRAM address to the data represented by the bits C5 to C0 (binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to
C0 set in the instruction code at that time.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
8) DDRAM Address Setting
RS1
1
RS0
0
R/W
DB7
1
DB6
D6
DB5
D5
DB4
D4
DB3
D3
DB2
D2
DB1
D1
DB0
D0
0
Instruction code:
This instruction sets the DDRAM address to the data represented by the bits D6 to D0 (binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character codes starting from the one represented by the DDRAM address bits D6 to
D0 set in the instruction code at that time.
In the 1-line mode (the “N” bit is “0”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “4F” in hexadecimal.
In the 2-line mode (the “N” bit is “1”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “27” or “40” to “67” in hexadecimal.
If an address other than above is input, the ML9042 cannot properly write a character code in or read it from the
DDRAM.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
9) DDRAM/ABRAM/CGRAM Data Write
RS1
1
RS0
1
R/W
DB7
E7
DB6
E6
DB5
E5
DB4
E4
DB3
E3
DB2
E2
DB1
E1
DB0
E0
0
Instruction code:
A character code (E7 to E0) is written to the DDRAM, Display-ON data (E7 to E0) to the ABRAM or a character
pattern (E7 to E0) to the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is written, the address counter (ADC) is incremented or decremented as set by the Entry Mode
Setting instruction (see 3).
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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10) Busy Flag/Address Counter Read (Execution time: 0 µs)
RS1
1
RS0
0
R/W
DB7
BF
DB6
O6
DB5
O5
DB4
O4
DB3
O3
DB2
O2
DB1
O1
DB0
O0
1
Instruction code:
The “BF” bit (DB7) of this instruction tells whether the ML9042 is busy in internal operation (BF = “1”) or not
(BF = “0”).
When the “BF” bit is “1”, the ML9042 cannot accept any other instructions. Before inputting a new instruction,
check that the “BF” bit is “0”.
When the “BF” bit is “0”, the ML9042 outputs the correct value of the address counter. The value of the
address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and
CGRAM addresses is set in the counter is determined by the preceding address setting.
When the “BF” bit is “1”, the value of the address counter is not always correct because it may have been
incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
RS1
1
RS0
1
R/W
DB7
P7
DB6
P6
DB5
P5
DB4
P4
DB3
P3
DB2
P2
DB1
P1
DB0
P0
1
Instruction code:
A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a
character pattern (P7 to P0) from the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the Entry Mode Setting
instruction (see 3).
Note: Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.
(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input
before this Data Read instruction is input.
(3) When two or more consecutive RAM Data Read instructions are executed, the following read data is
correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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Expansion Instruction Codes
The busy status of the ML9042 is rather longer than the cycle time of the CPU, since the internal processing of the
ML9042 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is “1”), the
ML9042 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is
“0” before sending an expansion instruction code to the ML9042.
1) Arbitrator Display Line Set
RS1
0
RS0
0
R/W
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
1
DB0
AS
0
Expansion instruction code:
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit
and the common outputs is as follows:
For display examples, refer to LCD Drive Waveforms section.
ABE bit
CSR bit
duty
1/8
AS bit
L
Shift direction
COM1→COM8
COM1→COM8
COM1→COM16
COM1→COM16
COM8→COM1
COM8→COM1
COM16→COM1
COM16→COM1
COM1→COM9
COM1→COM9
COM1→COM17
COM1→COM17
COM9→COM1
COM9→COM1
COM17→COM1
COM17→COM1
Arbitrator’s common pin
None
L
L
L
L
1/8
H
L
None
L
L
1/16
1/16
1/8
None
L
L
H
L
None
L
H
H
H
H
L
None
L
1/8
H
L
None
L
1/16
1/16
1/9
None
L
H
L
None
H
COM9
COM1
COM17
COM1
COM1
COM9
COM1
COM17
H
L
1/9
H
L
H
L
1/17
1/17
1/9
H
L
H
L
H
H
H
H
H
H
1/9
H
L
H
1/17
1/17
H
H
Note:
The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of
270 kHz.
2) ABRAM Address Setting
RS1
0
RS0
0
R/W
DB7
0
DB6
1
DB5
1
DB4
H4
DB3
H3
DB2
H2
DB1
H1
DB0
H0
1
Expansion instruction code:
This instruction sets the ABRAM address to the data represented by the bits H4 to H0 (binary).
The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.
The CPU writes or reads the Display-ON data starting from the one represented by the ABRAM address bits H4
to H0 set in the instruction code at that time.
When the ABRAM address represented by bits H4 to H0 (binary) is in the range “00” to “13” in hexadecimal,
data is output to the LCD as the arbitrator.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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Examples of Combinations of ML9042 and LCD Panel
(1) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and no arbitrator
display
(1/8 duty, ABE = “0”, AS = “0” or “1”, CSR = “0”, SSR = “1”)
COM1
Character
COM8
SEG100
SEG1
ML9042
•
COM9 to COM17 output Display-OFF common signals.
(1/8 duty, ABE = “0”, AS = “0” or “1”, CSR = “1”, SSR = “0”)
ML9042
SEG1
SEG100
COM8
COM1
Character
•
COM9 to COM17 output Display-OFF common signals.
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(2) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and the arbitrator
display
(1/9 duty, ABE = “1”, AS = “0”, CSR = “0”, SSH = “1”)
COM1
Character
COM8
COM9
Arbitrator
SEG100
ML9042
SEG1
•
COM10 to COM17 output Display-OFF common signals.
(1/9 duty, ABE = “1”, AS = “1”, CSR = “0”, SSR = “1”)
COM1
COM2
Arbitrator
Character
COM9
SEG100
ML9042
SEG1
•
COM10 to COM17 output Display-OFF common signals.
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(1/9 duty, ABE = “1”, AS = “0”, CSR = “1”, SSR = “0”)
ML9042
SEG100
SEG1
COM9
Character
Arbitrator
COM2
COM1
•
COM10 to COM17 output Display-OFF common signals.
(1/9 duty, ABE = “1”, AS = “1”, CSR = “1”, SSR = “0”)
ML9042
SEG100
SEG1
Arbitrator
Character
COM9
COM8
COM1
•
COM10 to COM17 output Display-OFF common signals.
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(3) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and no arbitrator
display
(1/16 duty, ABE = “0”, AS = “0” or “1”, CSR = “0”, SSR = “1”)
COM1
Character
COM8
COM9
Character
COM16
SEG100
ML9042
SEG1
•
COM17 outputs Display-OFF common signal.
(1/16 duty, ABE = “0”, AS = “0” or “1”, CSR = “1”, SSR = “0”)
ML9042
SEG100
SEG1
COM16
Character
Character
COM9
COM8
COM1
•
COM17 outputs Display-OFF common signal.
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(4) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and the arbitrator
display
(1/17 duty, ABE = “1”, AS = “0”, CSR = “0”, SSR = “1”)
COM1
Character
COM8
COM9
Character
COM16
COM17
Arbitrator
SEG100
ML9042
SEG1
(1/17 duty, ABE = “1”, AS = “1”, CSR = “0”, SSR = “1”)
COM1
COM2
Arbitrator
Character
COM9
COM10
COM17
Character
SEG100
SEG1
ML9042
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(1/17 duty, ABE = “1”, AS = “0”, CSR = “1”, SSR = “0”)
ML9042
SEG100
SEG1
COM17
Character
COM10
COM9
Character
Arbitrator
COM2
COM1
(1/17 duty, ABE = “1”, AS = “1”, CSR = “1”, SSR = “0”)
ML9042
SEG100
SEG1
Arbitrator
Character
COM17
COM16
COM9
COM8
COM1
Character
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EXAMPLES OF VLCD GENERATION CIRCUITS
•
With 1/4 bias, a voltage multiplier
BE
VIN
VDD
Reference potential
for voltage multiplier
VC
VCC
+
VOUT
V0
V1
ML9042
+
V2
V3A
V3B
V4
GND
•
With 1/4 bias, no voltage multiplier
1) Apply VDD to VOUT and V0.
2) Apply VDD to VOUT, and apply the V0 level to V0 externally.
BE
VIN
VDD
VC
VCC
VOUT
V0
V1
V0 level
ML9042
V2
V3A
V3B
V4
GND
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•
With 1/5 bias, a voltage multiplier
BE
VIN
VDD
Reference potential
for voltage multiplier
VC
VCC
+
VOUT
V0
V1
ML9042
+
V2
V3A
V3B
V4
GND
•
With 1/5 bias, no voltage multiplier
1) Apply VDD to VOUT and V0.
2) Apply VDD to VOUT, and apply the V0 level to V0 externally.
BE
VIN
VDD
VC
VCC
VOUT
V0
V1
V0 level
ML9042
V2
V3A
V3B
V4
GND
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LCD Drive Waveforms
The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/9 and 1/17 duties).
See 1) and 2) below.
The relationship between the duty ratio and the frame frequency is as follows:
Duty ratio
1/8
Frame Frequency
84.4 Hz
1/9
75.0 Hz
1/16
84.4 Hz
1/17
79.4 Hz
Note: At an oscillation frequency (OSC) of 270 kHz
1) COM and SEG Waveforms on 1/9 Duty (ABE = “1”)
CSR=“H”
CSR=“L”
2
1
9
8
7
6
3
7
2
8
1
9
9
1
8
2
7
3
6
4
3
7
2
8
1
9
9
1
8
2
···
···
···
···
8
9 1 2 3 4
COM1 (CSR = “L”, AS = “L”)
COM2 (CSR = “L”, AS = “H”)
COM9 (CSR = “H”, AS = “L”)
COM8 (CSR = “H”, AS = “H”)
(first character line)
V0
V1
V2, V3B
V4
V5
1 frame
COM2 (CSR = “L”, AS = “L”)
COM3 (CSR = “L”, AS = “H”)
COM8 (CSR = “H”, AS = “L”)
COM7 (CSR = “H”, AS = “H”)
(second character line)
V0
V1
V2, V3B
V4
V5
COM8 (CSR = “L”, AS = “L”)
COM9 (CSR = “L”, AS = “H”)
COM2 (CSR = “H”, AS = “L”)
COM1 (CSR = “H”, AS = “H”)
(eighth character line)
V0
V1
V2, V3B
V4
V5
COM9 (CSR = “L”, AS = “L”)
COM1 (CSR = “L”, AS = “H”)
COM1 (CSR = “H”, AS = “L”)
COM9 (CSR = “H”, AS = “H”)
(arbitrator line)
V0
V1
V2, V3B
V4
V5
V0
V1
V2, V3B
V4
COM10 to
COM17
V5
Display
turning-off
waveform
V0
V1
SEG
V2, V3B
V4
V5
Display
turning-on
waveform
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FEDL9042-01
OKI Semiconductor
ML9042-xx
2) COM and SEG Waveforms on 1/17 Duty (ABE = “1”)
2 1 1716 15 14 13 12 11 10 9
8
7
6
5
2
1 17 16 15 14
CSR=“H”
CSR=“L”
···
···
16 17 1 9 10 11 12 13
2
3
4
5
6
7
8
16 17 1
2 3 4
V0
V1
V2
COM1 (CSR = “L”, AS = “L”)
COM2 (CSR = “L”, AS = “H”)
COM17 (CSR = “H”, AS = “L”)
COM16 (CSR = “H”, AS = “H”)
V3A (V3B
)
V4
V5
(first character line)
1 frame
V0
V1
V2
COM2 (CSR = “L”, AS = “L”)
COM3 (CSR = “L”, AS = “H”)
COM16 (CSR = “H”, AS = “L”)
COM15 (CSR = “H”, AS = “H”)
V3A (V3B
)
V4
V5
(second character line)
V0
V1
V2
COM16 (CSR = “L”, AS = “L”)
COM17 (CSR = “L”, AS = “H”)
COM2 (CSR = “H”, AS = “L”)
COM1 (CSR = “H”, AS = “H”)
V3A (V3B
)
V4
V5
(sixteenth character line)
V0
V1
V2
COM17 (CSR = “L”, AS = “L”)
COM1 (CSR = “L”, AS = “H”)
COM1 (CSR = “H”, AS = “L”)
COM17 (CSR = “H”, AS = “H”)
V3A (V3B
)
V4
V5
(arbitrator line)
Display
turning-off
waveform
V0
V1
V2
SEG
V3A (V3B
)
V4
V5
Display
turning-on
waveform
47/58
FEDL9042-01
OKI Semiconductor
ML9042-xx
Initial Setting of Instructions
(a) Data transfer from and to the CPU using 8 bits of DB0 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.7 V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 µs or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 µs or more).
9) Set “8 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)
10) Check the Busy Flag for No Busy.
11) Execute the Display ON/OFF control Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
12) Check the Busy Flag for No Busy.
13) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS1
1
RS0
0
R/
W
DB7
0
DB6
0
DB5
1
DB4
1
DB3
DB2
DB1
DB0
0
×
×
×
×
×: Don’t Care
(b) Data transfer from and to the CPU using 4 bits of DB4 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.7 V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 µs or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 µs or longer).
9) Set “4 bits” with the Function Setting instruction.
10) Wait for 100 µs or longer.
11) Set “4 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction. (After this,
the number of LCD lines and the font size cannot be changed.)
12) Check the Busy Flag for No Busy.
13) Execute the Display ON/OFF control Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
14) Check the Busy Flag for No Busy.
15) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS1
1
RS0
0
R/W
DB7
0
DB6
0
DB5
1
DB4
1
0
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FEDL9042-01
OKI Semiconductor
ML9042-xx
An example of instruction code for 9)
RS1
1
RS0
0
R/W
DB7
0
DB6
0
DB5
1
DB4
0
0
*: From 11), input data twice by the use of 4-bit data.
*: In 13), check the Busy Flag for No Busy before executing each instruction.
(c) Data transfer from and to the CPU using the serial I/F
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.7 V or higher.
3) Check the busy flag for No Busy.
4) Set “Number of LCD lines” and “Font size” with the Function Setting Instruction. (After this, the
number of LCD lines and the font size cannot be changed.)
5) Check the busy flag for No Busy.
6) Execute the Display ON/OFF control Instruction, the Display Clear Instruction, the Entry Mode
Instruction and the Arbitrator Display Line Setting Instruction.
7) Check the busy flag for No Busy.
8) Initialization is completed.
*: In 6), check the Busy Flag for No Busy before executing each instruction.
49/58
FEDL9042-01
OKI Semiconductor
ML9042-xx
ML9042-xx CVWA/DVWA PAD CONFIGURATION
Pad Layout
Chip Size:
Chip Thickness: 625±20 µm
Bump Size: 100 × 44 µm
7.8 × 1.8 mm
Y
220
115
114
221
X
233
101
1
100
Pad Coordinates
Pad
1
Symbol
X (µm)
Y (µm)
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
Pad
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
DUMMY
E/SHTB
E/SHTB
DUMMY
DUMMY
DB0/SO
DB0/SO
DUMMY
DUMMY
DB1
X (µm)
-2250
-2175
-2100
-2025
-1950
-1875
-1800
-1725
-1650
-1575
-1500
-1425
-1350
-1275
-1200
-1125
-1050
-975
Y (µm)
DUMMY
OSC2
-3750
-3675
-3600
-3525
-3450
-3375
-3300
-3225
-3150
-3075
-3000
-2925
-2850
-2775
-2700
-2625
-2550
-2475
-2400
-2325
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
2
OSCR5
OSCR3
OSC1
3
4
5
DUMMYGND
T1
6
7
T2
8
T3
9
ROM1S
DUMMYVDD
RS1
10
11
12
13
14
15
16
17
18
19
20
DB1
DUMMY
DUMMY
DB2
RS1
RSO/CSB
RSO/CSB
DUMMY
DUMMY
RW/SI
DB2
DUMMY
DUMMY
DB3
RW/SI
DB3
-900
DUMMY
DUMMY
-825
50/58
FEDL9042-01
OKI Semiconductor
ML9042-xx
Pad
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Symbol
X (µm)
-750
-675
-600
-525
-450
-375
-300
-225
-150
-75
Y (µm)
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
–750
Pad
81
Symbol
V0
X (µm)
2250
2325
2400
2475
2550
2625
2700
2775
2850
2925
3000
3075
3150
3225
3300
3375
3450
3525
3600
3675
3750
3750
3750
3750
3750
3750
3750
3750
3750
3750
3750
3750
3750
3750
3675
3605
3535
3465
3395
3325
Y (µm)
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-750
-462
-392
-322
-252
-182
-112
-42
DUMMY
DB4
V0
82
DB4
V0
83
DUMMY
DUMMY
DB5
V0
84
V1
85
V2
86
DB5
V2
87
DUMMY
DUMMY
DB6
V3A
88
V3A
89
V3B
90
DB6
0
V3B
91
DUMMY
DUMMY
DB7
75
V4
92
150
VC
93
225
VC
94
DB7
300
VC
95
DUMMYVDD
SP
375
VC
96
450
VCC
97
GND
GND
GND
GND
GND
GND
BE
525
VCC
98
600
VCC
99
675
DUMMY
DUMMY
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
SEG100
SEG99
SEG98
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
750
825
900
975
VDD
1050
1125
1200
1275
1350
1425
1500
1575
1650
1725
1800
1875
1950
2025
2100
2175
VDD
VDD
VDD
28
VDD
98
VDD
168
TESTIN
TESTIN
TESTOUT
TESTOUT
VIN
238
308
378
448
750
VIN
750
VOUT
750
VOUT
750
V0
750
V0
750
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FEDL9042-01
OKI Semiconductor
ML9042-xx
Pad
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Symbol
X (µm)
3255
3185
3115
3045
2975
2905
2835
2765
2695
2625
2555
2485
2415
2345
2275
2205
2135
2065
1995
1925
1855
1785
1715
1645
1575
1505
1435
1365
1295
1225
1155
1085
1015
945
Y (µm)
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
Pad
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
X (µm)
455
Y (µm)
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
385
315
245
175
105
35
-35
-105
-175
-245
-315
-385
-455
-525
-595
-665
-735
-805
-875
-945
-1015
-1085
-1155
-1225
-1295
-1365
-1435
-1505
-1575
-1645
-1715
-1785
-1855
-1925
-1995
-2065
-2135
-2205
-2275
875
805
735
665
595
525
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FEDL9042-01
OKI Semiconductor
ML9042-xx
Pad
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
Symbol
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
X (µm)
-2345
-2415
-2485
-2555
-2625
-2695
-2765
-2835
-2905
-2975
-3045
-3115
-3185
-3255
-3325
-3395
-3465
-3535
-3605
-3675
-3750
-3750
-3750
-3750
-3750
-3750
-3750
-3750
-3750
-3750
-3750
-3750
-3750
Y (µm)
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
750
448
378
308
238
168
98
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
DUMMY
28
-42
-112
-182
-252
-322
-392
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FEDL9042-01
OKI Semiconductor
ML9042-xx
ML9042-xx CVWA/DVWA ALIGNMENT MARK SPECIFICATION
Alignment Mark Coordinates
Y
A
B
....................................................................................................
:
:
:
:
(0, 0)
X
C
....................................................................................................
Alignment Mark
X (µm)
–3770
3770
Y (µm)
770
A
B
C
770
3770
–770
The coordinates (X, Y) indicate the distances to the center of an alignment mark (the center of the maximum
outline of the L shape).
Alignment Mark Layer
Gold bump
Alignment Mark Gold Bump Specification
Symbol
Parameter
Mark
Size (µm)
a
b
Alignment Mark Width
Alignment Mark Size
A, B, C
A, B, C
30
80
b
a
b
+
a
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FEDL9042-01
OKI Semiconductor
ML9042-xx
ML9042-xx CVWA GOLD BUMP SPECIFICATION (HIGH HARDNESS)
Gold Bump Specification
(Unit: µm)
Symbol
Parameter
Bump Pitch (I/O Section: Pitch Direction)
Bump Size (I/O Section: Pitch Direction)
Bump Size (I/O Section: Depth Direction)
Bump-to-Bump Distance (I/O Section: Pitch Direction)
Bump Size (L-mark Section: Length)
Bump Size (L-mark Section: Width)
Sliding of Total Bump Pitches
MIN
70
40
96
22
76
26
—
TYP
—
MAX
A
B
C
D
E
F
—
48
104
30
84
34
2
44
100
26
80
30
—
G
Bump Height
10
—
15
—
20
4
H
Bump Height Dispersion Inside Chip (Range)
Bump Edge Height
I
—
—
5
J
K
Shear Strength (g)
27
50
—
—
130
Bump Hardness (Hv: 25 g load)
90
ꢀ Wafer Thickness; 625 ±20 µm
ꢀ Chip Size; 7.80 mm × 1.80 mm
Top View and Cross Section View
A
B
D
[I/O Section]
[L-Alignment Mark]
[Cross Section View]
55/58
FEDL9042-01
OKI Semiconductor
ML9042-xx
ML9042-xx CVWA GOLD BUMP SPECIFICATION (LOW HARDNESS)
Gold Bump Specification
(Unit: µm)
Symbol
Parameter
Bump Pitch (I/O Section: Pitch Direction)
Bump Size (I/O Section: Pitch Direction)
Bump Size (I/O Section: Depth Direction)
Bump-to-Bump Distance (I/O Section: Pitch Direction)
Bump Size (L-mark Section: Length)
Bump Size (L-mark Section: Width)
Sliding of Total Bump Pitches
MIN
70
40
96
22
76
26
—
TYP
—
MAX
A
B
C
D
E
F
—
48
104
30
84
34
2
44
100
26
80
30
—
G
Bump Height
10
—
15
—
20
4
H
Bump Height Dispersion Inside Chip (Range)
Bump Edge Height
I
—
—
5
J
K
Shear Strength (g)
27
30
—
—
80
Bump Hardness (Hv: 25 g load)
—
ꢀ Wafer Thickness; 625 ±20 µm
ꢀ Chip Size; 7.80 mm × 1.80 mm
Top View and Cross Section View
A
B
D
[I/O Section]
[L-Alignment Mark]
[Cross Section View]
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FEDL9042-01
OKI Semiconductor
ML9042-xx
REVISION HISTORY
Page
Document
No.
Date
Description
Previous Current
Edition
Edition
PEDL9042-01
Jun. 16, 2003
–
–
Preliminary first edition
5
5
Changed descriptions of Symbols VC and VCC
Changed DC Characteristics
Condition
VDD = 4.5 to 5.5V→VDD = 4.0 to 5.5V
Ta = 25°C→Ta =- 20 to 75°C
Spec
8
8
Min. 175 Typ. 270 Max. 365
→Min. 200 Typ. 270 Max. 351
Min. 175 Typ. 270 Max. 365
→Min. 200 Typ. 280 Max. 364
Added of table
Partially changed figure of generation circuits
(VC+)→(VCC+) and V2,V3A,V3B
Partially changed figure of generation circuits
(VC+)→(VCC+)
FEDL9042-01
Nov. 19, 2003
25
44
25
44
45
45
57/58
FEDL9042-01
OKI Semiconductor
NOTICE
ML9042-xx
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
58/58
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