MSC1162 [OKI]
40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver; 40位真空荧光显示管网/阳极驱动器
| 型号： | MSC1162 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver |
| 文件： | 总14页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2C0034-27-Y5
This version: Nov. 1997
Previous version: Jul. 1996
¡ Semiconductor
MSC1162A
40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver
GENERAL DESCRIPTION
TheMSC1162AisamonolithicICdesignedfordirectlydrivingthegridandanodeofthevacuum
fluorescent display tube. The device contains a 40-bit bidirectional shift register, a 40-bit latch
circuit, and 40-output circuit on a single chip.
Display data is serially stored in the shift register at the rising edge of a clock pulse.
Setting the CL pin low allows all the driver outputs to be driven low, which makes it possible to
set the display blanking.
Also, setting both of the CL and CHG pins high allows all the driver outputs to be driven high,
which provides the easy testing of all lights after final assembly of a VFD tube panel.
The MSC1162A is compatible with the MSC1162.
FEATURES
• Logic Supply Voltage (V ) : 5V
CC
• Driver Supply Voltage (V ): 65V
HV
• Driver Output Current
I
I
I
(Only one driver output : "H") : –40mA
(All the driver outputs : "H") : –2mA
:1mA
OHVH1
OHVH2
OHVL
• Directly connected to VFD tube without pull-down resistors
• Data Transfer Speed: 4MHz
• Package :
60-pin plastic SSOP (SSOP60-P-700-0.65-BK) (Product name : MSC1162AGS-BK)
1/14
¡ Semiconductor
MSC1162A
BLOCK DIAGRAM
VHV
VCC
VCC
CL
CHG
LS
DIN
CLK
C
SI
HVO1
HVO2
PO1
I-1
I-2
O-1
O-2
PO2
40-Bit Bi-
40-Bit
Latch
directional
Shift
Register
HVO40
DOUT
PO40
SO
I-40 O-40
GND1
GND2
2/14
¡ Semiconductor
MSC1162A
INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic portion Input/Output Circuits and Driver Output Circuits
Input Pin
VCC
VCC
INPUT
GND1
GND2
Output Pin
VCC
VCC
DOUT
GND2
GND1
3/14
¡ Semiconductor
MSC1162A
Driver Output Circuit
VHV
VHV
Output
GND 1
GND 1
4/14
¡ Semiconductor
MSC1162A
PIN CONFIGURATION (TOP VIEW)
HVO
HVO
1
2
1
2
3
4
5
6
7
8
60 HVO 40
59
58
57
56
55
54
53
HVO 39
HVO 38
HVO 37
HVO 36
HVO 35
HVO 34
HVO 33
HVO
HVO
HVO
HVO
HVO
HVO
HVO
3
4
5
6
7
8
9
9
52 HVO 32
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HVO 10
HVO 11
HVO 12
HVO 13
HVO 14
HVO 15
HVO 16
HVO 17
HVO 18
HVO 19
HVO 20
VHV
GND 1
GND 2
CL
NC
LS
NC
R/L
DIN
VCC
HVO 31
HVO 30
HVO 29
HVO 28
HVO 27
HVO 26
HVO 25
HVO 24
HVO 23
HVO 22
HVO 21
VHV
GND 1
GND 2
NC
CHG
NC
CLK
NC
DOUT
VCC
NC : No-connection pin
60-Pin Plastic SSOP
5/14
¡ Semiconductor
MSC1162A
PIN DESCRIPTION
Symbol
Type
Description
Shift register clock input pin.
Shift register reads data through DIN while the CLK pin is low state and the data in the shift
register is shifted from one stage to the next stage at the rising edge of the clock.
CLK
I
Serial data input pin of the shift register.
Display data (positive logic) is input in through the DIN pin synchronization with clock.
DIN
I
Serial data output pin of the shift register.
Data is output through the DOUT pin in synchronization with the CLK signal.
When R/L = High, the data of PO40 in the shift register is output through the DOUT pin.
When R/L = Low, the data of PO1 pin in the shift register is output through the DOUT pin.
DOUT
O
Latch strobe input pin
When LS is high, the parallel output data (PO1-40) of the shift register read out. When LS
goes from high to low, the parallel output data (PO1-40) of the shift register is held.
LS
I
I
Clear input pin with a built-in pull-up resistor
The CL pin is normally being set high.
If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in phase
with the corresponding latch outputs (O1 to O40).
If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high
irrespective of the states of the latch outputs.
CL
If the CL pin is set low, the driver outputs are driven low irrespective of the states of the
CHG pin and latch outputs.
This allows display blanking to be set.
Input for testing (with a pull-down resistor)
The CL pin is normally being set low.
If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV40) are in phase
with the corresponding latch outputs (O1 to O40).
If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV40) are low
irrespective of the states of the latch outputs.
CHG
I
If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the
latch outputs.
This provides the easy testing of all lights after final assembly.
High voltage driver outputs for driving VFD tube
The driver outputs are in phase with the corresponding latch outputs (O1 to O40).
The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.
VHO1-40
O
VHV
VCC
Power supply pin for driver circuits of VFD tube
Power supply pin for logic
GND pin for driver circuits of a VFD tube. (D-GND)
Since the GND1 is not be connected to L-GND, connect this pin to the external L-GND.
GND1
GND2
GND pin for the logic circuits. (L-GND)
Since the GND2 pin is not be connected to D-GND, connect this pin to the external D-GND.
6/14
¡ Semiconductor
MSC1162A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Logic Supply Voltage
Driver Supply Voltage
*1
*1, *2
*1
VCC
VHV
Applicable to logic supply pin
Applicable to driver supply pin
Applicable to all input pins
–0.3 to +6.5
–0.3 to +70
V
V
Input Voltage
VIN
VO
–0.3 to VCC +0.3
–0.3 to VCC +0.3
0 to 15
V
V
*1
Output Voltage
Applicable to data output pin
Applicable to driver output pin
Driver Driving Frequency
fDRV
kHz
Withstand Output Voltage
VHVO
Applicable to driver output pin
–0.3 to VHV +0.3
V
*1, *2
Power Dissipation
PD
Rj-a
Ta £ 25°C
Ta > 25°C
—
860
145
mW
°C/W
°C
Package Thermal Resistance
Storage Temperature
*3
TSTG
–55 to +150
Notes: *1 Maximum Supply Voltage with respect to L-GND and D-GND
*2 Permanent damage may be caused if the voltage is supplied over the rating value.
*3 Package Thermal Resistance (between junction and ambient)
The junction temperature (Tj) expressed by the equation indicated below should not
exceed 150°C.
T =P ¥ R +Ta (P: Maximum power consumption)
j
j–a
7/14
¡ Semiconductor
MSC1162A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC
Condition
Min. Max. Unit
Logic Supply Voltage
Driver Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Applicable to logic supply voltage pin
Applicable to driver supply voltage pin
Applicable to all input pins
4.5
10
3.6
—
—
—
5.5
65
V
V
VHV
—
V
VIH
VIL
Applicable to all input pins
1.1
–40
–2
V
IOHVH1
IOHVH2
Only one output is high
Applicable to driver
mA
mA
High Level Driver Output
Current
output pin
All outputs are high
Low Level Driver Output
Current
IOHVL
Applicable to all driver output pins
—
1
mA
CLK Frequency
fCLK
—
75
80
50
140
80
50
0
4
MHz
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ms
°C
CLK Pulse Width
Data Setup Time
Data Hold Time
tw(CLK)
—
—
—
—
—
—
—
—
—
—
—
85
t
SU
(D-CLK)
th(CLK-D)
tw(D)
Data Pulse Width
Latch Probe Pulse Width
See timing diagram
tw(LS)
CLK-LS tsu(CLK-LS)
LS-CLK tsu(LS-CLK)
LS-CHG tsu(LS-CHG)
Setup Time
0
LS-CL
CHG
CL
tsu(LS-CL)
tw(CHG)
tw(CL)
Top
0
—
—
—
2
Pulse Width
2
Operating Temperature
–40
8/14
¡ Semiconductor
MSC1162A
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VCC=4.5 to 5.5V, VHV=10 to 65V, Ta=–40 to +85°C)
Parameter
Symbol
Condition
All input: Low
Min.
Typ.
Max. Unit
ICC1
—
4.3
6.65
mA
1.0
No load
Logic Supply Current
All input: High,
Ta=25°C
VCC=5.5V
ICC2
IHV1
IHV2
—
0.5
—
All input: Low
1.0
3.8
mA
No load
Driver Supply Current
—
All input: High
Ta=25°C
V
CC=5.5V
2.45
mA
V
CC=5.5V, VIN=5.5V
–1
5
—
—
—
—
1
80
1
mA
mA
mA
mA
Inputs excluding CHG
High Level Input Current
IIH
VCC=5.5V, VIN=5.5V
CHG input
VCC=5.5V, VIN=0V
Inputs excluding CL
–1
–5
Low Level Input Current
Input Capacitance
IIL
CI
VCC=5.5V, VIN=0V
–80
CL input
Ta=25°C
VCC=4.5V
—
3.5
15
—
—
—
—
—
—
—
—
—
1.1
1.1
—
—
pF
V
V
V
V
V
V
High Level Data Output
Voltage
VODH IOH=–0.1mA
V
CC=5.5V
VCC=4.5V
CC=5.5V
4.5
—
Low Level Data Output
Voltage
VODL
IOL=0.1mA
V
—
VOHVH1
VOHVH2
VHV–4
IOH=–40mA
IOH=–2mA
High Level Driver Output
Voltage
V
HV–4
Low Level Driver Output
Voltage
VOHVL
IOL=1mA
—
—
3.0
V
AC Characteristics
(VCC=5V, VHV=65V, Ta=25°C)
Parameter
Symbol
tPD
Condition
Min.
Typ.
—
Max. Unit
CLK-DOUT Delay Time
Delay Time Low to High
Transit Time Low to High
Delay Time High to Low
Transit Time High to Low
—
—
—
—
—
—
—
—
—
—
300
1.0
5.0
1.0
5.0
ns
ms
ms
ms
ms
tDLH
0.3
2.0
0.3
2.0
tTLH
tDHL
tTHL
9/14
1/fCLK
T1/2
T1/2
T3/4
T39/40
T3/4
CLK
DIN
tsu(D-CLK) th(CLK-D)
tw(CLK)
tw(D)
tPD
tPD
DOUT
LS
tw(LS)
tsu(CLK-LS)
tsu(LS-CLK)
tsu(LS-CHG)
tw(CHG)
tw(CHG)
CHG
tw(CL)
tw(CL)
tsu(LS-CL)
CL
tDLH
tDHL
tDLH
tDHL
HVO (1, 2, 39, 40)
HVO (OTHERS)
tTLH
tTLH
tTHL
tTHL
¡ Semiconductor
MSC1162A
FUNCTIONAL DESCRIPTION
Function Table
Shift register
Input
Shift Register Parallel Out
Output
DOUT
CLK
R/L
X
DIN
X
PO1
PO2
PO39
PO40
Not changed
Not changed
PO40
H
L
L
PO1n
PO1n
PO3n
PO3n
PO38n
PO38n
PO40n
PO40n
PO39n
H
H
H
PO39n
PO40
L
L
PO2n
PO2n
L
PO1
L
H
H
PO1
X: Don't Care
PO1n to PO40n : PO1 to PO40 data just before CLOCK rises.
Latch
Input
Shift Register Parallel Out
Latch Output
LS
I
POm
Om
X
L
Not changed
H
H
L
H
H
X: Don't Care, m: 1 to 40
Driver output
Input
Latch Output
Driver Output
CL
L
CHG
X
Om
X
HVOm
L
H
L
H
H
X
H
L
L
H
L
H
H
X: Don't Care, m: 1 to 40
11/14
¡ Semiconductor
MSC1162A
NOTES ON USE
1. Connect GND1 to GND2 externally to be an equal potential voltage.
2. The contents of the shift register are undefined when the power is applied.
Therefore, unnecessary driver outputs may be driven high just after power-on, and
the VFD tube may flicker.
To avoid this, follow the procedures:
1) Apply the driver power supply after applying the logic power supply, with the
CL pin remained low.
2) Start displaying by setting the CL pin high after in putting display data the shift
register through the DIN pin.
12/14
¡ Semiconductor
MSC1162A
Test circuit
20pF
VCC
VHV
HVO1
HVO2
1.5kW
65V
5.0V
HVO40
DOUT
30pF
DIN
13/14
¡ Semiconductor
MSC1162A
PACKAGE DIMENSIONS
(Unit : mm)
SSOP60-P-700-0.65-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.21 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
14/14
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