MSC23CV43257D-XXBS8 [OKI]

4,194,304-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO; 4,194,304字×32位动态RAM模块:与EDO快页模式类型
MSC23CV43257D-XXBS8
型号: MSC23CV43257D-XXBS8
厂家: OKI ELECTRONIC COMPONETS    OKI ELECTRONIC COMPONETS
描述:

4,194,304-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
4,194,304字×32位动态RAM模块:与EDO快页模式类型

文件: 总9页 (文件大小:80K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
This version: Mar. 1999  
Semiconductor  
MSC23CV43257D-xxBS8  
4,194,304-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO  
DESCRIPTION  
The MSC23CV43257D-xxBS8 is a fully decoded, 4,194,304-word x 32-bit CMOS dynamic random access memory  
module composed of eight 16Mb DRAMs (4Mx4) in TSOP packages mounted with eight decoupling capacitors on a  
72-pin glass epoxy small outline package. This module supports any application where high density and large  
capacity of storage memory are required.  
FEATURES  
· 4,194,304-word x 32-bit organization  
· 72-pin Small Outline Dual In-line Memory module  
MSC23CV43257D-xxBS8 : Gold tab  
· Single +3.3V supply ± 0.3V tolerance  
· Input  
: LVTTL compatible  
· Output  
: LVTTL compatible, 3-state  
· Refresh : 2048cycles/32ms  
· /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability  
· Fast page mode with EDO capability  
· Multi-bit test mode capability  
· 11/11 Addressing (Row/Column)  
PRODUCT FAMILY  
Cycle  
Time  
Access Time (Max.)  
Power Dissipation  
Family  
tRAC  
60ns  
70ns  
tAA  
tCAC  
15ns  
20ns  
Operating (Max.)  
Standby (Max.)  
(Min.)  
MSC23CV43257D-60BS8  
MSC23CV43257D-70BS8  
30ns  
35ns  
104ns  
124ns  
2592mW  
2304mW  
14.4mW  
Semiconductor  
MSC23CV43257D  
MODULE OUTLINE  
MSC23CV43257D-xxBS8  
(Unit : mm)  
3.80Max.  
25.4±0.13  
3.18±0.13  
2.0±0.13  
5.5Min.  
71  
1
2.62Typ.  
1.00±0.1  
44.45±0.1  
*1 59.69±0.2  
*1 The common size difference of the board width 19.78mm of its height is specified as ±0.2.  
The value above 19.78mm is specified as ±0.5.  
R2.0  
1.0±0.1  
17.78±0.13  
0.25 Max.  
1.8±0.1  
2- 1.8  
72  
2
0.23 Min.  
1.27±0.1  
3.25Typ.  
φ
R2.0  
44.45±0.1  
51.66±0.1  
3.03  
5.00  
Semiconductor  
MSC23CV43257D  
PIN CONFIGURATION  
Front Side  
Pin Name Pin No.  
Back Side  
Pin No.  
1
Pin Name  
DQ16  
VSS  
Pin No.  
2
Pin Name  
Pin No.  
38  
Pin Name  
VSS  
DQ1  
DQ3  
DQ5  
DQ7  
PD1  
A1  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
DQ0  
DQ2  
DQ4  
DQ6  
VCC  
DQ17  
/CAS0  
/CAS3  
/RAS0  
NC  
3
4
40  
5
/CAS2  
/CAS1  
NC  
6
42  
7
8
44  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
46  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
/WE  
A0  
48  
NC  
DQ18  
DQ20  
DQ22  
NC  
A2  
50  
DQ19  
DQ21  
DQ23  
DQ24  
DQ26  
DQ28  
DQ29  
DQ31  
PD2  
A3  
A4  
52  
A5  
A6  
54  
A10  
DQ8  
DQ10  
DQ12  
DQ14  
NC  
NC  
56  
DQ25  
DQ27  
VCC  
DQ9  
DQ11  
DQ13  
A7  
58  
60  
62  
DQ30  
NC  
64  
VCC  
66  
A8  
PD3  
A9  
68  
PD4  
NC  
PD5  
/RAS2  
NC  
70  
PD6  
DQ15  
PD7  
72  
VSS  
Presence Detect Pins  
Pin No.  
11  
Pin Name  
-60  
NC  
NC  
VSS  
NC  
NC  
NC  
NC  
-70  
NC  
NC  
VSS  
NC  
VSS  
NC  
NC  
PD1  
PD2  
PD3  
PD4  
PD5  
PD6  
PD7  
66  
67  
68  
69  
70  
71  
Semiconductor  
MSC23CV43257D  
BLOCK DIAGRAM  
A0-A10  
/RAS0  
/CAS0  
/WE  
/RAS2  
/CAS2  
A0-A10 DQ  
DQ0  
DQ1  
DQ2  
DQ3  
A0-A10 DQ  
DQ16  
DQ17  
DQ18  
DQ19  
/RAS  
/CAS  
/WE  
DQ  
DQ  
DQ  
/OE  
/RAS  
/CAS  
/WE  
DQ  
DQ  
DQ  
/OE  
V
CC  
V
SS  
V
CC  
V
SS  
A0-A10 DQ  
DQ4  
DQ5  
DQ6  
DQ7  
A0-A10 DQ  
DQ20  
DQ21  
DQ22  
DQ23  
/RAS  
/CAS  
/WE  
DQ  
DQ  
DQ  
/OE  
/RAS  
/CAS  
/WE  
DQ  
DQ  
DQ  
/OE  
V
CC  
V
SS  
V
CC  
V
SS  
A0-A10 DQ  
DQ8  
DQ9  
DQ10  
DQ11  
A0-A10 DQ  
DQ24  
DQ25  
DQ26  
DQ27  
/RAS  
/CAS  
/WE  
DQ  
DQ  
DQ  
/OE  
/RAS  
/CAS  
/WE  
DQ  
DQ  
DQ  
/OE  
V
CC  
V
SS  
V
CC  
V
SS  
A0-A10 DQ  
DQ12  
DQ13  
DQ14  
DQ15  
A0-A10 DQ  
DQ28  
DQ29  
DQ30  
DQ31  
/RAS  
/CAS  
/WE  
DQ  
DQ  
DQ  
/OE  
/RAS  
/CAS  
/WE  
DQ  
DQ  
DQ  
/OE  
V
CC  
V
SS  
V
CC  
V
SS  
/CAS1  
/CAS3  
V
CC  
C1-C8  
V
SS  
Semiconductor  
MSC23CV43257D  
ELECTRICAL CHARACTERISTICS  
Absolute Maximum Ratings  
Parameter  
Voltage on Any Pin Relative to VSS  
Voltage on VCC Supply Relative to VSS  
Short Circuit Output Current  
Power Dissipation  
Symbol  
VIN, VOUT  
VCC  
Rating  
-0.5 to +4.6  
-0.5 to +4.6  
50  
Unit  
V
V
IOS  
mA  
W
PD *  
8
Operating Temperature  
TOPR  
0 to +70  
-40 to +125  
°C  
°C  
Storage Temperature  
TSTG  
* Ta = 25°C  
Recommended Operating Conditions  
( Ta = 0°C to +70°C )  
Parameter  
Symbol  
Min.  
3.0  
0
Typ.  
Max.  
Unit  
V
VCC  
VSS  
VIH  
VIL  
3.3  
3.6  
0
Power Supply Voltage  
0
-
V
Input High Voltage  
Input Low Voltage  
2.0  
-0.3  
VCC+0.3  
0.8  
V
-
V
Capacitance  
( VCC = 3.3V ± 0.3V, Ta = 25°C, f = 1 MHz )  
Parameter  
Symbol  
CIN1  
Typ.  
Max.  
57  
Unit  
pF  
Input Capacitance (A0 - A10)  
Input Capacitance (/WE)  
-
-
-
-
-
CIN2  
65  
pF  
Input Capacitance (/RAS0, /RAS2)  
Input Capacitance (/CAS0- /CAS3)  
I/O Capacitance (DQ0 - DQ31)  
CIN3  
35  
pF  
CIN4  
20  
pF  
CDQ  
16  
pF  
Semiconductor  
MSC23CV43257D  
DC Characteristics  
(VCC = 3.3V ± 0.3V, Ta = 0°C to +70°C )  
-60  
-70  
Parameter  
Symbol  
Condition  
Unit  
Note  
Min.  
Max.  
Min.  
Max.  
0V VIN VCC+0.3V;  
All other pins not  
under test = 0V  
Input Leakage Current  
Output Leakage Current  
ILI  
-80  
80  
-80  
80  
µA  
µA  
DQ disable  
0V VOUT VCC  
ILO  
-10  
10  
-10  
10  
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
IOH = -2.0mA  
IOL = 2.0mA  
2.4  
0
VCC  
0.4  
2.4  
0
VCC  
0.4  
V
V
Average Power  
Supply Current  
(Operating)  
/RAS, /CAS cycling,  
tRC = Min.  
ICC1  
-
720  
-
640  
mA  
1, 2  
/RAS, /CAS = VIH  
-
-
16  
4
-
-
16  
4
mA  
mA  
1
1
Power supply current  
(Standby)  
ICC2  
/RAS, /CAS  
VCC -0.2V  
Average Power  
Supply Current  
(/RAS only refresh)  
/RAS cycling,  
/CAS = VIH,  
tRC = Min.  
ICC3  
ICC6  
ICC7  
-
-
-
720  
720  
720  
-
-
-
640  
640  
640  
mA  
mA  
mA  
1, 2  
1, 2  
1, 3  
Average Power  
Supply Current  
(/CAS before /RAS refresh)  
/RAS cycling,  
/CAS before /RAS  
Average Power  
Supply Current  
(Fast Page Mode)  
/RAS = VIL,  
/CAS cycling,  
tHPC = Min.  
Notes: 1. ICC Max. is specified as ICC for output open condition.  
2. The address can be changed once or less while /RAS = VIL.  
3. The address can be changed once or less while /CAS = VIH.  
Semiconductor  
MSC23CV43257D  
AC Characteristics (1/2)  
(VCC = 3.3V ± 0.3V, Ta = 0°C to +70°C ) Note: 1, 2, 3, 10, 11  
-60  
-70  
Parameter  
Symbol  
Unit  
Note  
Min.  
104  
25  
-
Max.  
Min.  
124  
30  
-
Max.  
Random Read or Write Cycle Time  
Fast Page Mode Cycle Time  
Access Time from /RAS  
tRC  
tHPC  
tRAC  
tCAC  
tAA  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
-
-
60  
70  
4, 5, 6  
4, 5  
4, 6  
4
Access Time from /CAS  
-
15  
-
20  
Access Time from Column Address  
Access Time from /CAS Precharge  
Output Low Impedance Time from /CAS  
Data Output Hold After /CAS Low  
/CAS to Data Output Buffer Turn-off Delay Time  
/RAS to Data Output Buffer Turn-off Delay Time  
/WE to Data Output Buffer Turn-off Delay Time  
Transition Time  
-
30  
-
35  
tCPA  
tCLZ  
tDOH  
tCEZ  
tREZ  
-
35  
-
40  
0
-
0
-
4
5
-
5
-
0
15  
0
20  
7,8  
7,8  
7
0
15  
0
20  
WEZ  
t
0
15  
0
20  
tT  
1
50  
1
50  
3
Refresh Period  
tREF  
tRP  
-
32  
-
32  
/RAS Precharge Time  
40  
60  
60  
10  
10  
10  
40  
5
-
50  
70  
70  
13  
10  
13  
45  
5
-
/RAS Pulse Width  
tRAS  
tRASP  
tRSH  
tCP  
10K  
10K  
/RAS Pulse Width (Fast Page Mode with EDO)  
/RAS Hold Time  
100K  
100K  
-
-
/CAS Precharge Time (Fast Page Mode with EDO)  
/CAS Pulse Width  
-
-
tCAS  
tCSH  
tCRP  
tRHCP  
tRCD  
tRAD  
tASR  
tRAH  
tASC  
tCAH  
tRAL  
tRCS  
tRCH  
tRRH  
10K  
10K  
/CAS Hold Time  
-
-
-
-
/CAS to /RAS Precharge Time  
/RAS Hold Time from /CAS Precharge  
/RAS to /CAS Delay Time  
35  
14  
12  
0
-
40  
14  
12  
0
-
45  
30  
-
50  
35  
-
5
6
/RAS to Column Address Delay Time  
Row Address Set-up Time  
Row Address Hold Time  
10  
0
-
10  
0
-
Column Address Set-up Time  
Column Address Hold Time  
-
-
10  
30  
0
-
13  
35  
0
-
Column Address to /RAS Lead Time  
Read Command Set-up Time  
Read Command Hold Time  
-
-
-
-
0
-
0
-
9
9
Read Command Hold Time referenced to /RAS  
0
-
0
-
Semiconductor  
MSC23CV43257D  
AC Characteristics (2/2)  
(VCC = 3.3V ± 0.3V, Ta = 0°C to +70°C ) Note: 1, 2, 3, 10, 11  
-60  
-70  
Parameter  
Symbol  
Unit  
Note  
Min.  
0
Max.  
Min.  
0
Max.  
Write Command Set-up Time  
Write Command Hold Time  
tWCS  
tWCH  
tWP  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10  
10  
10  
10  
10  
0
13  
10  
10  
13  
13  
0
Write Command Pulse Width  
/WE Pulse Width (DQ Disable)  
Write Command to /RAS Lead Time  
Write Command to /CAS Lead Time  
Data-in Set-up Time  
WPE  
t
tRWL  
tCWL  
tDS  
Data-in Hold Time  
tDH  
10  
5
13  
5
/CAS Active Delay Time from /RAS Precharge  
tRPC  
/RAS to /CAS Set-up Time  
(/CAS before /RAS)  
tCSR  
tCHR  
tWRP  
tWRH  
tWTS  
tWTH  
5
-
-
-
-
-
-
5
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
/RAS to /CAS Hold Time  
(/CAS before /RAS)  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
/WE to /RAS Precharge Time  
(/CAS before /RAS)  
/WE Hold Time from /RAS  
(/CAS before /RAS)  
/RAS to /WE Set-up Time  
(Test Mode)  
/RAS to /WE Hold Time  
(Test Mode)  
Semiconductor  
MSC23CV43257D  
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles  
(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.  
2. The AC characteristics assumes tT = 2ns.  
3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are  
measured between VIH and VIL.  
4. This parameter is measured with a load circuit equivalent to 1TTL loads and 100pF.  
The output timing reference levels are VOH = 2.0V and VOL = 0.8V.  
5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met.  
tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then  
the access time is controlled by tCAC  
.
6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met.  
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then  
the access time is controlled by tAA.  
7. tCEZ(Max.), tREZ(Max.) and tWEZ(Max.) define the time at which the output achieves the open circuit  
condition and are not referenced to output voltage levels.  
8. tCEZ or tREZ must be satisfied for open circuit condition.  
9. tRCH or tRRH must be satisfied for a read cycle.  
10. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is  
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet  
is an 8-bit parallel test function. In a test mode CA0, CA1 and CA10 are not used. In a read cycle, if 8  
data bits are equal, the DQ pin will indicate a high level. If the 8 data bits are not equal, the DQ pin will  
indicate a low level. The test mode is cleared and the memory device returned to its normal operating  
state by performing a /RAS only refresh cycle or a /CAS before /RAS refresh cycle.  
11. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.  
These parameters should be specified in test mode cycle by adding the above value to the specified  
value in this data sheet.  

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