MSC7170-01 [OKI]
5x7 Dot Character x 16-Digit x 2-Line Display Controller/Driver with Keyscan Function; 5×7点阵字符x 16位×2行显示控制器/驱动器，带有键扫描功能
| 型号： | MSC7170-01 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 5x7 Dot Character x 16-Digit x 2-Line Display Controller/Driver with Keyscan Function |
| 文件： | 总27页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7170-03
This version: Sep. 2000
Previous version: Nov. 1997
¡ Semiconductor
MSC7170-01
5¥7 Dot Character ¥ 16-Digit ¥ 2-Line Display Controller/Driver with Keyscan Function
GENERAL DESCRIPTION
The MSC7170-01 is a display controller/segment driver containing a 5 ¥ 6 keyscan circuit,
designed for a 5 ¥ 7 dot matrix type vacuum fluorescent (VF) display tube.
Use of the MSC1164 grid driver allows a maximum of 16-digit pair to be displayed, or use of the
MSC7171 grid driver allows a maximum of 12 digit pairs to be displayed.
FEATURES
• Able to display 5 ¥ 7 dot matrix type characters of a maximum of 16 digits ¥ 2 lines (when
MSC1164 is used)
• The number of display digits selectable in a range of 1 digit ¥ 2 lines to 16 digits ¥ 2 lines
• Standby function
Combination of the MSC7171 grid driver and the MSC7170-01 decreases grid driver current
during the standby mode of the driver.
• Display intensity selectable by 10-bit digital dimming
• Display characters selectable from among 256 types by internal PLA
• 8-bit synchronous serial data transfer
SPI interface
• 5 ¥ 6 keyscan circuit
• Driver output current (I
1 mA (SEG1 to SEG35) : –15 mA (SEG36)
OH
) :
• Supply voltage: V
V
DD
DISP
= 60 V (max.)
= 5 V±10% :
• Package:
100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name: MSC7170-01GS-BK)
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FEDL7170-03
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¡ Semiconductor
BLOCK DIAGRAM
ROW
COL
1 2 3 4 5
1 2 3 4 5 6
VDISP
SEG1-1
SEG1-2
ROW 1 CURSOR
DATA BUFFER
16b
5¥6KEYBOARD SCANNER
KBINT
36
SEG
DRIVER
LATCH
VDD
RESET
ROW 1 DISPLAY
DATA BUFFER
16w¥8b
8
8
8
SEG1-36
LATCH
LATCH
35
CHARACTER
GENERATOR
256w¥35b
8
ENABLE
SIMO
ROW 2 DISPLAY
DATA BUFFER
16w¥8b
35
SHIFT
REGISTER
SEG2-1
SEG2-2
SCLK
SOMI
36
SEG
DRIVER
LATCH
8
ROW 2 CURSOR
DATA BUFFER
16b
SEG2-36
VSS1
LATCH
8
5
8
8
ADDRESS SELECTOR
5
COMMAND
DECODER
4
WRITE
ADDRESS
COUNTER
READ
ADDRESS
COUNTER
5
CONTROLLER
DIGIT
COUNT
REGISTER
GRID
DRIVER
INTERFACE
STANDBY
DATA
4
8
4
4
4
ADDRESS
COMPARE
TIMING
GENERATOR
CLOCK
BLANK
DUTY
AND
BLANK
DUTY
CYCLE
COUNTER
VSS2
OSCI
AC
FILAMENT
SYNC
GENERATOR
OSC
DUTY
OSCO
SYNC
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FEDL7170-03
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¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
VDISP
1
SEG 2-21
2
SYNC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DATA
CLOCK
DUTY
STANDBY
VSS2
SEG 2-22
SEG 2-23
SEG 2-24
SEG 2-25
SEG 2-26
SEG 2-27
SEG 2-28
SEG 2-29
SEG 2-30
SEG 2-31
SEG 2-32
SEG 2-33
SEG 2-34
SEG 2-35
SEG 2-20
SEG 2-19
SEG 2-18
SEG 2-17
3
4
5
6
7
SEG 1-21
SEG 1-36
SEG 1-22
SEG 1-23
SEG 1-24
SEG 1-25
SEG 1-26
SEG 1-27
SEG 1-28
SEG 1-29
SEG 1-30
SEG 1-31
SEG 1-32
SEG 1-33
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG 2-16
SEG 2-15
SEG 2-14
SEG 1-34
SEG 1-35
SEG 1-20
SEG 2-13
SEG 2-12
SEG 1-19
SEG 1-18
SEG 2-11
SEG 2-10
SEG 1-17
SEG 1-16
SEG 2-9
SEG 2-8
SEG 2-7
SEG 1-15
SEG 1-14
SEG 1-13
100-Pin Plastic QFP
Note:
SEGn-x sequence depends on ROM code content and may be altered by changing
segment number x relationship to ROM bit number. See Correspondence between
Segment Output and VF Display Tube Dots.
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FEDL7170-03
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¡ Semiconductor
PIN DESCRIPTIONS
Pin
Symbol
Description
1
VDISP
High voltage power supply
SEG2-1 to
SEG2-35
VF tube 5¥7 dot anode driver outputs. These pins may be connected directly to
2-36
37
the VF tube.
SEG2-36
VF tube cursor driver output.
VF tube 5¥7 dot anode driver outputs. These pins may be connected directly to
SEG1-1
SEG1-2
38-39
40
the VF tube.
VSS1
High voltage ground
VF tube 5¥7 dot anode driver outputs. These pins may be connected directly to
SEG1-3 to
SEG1-35
41-72
73
the VF tube.
SEG1-36
VF tube cursor driver output.
VF tube 5¥7 dot anode driver output. This pin may be connected directly to
the VF tube.
74
75
76
SEG1-21
VSS2
Logic supply ground.
Grid driver standby output pin. A logic high level on this output forces the grid
driver (MSC7171) into a low power standby mode.
STANDBY
77
78
DUTY
Duty cycle output pin.
CLOCK
Grid driver clock output pin.
79
80
DATA
SYNC
Grid driver data output pin.
AC filament synchronization input pin.
81
82
OSCO
OSCI
Oscillator output pin.
Oscillator input pin.
Reset input pin.
Connects to crystal (or ceramic resonator) oscillator and
capacitor. These pins have internal feedback resistors.
83
RESET
SPI data output pin. Keyscan data is shifted out on the falling edge of SCLK.
84
85
SOMI
SCLK
SPI clock input pin. Data is shifted in on the SIMO pin on the rising edge of SCLK.
SPI data input pin. Command data is shifted in on the rising edge of SCLK.
86
87
SIMO
Chip select input pin. Interface to the microprocessor is possible only when a
logic low level is applied to this pin. The SOMI output pin is tri-stated when
ENABLE is at a logic high level so that multiple devices may use the SPI network.
ENABLE
Interrupt request output to the microprocessor for keyscan data read out.
Keyscanning is started when any key is depressed or released. After completion
of one cycle, KBINT goes to a logic low level to indicate new keyscan data is
available. KBINT remains low until execution of Keyscan Data Output command.
88
KBINT
Column 1-6 input pins from key switch matrix. A pull-up resistor is built in so that
the pin is in the logic high state except when a key is depressed and a logic low
level is input to the pin.
89-94
COL6-1
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FEDL7170-03
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¡ Semiconductor
Pin
Symbol
Description
Row 1-5 scanning signal output pins to key switch matrix. When any key is
depressed or released, keyscanning is started and is continued until Keyscan Data
Output command is executed. All Row 1-5 outputs go to logic low level when
keyscanning is stopped.
95-99
ROW5-1
100
VDD
Logic voltage supply.
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¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS
Parameter
Logic Supply Voltage
Driver Supply Voltage
Input Voltage
Symbol
VDD
Condition
Rating
–0.3 to 6.0
Unit
V
—
—
*1
VDISP
VIN
–0.3 to 65*1, 2
–0.3 to VDD+0.3 *1
663
V
Applies to all inputs
Ta£25∞C
V
Power Dissipation
PD
mW
Package Thermal Resistance
Rj-a
—
98
–2
*3 °C/W
mA
SEG1-1 to SEG1-35
SEG2-1 to SEG2-35
SEG1-36, SEG2-36
—
Driver Output Current
Storage Temperature
—
–2
mA
–15
mA
TSTG
–65 to 150
°C
Notes: *1 Voltage that can be applied to GND
*2 Stresses beyond the rating may cause permanent damage to the device.
*3 Package thermal resistance between junction and atomsphere.
Junction temperature T in the following expression must not exceed 150°C:
j
T = P ¥ R + Ta (P: maximum IC power consumption)
j
j-a
RECOMMENDED OPERATING CONDITIONS
Parameter
Logic Circuit Supply Voltage
Driver Supply Voltage
Operating Temperature
Symbol
VDD
Condition
Usable only for logic power terminal
Usable only for driver power terminal
—
Range
4.5 to 5.5
7 to 60
Unit
V
VDISP
Top
V
–40 to 85
°C
6/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta=–40 to 85°C, VDD=4.5 to 5.5 V, VDISP=7 to 60 V)
Parameter
Symbol
VIH
Condition
Min.
0.7 VDD
—
Max.
—
Unit
V
Applied Pin
All inputs
"H" Input Voltage
"L" Input Voltage
—
—
VIL
0.3 VDD
V
All inputs
SIMO, SCLK, ENABLE,
IIH1
IIH2
IIL1
IIL2
–1
–30
–1
1
30
1
mA
mA
mA
VDD=5.5 V
VIN=VDD
RESET
"H" Input Current
"L" Input Current
COL1 6, SYNC
SIMO, SCLK, ENABLE,
RESET
VDD=5.5 V
VIN=0.5 V
–15
–160
—
mA
V
COL1-6, SYNC
OSCO
VOH1 IOH=–500 mA
VDD–0.6
VDISP–3
VDISP–4
VOH2 IOH=–1 mA
—
V
SEGn-1 to n-35, n=1, 2
SEG1-36, SEG2-36
"H" Output Voltage VOH3 IOH=–15 mA
—
V
DUTY, SOMI, KBINT
DATA, CLOCK, STANDBY
VOH4 IOH=–200 mA
4
—
V
VOL1
VOL2
VOL3
IOL=500 mA
IOL=100 mA
IOL=3 mA
—
—
—
VSS+0.6
V
V
V
OSCO
2.5
3
SEGn-1 to n-35, n=1, 2
SEG1-36, SEG2-36
"L" Output Voltage
ROW1-5, DUTY,
VOL4
IOL=200 mA
—
0.5
V
SOMI, KBINT,DATA,
CLOCK, STANDBY
All SEGs on,
16-digit display,
maximum brightness,
no load,
IDD1
—
10
mA
VDD–VSS
fosc=4 MHz
IDD2
IDD3
All SEGs off
—
—
10
25
mA
Power
Supply
Low power mode
mA
All SEGs on,
16-digit display,
maximum brightness,
no load,
IDISP1
—
—
15
1
mA
VDISP–VSS
fosc=4 MHz
IDISP2 All SEGs off
mA
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FEDL7170-03
MSC7170-01
¡ Semiconductor
AC Characteristics (1/2)
(Ta=–40 to 85°C, VDD=4.5 to 5.5V, VDISP=7 to 60 V, fOSC=4 MHz, 12-digit display)
Parameter
ENABLE Setup Time
ENABLE Hold Time
SCLK Frequency
Symbol
tES
Condition
Min. Typ. Max. Unit
See Fig. 1 (Data Transfer Timing)
See Fig. 1 (Data Transfer Timing)
See Fig. 1 (Data Transfer Timing)
See Fig. 1 (Data Transfer Timing)
See Fig. 1 (Data Transfer Timing)
See Fig. 1 (Data Transfer Timing)
See Fig. 1 (Data Transfer Timing)
Enable to SOMI valid
50
4
—
—
0.5
—
—
—
—
—
—
—
—
—
2
ns
ms
tEH
tCP
—
250
—
50
120
—
—
—
MHz
ns
SCLK Pulse Width
SCLK Rise/Fall Time
SIMO Setup Time
tcw
—
tcr/tcf
tDS
500 ns
—
—
ns
ns
SIMO Hold Time
tDH
SOMI Output Enable
SOMI Output Disable
SCLK to SOMI Delay
tOE
200 ns
200 ns
100 ns
tOD
Enable to SOMI tri-state
tPD
See Fig. 1 (Data Transfer Timing)
MSB to LSB
See Fig. 2 (Example of Data Transfer)
Byte Length
Byte Delay
tBYTE
tDELAY
tSYNC
3.5
—
—
—
—
ms
MSB to LSB
See Fig. 2 (Example of Data Transfer)
—
20 ms
*1
0.4
Duty cycle=50%, fOSC–4 MHz
12-digit display
SYNC Frequency
250 kHz
fOSC=4 MHz
See Fig. 5 (Duty Cycle Timing)
CI=20pF
SEGn Pulse Width
Operating Frequency
DUTY Period
tSEG
tOSC
tGRID
—
1.5
—
10
4
—
ms
Self-oscillation
4.5 MHz
fOSC=4 MHz,
See Fig. 3 (12-digit Display Cycle
Timing)
256
—
—
ms
ms
fOSC=4 MHz
See Fig. 3 (12-digit Display Cycle
Timing)
Blank Interval (min.)
tBLANK
—
12
tBLANK=48/fOSC
fOSC=4 MHz
See Fig. 5 (Duty Cycle Timing)
DATA Pulse Width High
DATA Period
tDW
—
—
256
—
—
ms
ms
fOSC=4 MHz
See Fig. 3 (12-digit Display Cycle
Timing)
tDATA
3072
fOSC=4 MHz
See Fig. 5 (Duty Cycle Timing)
DATA to CLOCK Delay
CLOCK Pulse Width
CLOCK Cycle
tDC
tPW
tCLOCK
tSCAN
—
—
—
—
5
—
—
—
—
ms
ms
ms
ms
fOSC=4 MHz
See Fig. 5 (Duty Cycle Timing)
250
256
40
fOSC=4 MHz
See Fig. 5 (Duty Cycle Timing)
fOSC=4 MHz
See Fig. 6 (Keyscan Timing)
Keyscan Cycle Time
8/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
AC Characteristics (2/2)
(Ta=–40 to 85°C, VDD=4.5 to 5.5 V, VDISP=7 to 60 V, fOSC=4 MHz, 12-digit display)
Parameter
Symbol
Condition
Min. Typ. Max. Unit
fOSC=4 MHz,
See Fig. 6 (Keyscan Timing)
Keyscan Pulse Width
tSPW
—
8
—
ms
Keypress to
Ceramic resonator
Crystal
CL=20 pF, VDISP=60 V,
—
—
—
—
5
KBINT at "L" level
OSC=4 MHz
ms
Wake-up Time
tWAKE
10
f
tr
tf
0.5 1.3
5
5
5
5
ms
ms
ms
ms
Slew Rate (SEGn-1 to SEGn-35)
Slew Rate (SEGn-36)
V
OL=6 V, VOH=50 V
1
3.4
—
—
tr
0.2
0.1
5
CL=20 pF, VDISP=60 V,
V
OL=6 V, VOH=50 V
tf
Slew Rate (DUTY, DATA, CLOCK)
Input Capacitance
tr/tf
CI
VOL=0.1 VDD, VOH=0.9 VDD, CL=10 pF
all pins
20 200 ns
pF
—
6
—
*1) For the minimum value when digits other than 12 digits are displayed, refer to the following
expression.
f
OSC
t
>
SYNC (Min)
1024 ¥ (digit display number)
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FEDL7170-03
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¡ Semiconductor
TIMING DIAGRAM
3.8V
0.8V
ENABLE
tES
3.8V
0.8V
SIMO
tDS
tDH
tcw
tEH
tcr
tcw
tcf
3.8V
0.8V
SCLK
tCP
tPD
tOE
tOD
3.8V
0.8V
SOMI
Figure 1. Data Transfer Timing
ENABLE
s7 s6 s5 s4 s3 s2 s1 s0
tBYTE
c7 c6 c5 c4 c3 c2 c1 c0
d7 d6 d5 d4 d3 d2 d1 d0
SOMI
SCLK
SIMO
tDELAY
c7 c6 c5 c4 c3 c2 c1 c0
Figure 2. Data Transfer Example
DUTY
DATA
CLOCK
tGRID
tDATA
tBLANK
Figure 3. 12-Digit (n=12) Display Cycle Timing
10/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
tGRID
DUTY
DATA
tBLANK
CLOCK
GRID1
Figure 4. GRID1 Interval Timing
(fosc
)
DATA
tDC
tPW
CLOCK
tBLANK
DUTY
tDGL
tDGH
GRID12
GRIDn
GRID1
tSEG
SEGn-1 to n-35
SEGn-36
Note:
(f
) is internal to the MSC7170 and not visible externally.
OSC
GRIDn are outputs of, and t
and t
are timig parameters of, the MSC7171 (grid
DGH
DGL
driver).
Figure 5. Duty Cycle Timing
11/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
ROW1
ROW2
ROW3
ROW4
ROW5
KBINT
tSCAN
tSPW
Figure 6. Keyscan Timing
Key Depressed
Key Depressed
KBINT
SCAN
Active
Active
ENABLE
Key Command
Key Command
Figure 7-1. Single Keypress/Single Read
Key Depressed
KBINT
SCAN
Active
ENABLE
Null Command
Key Command
Figure 7-2. Single Keypress/Multiple Read
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¡ Semiconductor
Key 1 Depressed Key 2 Depressed
KBINT
SCAN
Active
ENABLE
Key Command
Key Command
Figure 7-3. Multiple Keypress/Multiple Interrupt
Figure 7. Typical Cases of Keyscan Operation
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¡ Semiconductor
FUNCTIONAL DESCRIPTION
The MSC7170-01 (Dot Matrix VF Segment Driver) in conjunction with the MSC7171 (Dot Matrix
VF Grid Driver) is capable of controlling a variety of dot matrix VF displays and keyboards. The
MSC7170-01 is designed to drive the anodes of up to 32 dot matrix digits in two lines. Each digit
is a 5 ¥ 7 matrix of anodes, or dots, which requires a total of 70 segment driver outputs. There are
twoextrasegmentoutputsforsupplyingdrivetodedicatedannunciators. Thegriddriversofthe
MSC7171 are controlled by the MSC7170-01 through a two-line serial interface and a duty cycle
control line, DUTY (see APPLICATION CIRCUIT). Additionally, the MSC7170-01 provides 10-
bit digital dimming of all display data, a 5¥6 keyscan function allowing control of up to 30 key
pads and a low-power standby mode. The MSC7170-01 is controlled through a standard SPI
interface.
All MSC7170-01 internal timings are generated through an external 4 MHz (typ) ceramic
oscillator. One display cycle is defined as up to 16384 periods of the 4 MHz (250 ns) reference in
increments of 1024 periods, one for each pair of digits displayed. Display intensity is determined
by the duty cycle of the DUTY output within one display increment divided by the total number
of increments, or character pairs, displayed (see Display Duty Cycle Set and Number of Display
Digit Pairs Set commands below). The maximum duty cycle is defined as 976 out of 1024
increments or 95.3 percent.
The MSC7170-01 is capable of synchronizing the DUTY signal with an AC filament to avoid
visible flicker during dimming conditions. This is required in VF tubes of greater than 100 mm,
equivalent to 14 digits, in length. Synchronization is accomplished by alternately initiating
display cycles coincident with rising and falling edges of the filament voltage. Upon completion
of a rising/falling edge display cycle, the MSC7170-01 will wait for a falling/rising edge before
initiating the next display cycle. The MSC7170-01 detects rising and falling edges of a CMOS-
compatible SYNC input derived directly from the filament voltage. The amount of hold time
between display cycles varies between no delay as a minimum and the period of the filament
voltage as maximum. The amount of delay should be consistent for all display cycles assuming
that the filament frequency is well defined.
The MSC7170-01 is controlled through a Serial Peripheral Interface (SPI) compatible communi-
cations port. The SPI is a high-speed synchronous serial I/O port that shifts a serial bit stream of
eight data bits into or out of a device at a bit transfer rate programmed in a controlling device.
The figure below shows a typical connection of the SPI for communications between a master
(radio microprocessor) and slave (MSC7170-01). Three I/O pins are associated with the SPI
interface — SPI slave-in master-out (SIMO), SPI slave-out master-in (SOMI), and SPI serial clock
(SCLK). Additionally, a separate input pin is used to enable the MSC7170-01 to communicate
with the microprocessor through this interface.
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FEDL7170-03
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¡ Semiconductor
MASTER
SLAVE
SIMO
SOMI
Slave In/Master Out
SIMO
SOMI
Serial Input Buffer
Serial Input Buffer
Enable
Slave Out/Master In
Shift Register
MSB
Shift Register
MSC7170-01
LSB
SCLK
MSB
SCLK
LSB
Serial Clock
Microprocessor
SPI Master/Slave Connection
Themicroprocessorprovidestheserialclock(500kHztyp.)toalldevicesontheSPInetworkwith
a CLOCK POLARITY of 1 (inactive level is high). Data is transferred from the master
(microprocessor) to the salve (MSC7170-01) over the SIMO line, while data is transferred from
the slave to the master over the SOMI line. Data is clocked out of the transmitting device on the
fallingedgeofSCLKandlatchedintothereceivingdevicewiththerisingedgeofSCLK.ALLdata
transmissions are made MSB (b7) first.
A typical data transfer cycle between the microprocessor and the MSC7170-01 is initiated by first
bringing the ENABLE line low. The first byte transmitted defines the command or operation to
be executed. All remaining bytes received, prior to ENABLE being returned high, are treated as
data bytes for that operation. Each command or operation executed requires a separateENABLE
transfer cycle.
The maximum waiting period between byte transfers, measured from MSB to LSB, is 20 msec.
All activity on the SCLK and SIMO pins while ENABLE is high is ignored. Additionally, the
SOMI pin shall be in a tri-state condition when ENABLE is high so that other SPI devices on the
network may drive the line without contention.
The MSC7170-01 controls up to 30 key pads via a 5 controls up to 30 key pads via a 5¥6 key scan
circuit. COL1 to 6 (inputs) and ROW1 to 5 (outputs) are connected to an external switch matrix
with an impedance of 500W max. The ROW1 to 5 outputs start scanning only when a depression
or release of any key is detected. Upon completion of the first keyscan cycle, see Figure 6, the
keyboardinterrupt,KBINT,outputispulledlowtoindicateavailabilityofnewkeyscandata.The
keyscan circuit continues to scan and KBINT remains low until the keyscan data has been read
using the Keyscan Data Output Command. In the event of a multiple key depression, a second
interrupt will be generated following the clearing of the first interrupt. A stuck key switch will
notgeneratemultipleinterruptssinceonlystatetransitionsaredetectedbythekeyscancircuitry.
Keyscan data may be read without stopping the keyscan by using the Null Command. The
keyscan data is transmitted to the microprocessor by rows as shown in the Output Data Bytes
section. The output of keyscan data wraps around to the first byte for SPI transactions of more
than six bytes. After completion of the last keyscan cycle all ROW outputs go to low level.
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FEDL7170-03
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¡ Semiconductor
Key switch data is latched internally for transfer to the microprocessor via the SPI port. The
microprocessor may use KBINT as an interrupt request or for polling the MSC7170-01 to
determine when new keyscan information is available. As an alternative for polling, the
MSC7170-01 continuously outputs a status byte during any SPI transaction, with the exceptions
of the Null Command and the Keyscan Data Output Command. An all zeros (00h) byte indicates
the presence of new keyscan information while all ones (FFh) indicate no new keyscan
information. For the Null and Keyscan Data Output commands, the first byte output is still the
status byte followed by five bytes containing the data from the five keyscan rows as described
aboveandintheOutputDataBytessection.ThestatusbyteisresetuponcompletionofaKeyscan
Data Output command in the same fashion as KBINT.
The MSC7170-01 can also be commanded into a low power or "standby" mode (see Mode Set
command). In this mode all operation, including the internal oscillator, of the MSC7170-01
ceases. The only exception is the key scan detection circuitry which, on any key pad activity
(depress or release), will cause the MSC7170-01 to return to normal operation. The MSC7170-
01 will be fully operational within 10 msec (max) after return to normal operation. The wake-up
cycle includes a full scan of the key matrix. KBINT will be pulled low to indicate full wake-up.
Normal operation is also resumed when the ENABLE line is taken low. In this case, a scan of the
key matrix is not executed, nor is the KBINT line pulled low to indicate full wake-up.
TheRESETandENABLElinesshallbemaintainedatlogichighlevelsduringstandbyoperation.
All segment outputs go to a high impedance state while in standby mode. The SPI interface lines
(SLCK, SIMO, and SOMI) will not interfere with the operation of the SPI network when the
standby mode is properly selected. To ensure correct operation of the SPI network, the standby
mode of the MSC7170-01 should always be selected before the logic supply is switched off.
The following sequence of events should be followed to enter standby mode:
1)
2)
3)
Set duty cycle to zero percent
Turn off high voltage (V
Send low power (standby) "on" command
)
DISP
Following wake-up, the high voltage should be turned on prior to setting a duty cycle greater
than zero percent.
The MSC7170-01 may be commanded into Blank and Lamp Test modes. For Blank mode,
the DUTY and SEGn-1 to SEGn-35 outputs remain at a continuous low level while the SEGn36
outputs assume a high level. The outputs remain at this level until the command is deselected.
For Lamp Test mode, the DUTY output assumes a maximum duty cycle condition and the SEGn
outputs are all forced to the on condition regardless of input data.
The MSC7170-01 accepts a reset signal from the microprocessor or other controller. There shall
be no internal pull-up resistor on this signal. The state of the MSC7170-01 following a reset is as
follows:
a)
b)
c)
d)
e)
f)
All segment driver outputs are low
The number of display digits is 16 ¥ 2.
The display duty cycle is set to 0
Display Data Buffers are not cleared
SPI registers are reset
Keyscan registers are reset
16/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
The MSC7170-01 is protected against thermal overload or other failure caused by extreme
display configurations (e.g. Lamp Test) or due to output short circuits to high voltage supply,
ground, or another output. These shall be no performance degradation once the short circuit is
removed.
17/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
Commands Description
No.
Instruction
Address Setup
Byte
c7
1
c6
0
c5
0
c4
0
c3
X
c2
X
c1
X
c0
X
1
2
1
2
1
2
1
1
1
2
3
4
5
1
1
0
X
X
X
a4
1
a3
X
a2
X
a1
X
a0
X
1
0
0
1
2
Character Code Setup
b7
1
b6
0
b5
1
b4
0
b3
X
b2
X
b1
b0
DC9 DC8
Display Duty Cycle Setup
DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
3
4
Display Digits Setup
Mode Setup
1
1
1
0
1
1
1
0
0
1
0
1
n3
X
n2
m2
X
n1
m1
X
n0
m0
X
X
C1-7 C1-6 C1-5 C1-4 C1-3 C1-2 C1-1 C1-0
C1-15 C1-14 C1-13 C1-12 C1-11 C1-10 C1-9 C1-8
C2-7 C2-6 C2-5 C2-4 C2-3 C2-2 C2-1 C2-0
C2-15 C2-14 C2-13 C2-12 C2-11 C2-10 C2-9 C2-8
5
Cursor Setup
6
7
Keyscan Data Output
Null
1
0
1
0
1
0
0
0
X
0
X
0
X
0
X
0
Address Setup Command
This command is used to setup a start position of display character code writing and must be
executed before the desired character code is sent. In applications using less than the full 16-digit
pair capability, only the first 2n memory locations are used. For example, if n = 12-digit pair is
selected, only addresses 0 through 23 are used. Row 1 display data (SEG1 outputs) is stored in
addresses 0 through 11 while Row 2 display data (SEG2 outputs) is stored in addresses 12
through 23. All bytes following Bytes 1 and 2 are treated as character code data bytes. Address
0 is set after reset.
c7
c6
c5
c4
c3
c2
c1
c0
Byte 1
Byte 2
1
0
0
0
X
X
X
X
d7
d6
d5
d4
d3
d2
d1
d0
X
X
X
a4
a3
a2
a1
a0
a4 to a0 : 00000=00h=0
: 11111=1Fh=31
18/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
Character Code Setup Command
This command is used to specify the character to be displayed in the display location previously
specified by the Address Setup command. A built-in automatic address increment function
simplifies writing more than one display character code. All bytes transmitted after Byte 2 are
treated as character code data for successive locations. The internal address counter will be
automatically incremented from the address set using the Address Set command through
address 31 (or character 32), while executing valid write cycles, regardless of the number of digit
pairsasdefinedusingtheNumberofDisplayDigitsSetupcommand.Intheeventthatadditional
data is input to the MSC7170-01 following a valid write to address 31, the address counter will
wrap-around and continue to increment (to address 0 etc.) with write cycles disabled. This
prevents overwriting of the memory.
c7
c6
c5
c4
c3
c2
c1
c0
Byte 1
Byte 2
1
0
0
1
X
X
X
X
d7
d6
d5
d4
d3
d2
d1
d0
b7
b6
b5
b4
b3
b2
b1
b0
b4 to b0 : 8-bit character code — Select one of 256 codes
Display Duty Cycle Setup Command
This command is used to set the duty cycle of the display. The time allocated to a 1-digit display
is1024T, whereTistheperiodoftheinternaloscillator(f ). Thedisplaytimeforeachdigitmay
OSC
be specified as 0 to 976T in increment of T. Entries greater than 976 default to 976. The display
duty cycle is calculated by dividing the input duty cycle value, DC, by 1024 times the number of
digits, n, commanded to display. Note that the percent duty cycle depends on how many digits
(characters) are displayed.
c7
c6
c5
c4
c3
c2
c1
c0
Byte 1
Byte 2
1
0
1
0
X
X
DC9 DC8
d7
d6
d5
d4
d3
d2
d1
d0
DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
19/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
Number of Display Digits Setup Command
Thiscommandisusedtosetthenumberofdigitstobedisplayed. Thenumberofdigitsselectable
ranges from 1 to 16.
c7
c6
c5
c4
c3
c2
c1
c0
Byte 1
1
0
1
1
n3
n2
n1
n0
n3 to n0 : 0000=0h=16-digit pair
: 0001=1h=1-digit pair
:
: 1111=Fh=15-digit pair
Mode Setup Command
This command is used to select an operation mode for the MSC7170-01. Lamp Test and Blank
modes turns all 36 segments of each displayable digit (as set by the Number of Display Digits
Setup command) to the ON and OFF states respectively. The contents of the display buffer are
not affected by either of these modes. The normal operation mode returns after reset. Low Power
mode is described earlier.
c7
c6
c5
c4
c3
c2
c1
c0
Byte 1
1
1
0
0
X
m2
m1
m0
m2
0
m1
0
m0
0
Mode
Normal operation
0
0
1
Lamp test (All display ON)
Low power
0
1
0
0
1
1
Normal operation
Blank (All display OFF)
Normal operation
Normal operation
Normal operation
1
0
0
1
0
1
1
1
0
1
1
1
20/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
Cursor Setup Command
This command is used to specify the on/off state of cursor segments (SEGn-36) in the display.
The cursor outputs are issued inversely to allow an external PNP transistor to be used in
applications requiring high current drive capability. Therefore, a logic high, l, in a given bit
position will turn on the associated cursor. In applications requiring low current (less than 15
mA) drive capability, the cursor outputs may drive the VF display tube directly. In these
applications, setting to "0" turns on the cursor.
c7
c6
c5
c4
c3
c2
c1
c0
Byte 1
1
1
0
1
X
X
X
X
d7
d6
d5
d4
d3
d2
d1
d0
Byte 2
Byte 3
Byte 4
Byte 5
C1-7 C1-6 C1-5 C1-4 C1-3 C1-2 C1-1 C1-0
C1-15 C1-14 C1-13 C1-12 C1-11 C1-10 C1-9 C1-8
C2-7 C2-6 C2-5 C2-4 C2-3 C2-2 C2-1 C2-0
C2-15 C2-14 C2-13 C2-12 C2-11 C2-10 C2-9 C2-8
Keyscan Data Output Command
ThiscommandisusedtoreadkeyscandataviatheSPIinterfaceandhasnoeffectontheoperation
or state of the display portion of the MSC7170-01. Upon completion of this command the KBINT
output is reset to its non-active state and the keyscan function is stopped. All bytes after Byte 1
are ignored.
c7
c6
c5
c4
c3
c2
c1
c0
Byte 1
1
1
1
0
X
X
X
X
NULL Command
This command has the same function as the Keyscan Data Output command with the exception
that KBINT is not reset and the keyscan function continues to scan the key matrix. The keyscan
may stop momentarily to prevent changing data while data output is in progress. All bytes after
Byte 1 are ignored.
c7
c6
c5
c4
c3
c2
c1
c0
Byte 1
0
0
0
0
0
0
0
0
21/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
Output Data Byte Description
• Status output
The following byte is output from the MSC7170-01 during execution of every SPI command with
theexceptionsoftheKeyscanDataOutputandNullcommands.Thestatusbyteisissuedforeach
byte of the input command sequence.
d7
d6
d5
d4
d3
d2
d1
d0
Byte 1
s7
s6
s5
s4
s3
s2
s1
s0
Status
s7 to s0: indicates change status from last SPI transaction
00h = change, FFh = no change
• Keyscan data output
The following bytes are output from the MSC7170-01 during execution of the Keyscan Data
Output and Null commands. The output of keyscan data wraps around to byte 1 for transactions
of more than six bytes.
d7
X
d6
X
d5
s16
s26
s36
s46
s56
d4
s15
s25
s35
s45
s55
d3
s14
s24
s34
s44
s54
d2
s13
s23
s33
s43
s53
d1
s12
s22
s32
s42
s52
d0
s11
s21
s31
s41
s51
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Row 1
Row 2
Row 3
Row 4
Row 5
X
X
X
X
X
X
X
X
sij
: i=ROW1 to 5, j =Col1 to 6
sij=1: Switch on
sij=0: Switch off
22/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
Character Codes and Character Patterns
MSB: D7 - D4
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Note:
These character patterns are user programmable and can be selected by mask option.
23/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
Correspondence between Segment Outputs and VF Display Tube Dots
VF Dot:
IC Pin:
1-1
2-1
3-1
4-1
5-1
SEGn-1
SEGn-2
SEGn-3
SEGn-4
SEGn-5
VF Dot:
IC Pin:
1-2
2-2
3-2
4-2
5-2
SEGn-6
SEGn-7
SEGn-8
SEGn-9
SEGn-10
VF Dot:
IC Pin:
1-3
2-3
3-3
4-3
5-3
SEGn-11
SEGn-12
SEGn-13
SEGn-14
SEGn-15
VF Dot:
IC Pin:
1-4
2-4
3-4
4-4
5-4
SEGn-16
SEGn-17
SEGn-18
SEGn-19
SEGn-20
VF Dot:
IC Pin:
1-5
2-5
3-5
4-5
5-5
SEGn-21
SEGn-22
SEGn-23
SEGn-24
SEGn-25
VF Dot:
IC Pin:
1-6
2-6
3-6
4-6
5-6
SEGn-26
SEGn-27
SEGn-28
SEGn-29
SEGn-30
VF Dot:
IC Pin:
1-7
2-7
3-7
4-7
5-7
SEGn-31
SEGn-32
SEGn-33
SEGn-34
SEGn-35
24/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
APPLICATION CIRCUIT
KEYBOARD MATRIX
S11 S12 S13 S14 S15 S16
DISPLAY VOLTAGE AND
AC FILAMENT SUPPLY
VGRID FIL1
S21 S22 S23 S24 S25 S26
S31 S32 S33 S34 S35 S36
S41 S42 S43 S44 S45 S46
S51 S52 S53 S54 S55 S56
VDISP
FIL2
P
1
2
3
4
5
1
2
3
4
5
6
ROW
COL
5V
VDD
VDISP
SYNC
SEG1-36
SEG2-36
NC
SIMO
SOMI
SCLK
ENABLE
RESET
KBINT
MSC7170-01
1
2
FILAMENT
OSCl
OSCO
35
35
SEG1-1 to SEG1-35
SEG2-1 to SEG2-35
DOT
MATRIX
VF
VSS2 STANDBY DATA CLOCK DUTY
VSS1
RESONATOR
S
P
DISPLAY
TUBE
STANDBY DATA CLOCK DUTY
12
GRID1-12
VDISP
MSC7171
VDD
VSS
S
P
P
25/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
PACKAGE DIMENSIONS
QFP100-P-1420-0.65-BK
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.29 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
26/27
FEDL7170-03
MSC7170-01
¡ Semiconductor
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
27/27
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