MSM14Q0230 [OKI]
0.35 レm Sea of Gates Arrays; 0.35微米海门阵列
| 型号： | MSM14Q0230 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 0.35 レm Sea of Gates Arrays |
| 文件： | 总20页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MSM13Q/14Q000
0.35 µm Sea of Gates Arrays
November 1999
■ ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Oki Semiconductor
MSM13Q0000/14Q0000
0.35 µm Sea of Gates Arrays
DESCRIPTION
Oki’s 0.3 5 µm ASIC products deliver ultra-high performance and high density at low power dissipation.
The MSM13Q0000/14Q0000 series devices (referred to as “MSM13Q/14Q”) are implemented with the
industry-standard Cell-Based Array (CBA) architecture in a Sea-of-Gates (SOG) structure. Built in a
0.35 µm drawn CMOS technology (with an L-Effective of 0.27 µm), these SOG devices are available in
three layers (MSM13Q) and four layers (MSM14Q) of metal. The semiconductor process is adapted from
Oki’s production-proven 64-Mbit DRAM manufacturing process.
The MSM13Q/14Q Series contains 6 arrays each, offering over 1 million raw gates and 352 I/O pads. Up
to 66% and 90% of the raw gates can be used for the 3-layer and 4-layer arrays, respectively. Oki’s 0.35
µm family is optimized for 3-V core operation with optimized 3-V I/O buffers and 5-V tolerant 3-V buff-
ers. These SOG products are designed to fit the most popular plastic quad flat packs (QFPs), thin QFPs
(TQFPs) , and plastic ball grid array (PBGA) packages.
The MSM13Q/14Q Series uses the popular CBA architecture from Silicon Architects of Synopsys which
mixes two types of cells (8-transistor compute cells and 4-transistor drive cells) on the same die to deliver
high gate density and high drives. The CBA is supported by a rich macro library, optimized for synthesis.
Memory blocks are efficiently created by Oki’s memory compilers to generate single- and dual-port
RAM’s in high-density and low-power configurations with synchronous RAM options.
As such, the MSM13Q/14Q series is well suited to memory-intensive designs with high production vol-
umes approaching the real estate and cost savings of standard cells. At the same time, its SOG architec-
ture allows rapid prototyping turnaround times. Thus, Oki’s MSM13Q/14Q family offers the best of two
worlds: quick prototyping of a gate array and low production cost of a standard cell.
Oki’s 0.35 µm ASIC products are supported by leading-edge CAD tools including a synthesis-linked
floorplanner, motive static timing analyzer, and H-clock tree methodology. They are further supported
by specialized macrocells including phase-locked loop (PLL), pseudo-emitter coupled logic (PECL),
peripheral component interconnect (PCI), universal synchronous receiver/transmitter (UART) cells, and
ARM7TDMI RISC cores.
FEATURES
• 0.35 µm drawn 3- and 4-layer metal CMOS
• Optimized 3.3-V core
• Optimized 3-V I/O and 3-V I/O that is 5-V
tolerant
• User-configurable single and dual-port;
synchronous or asynchronous memories
• Specialized macrocells including PLL, PECL,
PCI, UART, and ARM7TDMI
• Floorplanning for front-end simulation, back-
end layout controls, and link to synthesis
• Joint Test Action Group (JTAG) boundary scan
and scan-path ATPG
• Support for popular CAE systems, including
Cadence, IKOS, Mentor Graphics, Synopsys,
Viewlogic, and Zycad
• CBA SOG architecture
• Over 1.0M raw gates and 352 pads
• User-configurable I/O with V , V , TTL, 3-
state, and 1- to 24-mA options
• Slew-rate-controlled outputs for low-radiated
noise
• H-clock tree cells which reduce the maximum
skew for clock signals
SS
DD
Oki Semiconductor
1
■ MSM13Q0000/14Q0000 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
MSM13Q/14Q FAMILY LISTING
Raw Gate
MSM13Q/14Q
Series
Raw Gate
(Gates)
Usable Gate
M13Q(3LM)
Usable Gate
M14Q(4LM)
PAD No.
144
Row
196
240
288
360
452
500
Column
802
0150
0230
0340
0530
0840
1020
157,192
242,400
346,176
536,400
847,048
1,033,000
105,319
152,712
204,244
289,656
415,054
475,180
143,045
208,464
276,941
391,572
567,522
650,790
176
1,010
1,202
1,490
1,874
2,066
208
256
320
352
ARRAY ARCHITECTURE
The primary components of a 0.35 µm MSM13Q/14Q circuit include:
• I/O base cells
• Configurable I/O pads for V , V , or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant)
DD
SS
• V and V pads dedicated to wafer probing
DD
SS
• Separate power bus for output buffers
• Separate power bus for internal core logic and input buffers
• Core base modules containing three compute cells for each drive cell
• Isolated gate structure for reduced input capacitance and increased routing flexibility
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with 4 pads
per corner. The arrays also have separate power rings for the internal core functions (V
and V
)
DDC
SSC
and output drive transistors (V
and V ).
DDO
SSO
The array architecture uses optimally sized transistors to efficiently implement logic and memory in a
metal programmable technology. CBA uses two types of cells: compute cells and drive cells. The com-
pute cell employs four PMOS and four NMOS trasnsistors whose sizes are optimized for logic and mem-
ory implementations as shown in Figure 1. The quantity and size of the transistors in a compute cell are
carefully selected to maximize the efficiency of most commonly used functions in VLSI design. The drive
cell consists of two large PMOS pull-up transistors and two large pull-down transistors. The compute
and drive cells are tiled to create a channelless core array, with three comput cells for each drive cell as
shown in Figure 2. The 3:1 ratio of compute to drive cells was selected for optimal implementation of
emerging applications. Macrocells are created using either compute cells, drive cells, or combinations of
compute and drive cells.
2
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MSM13Q0000/14Q0000 ■
Compute Cell
Compute Cell
Compute Cell
Drive Cell
Figure 1. Base Cell Consisting of Three Compute Cells and One Drive Cell
Compute Cell
Drive Cell
Figure 2. Core Array with Base Cell Mirrored Horizontally and Vertically
Oki Semiconductor
3
■ MSM13Q0000/14Q0000 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
ELECTRICAL CHARACTERISTICS
[1]
Absolute Maximum Ratings (V = 0 V, T = 25°C)
SS
j
Parameter
Power supply voltage
Symbol
VDD
VI
Conditions
Rated Value
-0.3 to +4.6
-0.3 to VDD+0.3
-0.3 to 6.0
-0.3 to VDD+0.3
-0.3 to 6.0
-10 to +10
-6 to +6
Unit
V
Input voltage
Normal buffers
5-V tolerant
V
V
VI
Output voltage
Normal buffers
5-V tolerant
VO
VO
II
Input current
Normal buffers
5-V tolerant
mA
II
Output current per I/O
Normal buffers
5-V tolerant
IO
IO = 1, 2, 4, 6, 8, 12, 24 mA
-24 to +24
-8 to +8
mA
°C
IO
IO = 2, 4, 6, 8, 12 mA
–
Storage temperature
Tstg
-65 to +150
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (V = 0 V)
SS
Parameter
Symbol
Rated Value
+3.0 to +3.6
-40 to +85
Unit
V
Power supply voltage
Junction temperature
VDD (3 V)
Tj
°C
4
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MSM13Q0000/14Q0000 ■
DC Characteristics (V = 3.0 to 3.6 V, V = 0 V, T = -40°C to +85°C)
DD
SS
j
[1]
Rated Value
[2]
Parameter
High-level input voltage
Symbol
Conditions
Min.
2.0
2.0
-0.3
-0.3
–
Typ
Max.
VDD + 0.3
5.5
0.8
0.8
2.0
–
Unit
Normal buffer
VIH
VIH
VIL
VIL
Vt+
Vt-
–
–
5-V tolerant
Normal buffer
5-V tolerant
Low-level input voltage
TTL input
TTL input
–
–
TTL- level Schmitt trigger input Normal buffer
threshold voltage
1.5
1.0
0.5
1.5
1.0
0.5
–
TTL input
Vt+ - Vt-
0.7
0.4
–
∆Vt
Vt+
Vt-
–
5-V tolerant
2.0
–
TTL 5-V tolerant input
0.7
0.4
VDD - 0.2
2.4
VDD - 0.2
2.4
–
V
∆Vt
VOH
Vt+ - Vt-
–
High-level output voltage
Low-level output voltage
High-level input current
Normal buffer
5-V tolerant
IOH = -100 µA
–
IOH = -1, -2, -4, -6, -8, -12, -24 mA
IOH = -100 µA
–
–
VOH
VOL
VOL
IIH
–
–
IOH = -1, -2, -4, -6, -8, -12 mA
IOL = 100 µA
–
–
Normal buffer
5-V tolerant
–
0.2
0.4
0.2
0.4
10
I
OL = 1, 2, 4, 6, 8, 12, 24mA
–
–
IOL = 100 µA
–
–
IOL = 1, 2, 4, 6, 8, 12 mA
VIH = VDD
–
–
Normal buffer
5-V tolerant
–
0.1
66
0.1
66
-0.1
-66
-1.1
-0.1
0.1
-66
-0.1
-66
-1.1
0.1
66
-0.1
VIH = VDD (50-kΩ pull-down)
VIH = VDD
10
200
10
IIH
–
µA
VIH = VDD (50-kΩ pull-down)
VIL = VSS
10
200
-
Low-level input current
3-state output leakage current
Normal buffer
IIL
-10
-200
-3.3
-10
–
VIL = VSS (50-kΩ pull-up)
VIL = VSS (3-kΩ pull-up)
VIL = VSS
-10
-0.3
–
mA
µA
5-V tolerant
IIL
Normal buffer
IOZH
VOH = VDD
10
VOH = VDD (50-kΩ pull-down)
VOL = VSS
10
200
–
µA
IOZL
-10
-200
-3.3
–
V
OL = VSS (50-kΩ pull-up)
OL = VSS (3-kΩ pull-up)
-10
-0.3
10
V
mA
µA
5-V tolerant
IOZH
VOH = VDD
OH = VDD (50-kΩ pull-down)
V
10
200
–
IOZL
VOL = VSS
-10
[3]
Stand-by current
IDDQ
Output open, VIH = VDD, VIL = VSS
Design Dependent
µA
1. JEDEC Compatible; JESD8-1A LVTTL.
2. Typical condition is VDD = 3.3 V and Tj = 25oC on a typical process.
3. RAM/ROM should be in powerdown mode.
Oki Semiconductor
5
■ MSM13Q0000/14Q0000 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
AC Characteristics (V = 3.3 V, V = 0 V, T = 25°C)
DD
SS
j
Driving
Type
[1] [2]
[3]
Parameter
Conditions
F/O = 2, L = 0 mm
= 3.3 V
Rated Value
0.082
0.068
0.062
0.14
Unit
Internal gate
propagation delay
Inverter
1X
2X
4X
1X
2X
1X
2X
1X
2X
4X
1X
2X
1X
2X
V
DD
2-input NAND
2-input NOR
Inverter
0.13
0.16
0.14
ns
F/O = 2, L = 1 mm
= 3.3 V
0.19
V
DD
0.13
0.097
0.28
2-input NAND
2-input NOR
0.20
0.34
0.24
Toggle frequency
F/O= 1, L = 0 mm
F/O = 2,L = 1 mm
1040
0.35
MHz
Input buffer
propagation delay
TTL level normal input buffer
TTL level 5-V tolerant buffer
0.64
Output buffer
propagation delay
Push-pull
Normal output
buffer
4 mA
8 mA
12 mA
4 mA
CL = 20pF
CL= 50 pF
CL = 100 pF
CL = 20 pF
2.15
2.25
2.82
3-state
5-V tolerant
buffer
2.41
ns
Output buffer
transition times
Push-pull
Normal output
buffer
12 mA
4 mA
CL = 100 pF
CL = 20 pF
4.68 (r)
3.48 (f)
[4]
3-state
5-V tolerant
buffer
3.53 (r)
3.24 (f)
1. Input transition time in 0.2 ns / 3.3 V.
2. Typical condition is VDD = 3.3 V and Tj = 25oC.
3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process.
4. Output rising and falling times are both specified over a 10 to 90% range.
6
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MSM13Q0000/14Q0000 ■
MACRO LIBRARY
Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard
macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following
figure illustrates the main classes of macrocells and macrofunctions available.
Examples
Flip-Flops
Combinational Logic
NANDs EXORs
Basic Macrocells
NORs
Latches
Basic Macrocells
with Scan test
Flip-Flops
Clock Tree Driver
Macrocells
Macrocells
Open Drain Outputs
Slew Rate Control Outputs
PCI Outputs
3-State Outputs
Push-Pull Outputs
PECL Outputs
3V, 5V Tolerant
Output Macrocells
Counters
Shift Registers
MSI Macrocells
Mega/Special
UART
PLL
USB Controller
Ethernet Controller
[1]
Macrocells
Macro Library
Inputs
Inputs with Pull-Downs
3-V, 5-V Tolerant
Input Macrocells
Inputs with Pull-Ups PECL Inputs
3-V, 5-V Tolerant
Bi-Directional
Macrocells
I/O
PCI I/O
I/O with Pull-Downs
I/O with Pull-Ups
Oscillator
Macrocells
Gated Oscillators
CBA RAMs:
Single-Port RAMs (asynchronous or synchronous)
Dual-Port RAMs (asynchronous)
Memory
Macrocells
MSI
Macrofunctions
4-Bit Register/Latches
Macrofunctions
[1] Under development
Figure 3. Oki Macrocell and Macrofunction Library
Oki Semiconductor
7
■ MSM13Q0000/14Q0000 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Macrocells for Driving Clock Trees
Oki offers H-clock-tree drivers that minimize clock skew. The advanced layout software uses dynamic
driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular cir-
cuit. Features of the H-clock-tree driver-macrocells include:
• True RC back annotation of the clock network
• Automatic fan-out balancing
• Dynamic sub-trunk allocation
• Single clock tree driver logic symbol
• Automatic branch length minimization
• Dynamic driver placement
• Allows multiple clock trees
Clock
Figure 4. H-Clock-Tree Structure
8
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MSM13Q0000/14Q0000 ■
OKI ADVANCED DESIGN CENTER CAD TOOLS
Oki’s advanced design center CAD tools include support for the following:
• Floorplanning for front-end simulation, back-end layout control, and link to synthesis
• Clock tree structures improve first-time silicon success by eliminating clock skew problems
• JTAG Boundary scan support
• Power calculation which predicts circuit power under simulation conditions to accurately model
package requirements (in development)
Table 1: CAD Design Tools
Vendor
Platform
Operating System [1]
Vendor Software/Revision [1]
Description
Cadence
HP9000, 7xx
IBM RS6000
Sun® [2]
HP-UX
AIX
SunOS, Solaris
Composer™
Verilog™
Design capture
Simulation
Timing analysis
Fault grading
Design synthesis
Design capture
VHDL simulation
Veritime™
Verifault™
Synergy™
Concept™ [3]
Leapfrog™
IKOS
HP9000, 7xx,
Sun [2]
HP-UX, SunOS, Solaris
NSIM
Gemini/Voyager
Simulation
Mentor Graphics™
HP9000, 7xx
Sun [2]
HP-UX
SunOS, Solaris
IDEA™
Design capture
VHDL simulation
Logic simulation
Timing analysis
Fault grading
Fault grading
Design synthesis
Test synthesis
QuickVHDL
QuickSim II™
QuickPath™
QuickFault™
QuickGrade™
AutoLogic™
DFT Advisor
Synopsys
(Interface to Mentor
Graphics, VIEWLogic)
IBM RS6000
HP9000, 7xx
Sun [2]
AIX
HP-UX
SunOS, Solaris
Design Compiler™
HDL/VHDL Compiler™
Test Compiler™
VSS™
Compilation
Design synthesis
Test synthesis
VHDL simulation
Model Technology, Inc.
(MTI)
HP9000, 7xx
Sun [2]
PC
HP-UX
SunOS, Solaris.
Win95/NT™
V-System
VHDL Simulation
VIEWLogic
PC
Sun
Windows™,
Windows NT™
SunOS, Solaris
Workview Office™
Powerview™
Vantage Optium
Motive
Design capture
Simulation
VHDL simulation
Timing analysis
Design synthesis
Simulation
[2]
ViewSim™ with VSO
1. Contact Oki Application Engineering for current software versions.
2. Sun or Sun-compatible.
3. Sun and HP platform only.
Oki Semiconductor
9
■ MSM13Q0000/14Q0000 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Design Process
The following figure illustrates the overall IC design process and shows the three main interface points
between external design houses and Oki ASIC Application Engineering.
[5]
Level 1
VHDL/HDL Description
Synthesis
Schematics
Test Vectors
CAE Front-End
[2]
LSF
[1]
CDC
Floorplanning
Floorplanning
Gate-Level Simulation
Level 2
Netlist Conversion
(EDIF 200)
Test Vector Conversion
[4]
(Oki TPL
)
Scan Insertion (Optional)
[3]
TDC
[1]
CDC
Pre-Layout Simulation
(Cadence Verilog)
Floorplanning
Layout
[5]
Level 2.5
[6]
Oki Interface
Fault Simulation
Automatic Test
Pattern Generation
( Zycad)
(Synopsys Test Compiler)
Verification
(Cadence DRACULA)
Post-Layout Simulation
(Cadence Verilog)
[5]
Level 3
Manufacturing
Prototype
Test Program
Conversion
[1] Oki’s Circuit Data Check (CDC) program verifies logic design rules.
[2] Oki’s Link to Synthesis Floorplanning (LSF) toolset transfers post-floorplanning timing for resynthesis.
[3] Oki’s Test Data Check (TDC) program verifies test vector rules.
[4] Oki’s Test Pattern Language (TPL).
[5] Alternate Customer-Oki design interfaces available in addition to standard level 2.
[6] Standard design process includes fault simulation.
Figure 5. Oki’s Design Process
10
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MSM13Q0000/14Q0000 ■
Automatic Test Pattern Generation
Oki’s 0.35 µm ASIC technologies support Automatic Test Pattern Generation (ATPG) using full scan-
path design techniques, including the following:
• Increases fault coverage ≥95%
• Uses Synopsys Test Compiler
• Inserts scan structures automatically
• Connects scan chains
• Traces and reports scan chains
• Checks for rule violations
• Generates complete fault reports
• Allows multiple scan chains
• Supports vector compaction
ATPG methodology is described in detail in Oki’s 0.35 µm Scan Path Application Note.
Combinational Logic
A
B
FD1AS
FD1AS
D
Q
D
Q
Scan Data Out
C
C
Scan Data In
Scan Select
SD
SS
SD
SS
QN
QN
Figure 6. Full Scan Path Configuration
Floorplanning Design Flow
Oki offers three floorplanning tools for high-density ASIC design. The two main purposes for Oki’s floor-
planning tool are to:
• Ensure conformance of critical circuit performance specifications
• Shorten overall design turnaround time (TAT)
The supported floorplanners are: Cadence DP3, Gambit GFP, and Oki’s internal floorplanner.
In a traditional design approach with synthesis tools, timing violations after prelayout simulation are
fixed by manual editing of the netlist. This process is difficult and time consuming. Also, there is no
physical cluster information provided in the synthesis tool, and so it is difficult to synthesize logic using
predicted interconnection delay due to wire length. Therefore, synthesis tools may create over-optimized
results.
To minimize these problems, Synopsys proposed a methodology called Links to Layout (LTL). Based on
this methodology, Oki developed an interface between Oki’s floorplanners and the Synopsys environ-
ment, called Link Synopsys to Floorplanner (LSF). Because not all Synopsys users have access to the Syn-
opsys Floorplan Management tool, Oki developed the LSF system to support both users who can access
Oki Semiconductor
11
■ MSM13Q0000/14Q0000 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Synopsys Floorplan Management and users who do not have access to Synopsys Floorplan Manage-
ment.
More information on OKI’s floorplanning capabilities is available in Oki’s Application Note, Using Oki’s
Floorplanner: Standalone Operation and Links to Synopsys.
Incremental
Optimization with
Physical Information
Initial Synthesis
HDL Entry
No
Constraints Met?
PDEF
Yes
(Synopsis)
Constraints
Synthesis
Invoke Import on
Floorplanner
Gate Level
Netlist
No
Constraints Met?
Yes
Gate Level
Netlist
(EDIF)
(EDIF)
Incremental
Floorplan
Initial Floorplan
Oki RC
PDEF (Synopsys)
Wire Load Model (Synopsys)
Net Capacitance (Synopsys
Script (Synopsys)
Invoke Export on
Floorplanner
Invoke Delay
Delay
(SDF)
Load
Back-Annotation Files
No
Constraints Met?
Yes
= In Synopsys DC/DA
= In Floorplanner
Timing Optimization
To Simulation and P&R
Figure 7. LSF System Design Flow
12
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MSM13Q0000/14Q0000 ■
IEEE JTAG Boundary Scan Support
Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from
incorporating boundary-scan logic into a design include:
• Improved chip-level and board-level testing and failure diagnostic capabilities
• Support for testing of components with limited probe access
• Easy-to-maintain testability and system self-test capability with on-board software
• Capability to fully isolate and test components on the scan path
• Built-in test logic that can be activated and monitored
• An optional Boundary Scan Identification (ID) Register
Oki’s boundary scan methodology meets the JTAG Boundary Scan standard, IEEE 1149.1-1990. Either the
customer or Oki can perform boundary-scan insertion. More information is available in Oki’s JTAG
Boundary Scan Application Note. (Contact the Oki Application Engineering Department for interface
options.)
Oki Semiconductor
13
■ MSM13Q0000/14Q0000 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
PACKAGE OPTIONS
TQFP & LQFP Package Menu
TQFP
80
●
LQFP
176
Base Array
MSM...
[1]
I/O Pads
144
64
●
●
●
100
●
144
●
208
13Q/14Q0150
●
●
●
●
●
13Q/14Q0230
13Q/14Q0340
13Q/14Q0530
13Q/14Q0840
13Q/14Q1020
Body Size (mm)
Lead Pitch (mm)
176
●
●
●
●
●
208
●
●
●
❍
256
●
❍
●
●
320
❍
●
●
352
10 x 10
0.5
12 x 12
0.5
14 x 14
0.5
20 x 20
0.5
24 x 24
0.5
28 x 28
0.5
1. I/O Pads can be used for input, output, bi-directional, power, or ground.
● = Available now; ❍= In development
PQFP Package Menu
PQFP (42 Alloy)
PQFP (Cu-Alloy)
Base Array
MSM...
[1]
I/O Pads
144
128
❍
160
208
240
13Q/14Q0150
❍
❍
●
13Q/14Q0230
13Q/14Q0340
13Q/14Q0530
13Q/14Q0840
13Q/14Q1020
Body Size (mm)
Lead Pitch (mm)
176
●
208
●
●
●
●
256
●
●
❍
❍
320
❍
●
●
352
28 x 28
0.80
28 x 28
0.65
28 x 28
0.50
32 x 32
0.50
1. I/O Pads can be used for input, output, bi-directional, power, or ground.
● = Available now; ❍= In development
14
Oki Semiconductor
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MSM13Q0000/14Q0000 ■
BGA Package Menu
Base Array
MSM...
[1]
I/O Pads
144
256
352
13Q/14Q0150
13Q/14Q0230
13Q/14Q0340
13Q/14Q0530
13Q/14Q0840
13Q/14Q1020
Body Size (mm)
Ball Pitch (mm)
●
●
176
208
●
256
●
●
●
320
●
352
27 x 27
1.27
35 x 35
1.27
1. I/O Pads can be used for input, output, bi-directional, power, or ground.
● = Available now; ❍= In development
Oki Semiconductor
15
■ MSM13Q0000/14Q0000 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Notes:
16
Oki Semiconductor
The information contained herein can change without notice owing to product and/or technical improvements.
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The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action
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Copyright 1999 Oki Semiconductor
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