MSM511000CL-45JS [OKI]
1,048,576-Word x 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE; 1,048,576字×1位动态RAM ：快速页面模式类型
| 型号： | MSM511000CL-45JS |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 1,048,576-Word x 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| 文件： | 总15页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2G0009-17-41
This version: Jan. 1998
Previous version: May 1997
¡ Semiconductor
MSM511000C/CL
1,048,576-Word ¥ 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM511000C/CL is a 1,048,576-word ¥ 1-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM511000C/CL achieves high integration, high-speed operation, and
low-powerconsumptionbecauseOkimanufacturesthedeviceinaquadruple-layerpolysilicon/
single-layer metal CMOS process. The MSM511000C/CL is available in a 26/20-pin plastic SOJ or
20-pin plastic ZIP. The MSM511000CL (the low-power version) is specially designed for lower-
power applications.
FEATURES
• 1,048,576-word ¥ 1-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 512 cycles/8 ms, 512 cycles/64 ms (L-version)
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Package options:
26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM511000C/CL-xxJS)
20-pin 400 mil plastic ZIP
(ZIP20-P-400-1.27)
(Product : MSM511000C/CL-xxZS)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Cycle Time
(Min.)
Power Dissipation
Family
tRAC
45 ns
50 ns
60 ns
70 ns
tAA
tCAC
14 ns
14 ns
15 ns
20 ns
Standby (Max.)
Operating (Max.)
24 ns
26 ns
30 ns
35 ns
MSM511000C/CL-45
MSM511000C/CL-50
MSM511000C/CL-60
MSM511000C/CL-70
90 ns
100 ns
120 ns
130 ns
468 mW
440 mW
385 mW
330 mW
5.5 mW/
1.1 mW (L-version)
1/15
¡ Semiconductor
MSM511000C/CL
PIN CONFIGURATION (TOP VIEW)
DIN
1
26 VSS
25 DOUT
24 CAS
23 NC
22 A9
A9 1
2
4
6
8
CAS
VSS
WE
NC
WE 2
RAS 3
NC 4
DOUT
DIN
3
5
RAS 7
NC 9
A0 11
A2 13
VCC 15
A5 17
A7 19
NC 5
NO LEAD
12 A1
14 A3
16 A4
18 A6
20 A8
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
26/20-Pin Plastic SOJ
20-Pin Plastic ZIP
Pin Name
A0 - A9
RAS
Function
Address Input
Row Address Strobe
Column Address Strobe
Data Input
CAS
DIN
DOUT
WE
Data Output
Write Enable
VCC
Power Supply (5 V)
Ground (0 V)
VSS
NC
No Connection
2/15
¡ Semiconductor
MSM511000C/CL
BLOCK DIAGRAM
Timing
Generator
RAS
CAS
Timing
Generator
Write
Column
Address
Buffers
WE
Column
Decoders
Clock
10
10
Generator
Internal
Address
Counter
I/O
Selector
Refresh
Control Clock
Sense
Amplifiers
Output
DOUT
A0 - A9
Buffer
Row
Address
Buffers
Row
De-
10
10
Word
Drivers
Memory
Cells
Input
Buffer
DIN
coders
VCC
On Chip
Generator
V
BB
VSS
3/15
¡ Semiconductor
MSM511000C/CL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VT
Rating
–1.0 to 7.0
50
Unit
V
IOS
mA
W
PD
*
1
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Symbol
VCC
Min.
4.5
0
Typ.
5.0
0
Max.
Unit
5.5
0
V
V
V
V
VSS
Input High Voltage
Input Low Voltage
VIH
2.4
–1.0
—
6.5
0.8
VIL
—
Capacitance
(VCC = 5 V 10ꢀ, Ta = 25°C, f = 1 MHꢁ)
Parameter
Symbol
CIN1
Typ.
Max.
Unit
pF
Input Capacitance (A0 - A9, DIN)
—
—
—
5
5
6
Input Capacitance (RAS, CAS, WE)
CIN2
pF
Output Capacitance (DOUT
)
COUT
pF
4/15
¡ Semiconductor
MSM511000C/CL
DC Characteristics
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C)
MSM511000 MSM511000 MSM511000 MSM511000
C/CL-45 C/CL-50 C/CL-60 C/CL-70
Parameter
Symbol
Condition
Unit Note
Min. Max. Min. Max. Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
IOH = –5.0 mA
IOL = 4.2 mA
V
V
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC
0
0.4
0
0.4
0
0.4
0
0.4
0 V £ VI £ 6.5 V;
All other pins not
under test = 0 V
DOUT disable
Input Leakage Current
mA
ILI
–10 10 –10 10 –10 10 –10 10
Output Leakage Current
–10 10 –10 10 –10 10 –10 10 mA
ILO
0 V £ VO £ 5.5 V
Average Power
Supply Current
(Operating)
RAS, CAS cycling,
—
80
—
70
—
60
mA
1, 2
ICC1
—
85
tRC = Min.
RAS, CAS = VIH
RAS, CAS
—
—
—
2
1
—
—
—
2
1
—
—
—
2
1
—
—
—
2
1
Power Supply
mA
1
ICC2
ICC3
ICC5
ICC6
ICC7
ICC10
Current (Standby)
1, 5
≥ VCC –0.2 V
RAS cycling,
CAS = VIH,
mA
200
200
200
200
Average Power
Supply Current
—
—
—
—
—
85
5
—
—
—
—
—
80
5
—
—
—
—
—
70
5
—
—
—
—
—
60 mA 1, 2
(RAS-only Refresh)
tRC = Min.
RAS = VIH,
Power Supply
CAS = VIL,
5
mA
1
Current (Standby)
DOUT = enable
Average Power
Supply Current
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
Supply Current
(Battery Backup)
RAS cycling,
85
80
300
80
75
300
70
65
300
60 mA 1, 2
CAS before RAS
RAS = VIL,
CAS cycling,
55 mA 1, 3
t
PC = Min.
tRC = 125 ms,
CAS before RAS,
tRAS £ 1 ms
1, 4,
5
mA
300
Notes : 1. I Max. is specified as I for output open condition.
CC
CC
2. The address can be changed once or less while RAS = V .
IL
3. The address can be changed once or less while CAS = V
4. V – 0.2 V £ V £ 6.5 V, –1.0 V £ V £ 0.2 V.
.
IH
CC
IH
IL
5. L-version.
5/15
¡ Semiconductor
MSM511000C/CL
AC Characteristics (1/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3
MSM511000 MSM511000 MSM511000 MSM511000
C/CL-45 C/CL-50 C/CL-60 C/CL-70
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max. Min. Max.
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
tRC
90
—
—
—
100
120
36
—
—
—
120
140
40
—
—
—
130
155
45
—
—
—
ns
ns
ns
tRWC 110
tPC 34
tPRWC 54
—
56
—
60
—
70
—
ns
Access Time from RAS
tRAC
tCAC
tAA
—
—
—
—
0
45
14
24
28
—
14
50
8
—
—
—
—
0
50
14
26
30
—
14
50
8
—
—
—
—
0
60
15
30
35
—
15
50
8
—
—
—
—
0
70
20
35
40
—
20
50
8
ns 4, 5, 6
Access Time from CAS
ns
ns
ns
ns
ns
ns
ms
4, 5
4, 6
4
Access Time from Column Address
Access Time from CAS Precharge
Output Low Impedance Time from CAS
tCPA
tCLZ
4
CAS to Data Output Buffer Turn-off Delay Time tOFF
0
0
0
0
7
Transition Time
tT
3
3
3
3
3
Refresh Period
tREF
tREF
tRP
—
—
35
—
—
40
—
—
50
—
—
50
Refresh Period (L-version)
RAS Precharge Time
64
—
64
—
64
—
64 ms
ns
—
RAS Pulse Width
tRAS 45 10,000 50 10,000 60 10,000 70 10,000 ns
tRASP 45 100,000 50 100,000 60 100,000 70 100,000 ns
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
tRSH 14
tCP 10
—
—
14
10
—
—
15
10
—
—
20
10
—
—
ns
ns
CAS Precharge Time (Fast Page Mode)
CAS Pulse Width
tCAS 14 10,000 14 10,000 15 10,000 20 10,000 ns
CAS Hold Time
tCSH 45
tCRP
—
—
—
31
21
—
—
—
—
—
—
50
5
—
—
—
36
24
—
—
—
—
—
—
60
5
—
—
—
45
30
—
—
—
—
—
—
70
5
—
—
—
50
35
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
5
tRHCP 28
tRCD 17
tRAD 12
30
18
13
0
35
20
15
0
40
20
15
0
5
6
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
Column Address Hold Time from RAS
Column Address to RAS Lead Time
tASR
tRAH
tASC
0
7
0
8
10
0
10
0
0
tCAH 12
tAR 35
tRAL 24
13
40
26
15
50
30
15
55
35
6/15
¡ Semiconductor
MSM511000C/CL
AC Characteristics (2/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3
MSM511000 MSM511000 MSM511000 MSM511000
C/CL-45 C/CL-50 C/CL-60 C/CL-70
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max. Min. Max.
Read Command Set-up Time
Read Command Hold Time
tRCS
tRCH
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
9
Read Command Hold Time referenced to RAS tRRH
0
0
0
Write Command Set-up Time
Write Command Hold Time
Write Command Hold Time from RAS
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
tWCS
0
0
0
tWCH 10
tWCR 35
10
40
10
14
14
0
10
50
10
15
15
0
15
55
15
20
20
0
tWP
10
tRWL 14
tCWL 14
tDS
tDH
0
10
10
Data-in Hold Time
12
13
40
14
26
50
35
0
15
50
15
30
60
40
0
15
55
20
35
70
45
0
Data-in Hold Time from RAS
CAS to WE Delay Time
tDHR 35
tCWD 14
tAWD 24
tRWD 45
tCPWD 33
9
9
9
9
Column Address to WE Delay Time
RAS to WE Delay Time
CAS Precharge WE Delay Time
CAS Active Delay Time from RAS Precharge tRPC
0
RAS to CAS Set-up Time (CAS before RAS) tCSR 10
RAS to CAS Hold Time (CAS before RAS) tCHR 25
10
25
10
30
10
30
7/15
¡ Semiconductor
MSM511000C/CL
Notes: 1. A start-up delay of 100 µs is required after power-up, followed by a minimum of
eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before
proper device operation is achieved.
2. The AC characteristics assume t = 5 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.
IH
IL
Transition times (t ) are measured between V and V .
T
IH
IL
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t (Max.) limit ensures that t (Max.) can be met.
RCD
RAC
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
is greater than the specified
RCD
RCD
t
.
RCD
CAC
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RAD
RAC
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
is greater than the specified
RAD
RAD
t
.
RAD
AA
7. tOFF (Max.)definesthetimeatwhichtheoutputachievestheopencircuitconditionand
is not referenced to output voltage levels.
8. t
9. t
or t
must be satisfied for a read cycle.
RCH
RRH
, t
, t
, t
and t
are not restrictive operating parameters. They are
WCS CWD RWD AWD
CPWD
included in the data sheet as electrical characteristics only. If t
≥t
(Min.), then
WCS WCS
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t ≥ t (Min.) , t ≥ t (Min.),
CWD
CWD
RWD
RWD
t
≥ t
(Min.) and t
≥ t
(Min.), then the cycle is a read modify write
AWD
AWD
CPWD
CPWD
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in a read modify write cycle.
8/15
E2G0088-17-41A
¡ Semiconductor
MSM511000C/CL
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
tRAD
tRAL
tCAH
tASR
tRAH
Row
tASC
VIH
VIL
–
–
Address
Column
tAR
tRCH
tRRH
tRCS
VIH
VIL
–
–
WE
tCAC
tCLZ
tAA
tOFF
tRAC
VOH
VOL
–
–
DOUT
Open
Valid Data
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tRCD
tRSH
tCAS
tCRP
tCRP
tCSH
VIH
VIL
–
–
tAR
tRAD
tRAL
tCAH
tASR
tRAH
Row
tASC
VIH
VIL
–
–
Address
Column
tCWL
tWCR
tWCS
tWCH
VIH
VIL
–
–
tWP
tRWL
WE
tDHR
tDS
tDH
VIH
VIL
–
–
DIN
Valid Data
VOH
VOL
–
–
DOUT
Open
"H" or "L"
9/15
¡ Semiconductor
MSM511000C/CL
Read Modify Write Cycle
tRWC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tRSH
tCRP
tCRP
tRWL
tRCD
tCAS
VIH
VIL
–
–
tCSH
tRAL
tCAH
tAR
tCWL
tRAD
tRAH
tASR
tASC
VIH
VIL
–
–
Address
Row
Column
tAWD
tRWD
tWP
tCWD
VIH
VIL
–
–
WE
tRCS
tDS
tDH
Valid Data
VIH
VIL
–
–
DIN
tCAC
tAA
tOFF
tRAC
VOH
VOL
–
–
DOUT
Open
Valid Data
tCLZ
"H" or "L"
Fast Page Mode Read Cycle
tRASP
tRP
VIH –
tRHCP
RAS
VIL
–
tCSH
tRCD
tPC
tCAS
tRSH
tCAS
tCRP
tCP
tCAS
tCP
tCRP
VIH –
CAS
VIL
–
tAR
tASC
tRAL
tCAH
tASR
tASC
tCAH
tRAH
Row
tCAH
tASC
VIH
VIL
–
–
Address
Column
Column
Column
tRRH
tRCH
tRAD
tRCH
tRCH
tRCS
tRCS
tRCS
VIH –
WE
tCAC
tCAC
tCAC
VIL
–
tAA
tCPA
tAA
tCPA
tAA
tRAC
VOH –
Valid
Data
Valid
Data
Valid
Data
DOUT
VOL
–
tOFF
tCLZ
tOFF
tCLZ
tOFF
tCLZ
"H" or "L"
10/15
¡ Semiconductor
MSM511000C/CL
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
VIH
VIL
–
–
tRHCP
RAS
CAS
tRSH
tCAS
tPC
tCAS
tCRP
tCAS
tCP
tRCD
tCP
tCRP
VIH
VIL
–
–
tAR
t
tRAL
tCAH
tASR
tCAH
Column
tCAH
Column
tRAH
Row
tASC
tASC
ASC
VIH
VIL
–
–
Address
Column
tRWL
tCWL
tRAD
tWCR
tWCS
tCWL
tCWL
tWCH
tWCH
tWCS
tWCS
tWCH
VIH
VIL
–
–
tWP
tWP
tWP
WE
tDS
tDS
Valid Data
tDS
tDH
tDH
tDH
VIH
VIL
–
–
DIN
Valid Data
tDHR
Valid Data
VOH
VOL
–
–
DOUT
Open
"H" or "L"
Fast Page Mode Read Modify Write Cycle
tRASP
VIH
–
tRHCP
tRSH
tCAS
RAS
tRP
tCRP
VIL
–
tCSH
tPRWC
tCAS
tRCD
tCP
tCP
tCAS
VIH
VIL
–
–
CAS
tAR
tRAH
tASC
tRAL
tCAH
tCAH
tCAH
tASR
tASC
tASC
VIH
VIL
–
–
Address
Column
Column
Row
Column
tRWD
tCPWD
tCPWD
tCWL
tRCS
tRCS
tCWL
tRCS
tCWL
tCWD
tCWD
tCWD
VIH
VIL
–
–
tAWD
tAWD
tAWD
tAA
WE
tCPA
tCPA
tWP
tWP
tWP
tAA
tAA
tCAC
tRAD
tCAC
tCAC
tOFF
tOFF
tOFF
VOH
VOL
–
–
DOUT
Valid Data
tDH
Valid Data
tDH
Valid Data
tRAC
tCLZ
tRWL
tCLZ
tCLZ
tDH
tDS
tDS
tDS
VIH
VIL
–
–
Valid
Data
Valid
Data
Valid
Data
DIN
"H" or "L"
11/15
¡ Semiconductor
MSM511000C/CL
RAS-Only Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tCRP
tRPC
VIH
VIL
–
–
tRAH
tASR
VIH
VIL
–
–
Address
DOUT
Row
tOFF
VOH
VOL
–
–
Open
Note: WE = "H" or "L"
"H" or "L"
CAS before RAS Refresh Cycle
tRC
tRP
tRAS
VIH –
RAS
VIL
–
tRPC
tCP
tCSR
tCHR
VIH –
CAS
VIL
–
tOFF
VOH –
DOUT
Open
VOL
–
Note: WE, Address = "H" or "L"
12/15
¡ Semiconductor
MSM511000C/CL
Hidden Refresh Read Cycle
tRC
tRAS
tRAS
tRP
VIH
VIL
–
–
RAS
CAS
tCRP
tRSH
tRCD
tCHR
VIH
VIL
–
–
tRAD
tRAL
tCAH
tASR
tRAH
Row
tASC
VIH
VIL
–
–
Address
Column
tAR
tRCS
tRRH
VIH
VIL
–
–
WE
tCAC
tAA
tOFF
tRAC
VOH
VOL
–
–
DOUT
Valid Data
tCLZ
"H" or "L"
Hidden Refresh Write Cycle
tRC
tRP
tRAS
tRAS
VIH
VIL
–
–
RAS
CAS
tCRP
tRSH
tRCD
tCHR
VIH
VIL
–
–
tAR
tRAD
tRAL
tCAH
tASR
tRAH
Row
tASC
VIH
VIL
–
–
Address
Column
tWCR
tWCS
tRAD
tRWL
tWCH
VIH
VIL
tWP
–
–
WE
tDS
tDH
VIH
VIL
–
–
DIN
Valid Data
tDHR
VOH
VOL
–
–
DOUT
Open
"H" or "L"
13/15
¡ Semiconductor
MSM511000C/CL
PACKAGE DIMENSIONS
(Unit : mm)
SOJ26/20-P-300-1.27
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
14/15
¡ Semiconductor
MSM511000C/CL
(Unit : mm)
ZIP20-P-400-1.27
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
1.50 TYP.
15/15
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