MSM5116160D [OKI]
1,048,576-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE; 1,048,576字×16位动态RAM ：快速页面模式类型
| 型号： | MSM5116160D |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 1,048,576-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| 文件： | 总17页 (文件大小：523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2G0153-29-41
This version: Apr. 1999
Previous version: Oct. 1998
¡ Semiconductor
MSM5116160D/DSL
1,048,576-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM5116160D/DSL is a 1,048,576-word¥16-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM5116160D/DSL achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
double-layer metal CMOS process. The MSM5116160D/DSL is available in a 42-pin plastic SOJ or
50/44-pin plastic TSOP. The MSM5116160DSL (the self-refresh version) is specially designed for
lower-power applications.
FEATURES
• 1,048,576-word ¥ 16-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 4096 cycles/64 ms, 4096 cycles/128 ms (SL version)
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• CAS before RAS self-refresh capability (SL version)
• Package options:
42-pin 400 mil plastic SOJ
(SOJ42-P-400-1.27)
(Product : MSM5116160D/DSL-xxJS)
50/44-pin 400 mil plastic TSOP (TSOPII50/44-P-400-0.80-K)(Product:MSM5116160D/DSL-xxTS-K)
(TSOPII50/44-P-400-0.80-L) (Product:MSM5116160D/DSL-xxTS-L)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
tRAC tAA tCAC tOEA
50 ns 25 ns 13 ns 13 ns
60 ns 30 ns 15 ns 15 ns
70 ns 35 ns 20 ns 20 ns
Cycle Time
(Min.)
Power Dissipation
Family
Standby (Max.)
Operating (Max.)
MSM5116160D/DSL-50
MSM5116160D/DSL-60
MSM5116160D/DSL-70
90 ns
110 ns
130 ns
495 mW
468 mW
440 mW
5.5 mW/
1.1 mW (SL version)
1/16
¡ Semiconductor
MSM5116160D/DSL
PIN CONFIGURATION (TOP VIEW)
VCC
1
42 VSS
VCC
1
50 VSS
VSS 50
1 VCC
2 DQ1
3 DQ2
4 DQ3
5 DQ4
6 VCC
DQ1 2
DQ2 3
DQ3 4
DQ4 5
41 DQ16 DQ1 2
40 DQ15 DQ2 3
39 DQ14 DQ3 4
38 DQ13 DQ4 5
49 DQ16 DQ16 49
48 DQ15 DQ15 48
47 DQ14 DQ14 47
46 DQ13 DQ13 46
VCC
6
37 VSS
VCC
6
45 VSS
VSS 45
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
36 DQ12 DQ5 7
35 DQ11 DQ6 8
34 DQ10 DQ7 9
44 DQ12 DQ12 44
43 DQ11 DQ11 43
42 DQ10 DQ10 42
7 DQ5
8 DQ6
9 DQ7
10 DQ8
11 NC
33 DQ9
32 NC
DQ8 10
NC 11
41 DQ9
40 NC
DQ9 41
NC 40
NC 12
31 LCAS
30 UCAS
29 OE
WE 13
RAS 14
A11R 15
A10R 16
A0 17
28 A9R
27 A8R
26 A7
NC 15
NC 16
36 NC
NC 36
15 NC
16 NC
17 WE
18 RAS
19 A11R
20 A10R
21 A0
35 LCAS LCAS 35
34 UCAS UCAS 34
WE 17
RAS 18
A11R 19
A10R 20
A0 21
A1 18
25 A6
33 OE
32 A9R
31 A8R
30 A7
29 A6
28 A5
27 A4
26 VSS
OE 33
A9R 32
A8R 31
A7 30
A2 19
24 A5
A3 20
23 A4
VCC 21
22 VSS
A1 22
A6 29
22 A1
42-Pin Plastic SOJ
A2 23
A5 28
23 A2
A3 24
A4 27
24 A3
VCC 25
VSS 26
25 VCC
50/44-Pin Plastic TSOP
(K Type)
50/44-Pin Plastic TSOP
(L Type)
Pin Name
A0 - A7,
A8R - A11R
RAS
Function
Address Input
Row Address Strobe
LCAS
Lower Byte Column Address Strobe
Upper Byte Column Address Strobe
Data Input/Data Output
Output Enable
UCAS
DQ1 - DQ16
OE
WE
Write Enable
VCC
Power Supply (5 V)
Ground (0 V)
VSS
NC
No Connection
Note :
The same power supply voltage must be provided to every V pin, and the same GND
CC
voltage level must be provided to every V pin.
SS
2/16
¡ Semiconductor
MSM5116160D/DSL
BLOCK DIAGRAM
WE
OE
Timing
Generator
RAS
I/O
Controller
LCAS
UCAS
Output
8
8
8
Buffers
I/O
Controller
DQ1 - DQ8
Column
Address
Buffers
Input
8
Column Decoders
8
8
Buffers
I/O
Selector
Internal
Address
Counter
Sense Amplifiers
16
16
Refresh
Control Clock
A0 - A7
Input
8
8
8
Buffers
8
4
Row
Address
Buffers
Row
Memory
Cells
12
DQ9 - DQ16
Deco-
Word
Drivers
ders
A8R - A11R
VCC
Output
8
Buffers
On Chip
V
Generator
BB
On Chip
IV Generator
CC
VSS
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS
LCAS
UCAS
WE
OE
DQ1 - DQ8
High-Z
High-Z
DOUT
DQ9 - DQ16
High-Z
Standby
Refresh
H
L
L
L
L
L
L
L
L
*
H
*
H
H
*
*
High-Z
*
H
*
L
High-Z
Lower Byte Read
Upper Byte Read
Word Read
L
H
L
L
H
L
L
High-Z
DOUT
L
L
H
L
L
L
H
H
L
L
L
DOUT
DOUT
DIN
Lower Byte Write
Upper Byte Write
Word Write
—
H
H
H
H
Don't Care
DIN
Don't Care
DIN
L
DIN
L
High-Z
High-Z
H
*: "H" or "L"
3/16
¡ Semiconductor
MSM5116160D/DSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
–0.5 to VCC + 0.5
–0.5 to 7
50
Unit
V
V
IOS
mA
W
PD
*
1
Operating Temperature
Topr
Tstg
0 to 70
°C
°C
Storage Temperature
–55 to 150
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Symbol
VCC
Min.
4.5
Typ.
5.0
0
Max.
Unit
5.5
V
V
V
V
VSS
0
0
Input High Voltage
Input Low Voltage
VIH
2.4
–0.5*2
—
VCC + 0.5*1
VIL
—
0.8
Notes : *1. TheinputvoltageisV +2.0Vwhenthepulsewidthislessthan20ns(thepulsewidth
CC
is with respect to the point at which V is applied).
CC
*2. TheinputvoltageisV –2.0Vwhenthepulsewidthislessthan20ns(thepulsewidth
SS
is with respect to the point at which V is applied).
SS
Capacitance
(VCC = 5 V 10ꢀ, Ta = 25°C, f = 1 MHꢁ)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance
(A0 - A7, A8R - A11R)
CIN1
—
5
pF
Input Capacitance
CIN2
CI/O
—
—
7
7
pF
pF
(RAS, LCAS, UCAS, WE, OE)
Output Capacitance (DQ1 - DQ16)
4/16
¡ Semiconductor
MSM5116160D/DSL
DC Characteristics
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C)
MSM5116160 MSM5116160 MSM5116160
D/DSL-50 D/DSL-60 D/DSL-70
Parameter
Symbol
Condition
Unit Note
Min. Max. Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
VOH IOH = –5.0 mA
VOL IOL = 4.2 mA
0 V £ VI £ 6.5 V;
ILI All other pins not
under test = 0 V
DQ disable
2.4
0
VCC
0.4
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
Input Leakage Current
–10
–10
—
10
10
90
–10
–10
—
10
10
85
–10
–10
—
10
10
80
mA
Output Leakage Current ILO
mA
0 V £ VO £ VCC
Average Power
RAS, CAS cycling,
Supply Current
(Operating)
ICC1
mA 1, 2
tRC = Min.
RAS, CAS = VIH
—
—
—
2
1
—
—
—
2
1
—
—
—
2
1
Power Supply
mA
1
ICC2 RAS, CAS
≥ VCC –0.2 V
RAS cycling,
ICC3 CAS = VIH,
tRC = Min.
Current (Standby)
200
200
200 mA 1, 5
Average Power
Supply Current
—
—
—
—
—
90
5
—
—
—
—
—
85
5
—
—
—
—
—
80
5
mA 1, 2
(RAS-only Refresh)
RAS = VIH,
Power Supply
ICC5 CAS = VIL,
DQ = enable
mA
1
Current (Standby)
Average Power
Supply Current
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
Supply Current
(Battery Backup)
Average Power
Supply Current
(CAS before RAS
Self-Refresh)
RAS cycling,
ICC6
90
85
400
85
80
400
80
75
mA 1, 2
CAS before RAS
RAS = VIL,
ICC7 CAS cycling,
mA 1, 3
1, 4,
tPC = Min.
tRC = 125 ms,
ICC10 CAS before RAS,
tRAS £ 1 ms
400 mA
5
RAS £ 0.2 V,
ICCS
—
300
—
300
—
300 mA 1, 5
CAS £ 0.2 V
Notes : 1. I Max. is specified as I for output open condition.
CC
CC
2. The address can be changed once or less while RAS = V .
IL
3. The address can be changed once or less while CAS = V
.
IH
4. V – 0.2 V £ V £ V + 0.5 V, –0.5 V £ V £ 0.2 V.
CC
IH
CC
IL
5. SL version.
5/16
¡ Semiconductor
MSM5116160D/DSL
AC Characteristics (1/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3
MSM5116160 MSM5116160 MSM5116160
D/DSL-50 D/DSL-60 D/DSL-70
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
tRC
tRWC
tPC
90
131
35
—
—
—
110
155
40
—
—
—
130
185
45
—
—
—
ns
ns
ns
Fast Page Mode Read Modify Write
Cycle Time
tPRWC
76
—
85
—
100
—
ns
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precharge
tRAC
tCAC
tAA
—
—
—
—
50
13
25
30
—
—
—
—
60
15
30
35
—
—
—
—
70
20
35
40
ns 4, 5, 6
ns
ns
4, 5
4, 6
tCPA
ns 4, 12
Access Time from OE
Output Low Impedance Time from CAS
tOEA
tCLZ
—
0
13
—
13
13
50
64
128
—
—
0
15
—
15
15
50
64
128
—
—
0
20
—
20
20
50
64
128
—
ns
ns
ns
ns
ns
ms
ms
ns
4
4
7
7
3
CAS to Data Output Buffer Turn-off Delay Time tOFF
OE to Data Output Buffer Turn-off Delay Time
Transition Time
0
0
0
tOEZ
tT
tREF
tREF
tRP
0
3
—
—
30
0
3
—
—
40
0
3
—
—
50
Refresh Period
Refresh Period (SL version)
RAS Precharge Time
15
RAS Pulse Width
tRAS
50 10,000 60 10,000 70 10,000 ns
50 100,000 60 100,000 70 100,000 ns
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
RAS Hold Time referenced to OE
CAS Precharge Time (Fast Page Mode)
CAS Pulse Width
tRASP
tRSH
tROH
tCP
13
13
7
—
—
—
15
15
10
—
—
—
20
20
10
—
—
—
ns
ns
ns
14
tCAS
tCSH
tCRP
tRHCP
tRCD
tRAD
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
13 10,000 15 10,000 20 10,000 ns
CAS Hold Time
50
5
—
—
—
37
25
—
—
—
—
—
—
—
—
60
5
—
—
—
45
30
—
—
—
—
—
—
—
—
70
5
—
—
—
50
35
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
12
12
5
30
17
12
0
35
20
15
0
40
20
15
0
6
7
10
0
10
0
Column Address Set-up Time
Column Address Hold Time
Column Address to RAS Lead Time
Read Command Set-up Time
Read Command Hold Time
0
11
11
7
10
30
0
15
35
0
25
0
11
0
0
0
ns 8, 11
Read Command Hold Time referenced to RAS tRRH
0
0
0
ns
8
6/16
¡ Semiconductor
MSM5116160D/DSL
AC Characteristics (2/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3
MSM5116160 MSM5116160 MSM5116160
D/DSL-50 D/DSL-60 D/DSL-70
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Write Command Set-up Time
Write Command Hold Time
tWCS
tWCH
0
7
—
—
0
—
—
0
—
—
ns 9, 11
10
15
ns
11
Write Command Pulse Width
OE Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
tWP
tOEH
tRWL
tCWL
7
—
—
—
—
10
15
15
15
—
—
—
—
10
20
20
20
—
—
—
—
ns
ns
ns
ns
13
13
13
13
Data-in Set-up Time
tDS
tDH
tOED
tCWD
tAWD
tRWD
0
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
0
15
20
50
65
100
70
5
—
—
—
—
—
—
—
—
—
—
ns 10, 11
ns 10, 11
ns
Data-in Hold Time
OE to Data-in Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
RAS to WE Delay Time
7
10
15
40
55
85
60
5
13
36
48
73
ns
ns
ns
ns
ns
ns
ns
9
9
9
CAS Precharge WE Delay Time
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS) tCSR
RAS to CAS Hold Time (CAS before RAS)
RAS Pulse Width
tCPWD 53
9
tRPC
5
11
11
12
10
10
10
10
10
10
tCHR
tRASS 100
—
—
—
100
110
–50
—
—
—
100
130
–50
—
—
—
ms
ns
ns
15
15
15
(CAS before RAS Self-Refresh)
RAS Precharge Time
tRPS
tCHS
90
(CAS before RAS Self-Refresh)
CAS Hold Time
–50
(CAS before RAS Self-Refresh)
7/16
¡ Semiconductor
MSM5116160D/DSL
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume t = 5 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.
IH
IL
Transition times (t ) are measured between V and V .
T
IH
IL
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t (Max.) limit ensures that t (Max.) can be met.
RCD
RAC
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
is greater than the specified
RCD
RCD
t
.
RCD
CAC
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RAD
RAC
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
is greater than the specified
RAD
RAD
t
.
RAD
AA
7. t
(Max.) and t
(Max.) define the time at which the output achieves the open
OFF
OEZ
circuit condition and are not referenced to output voltage levels.
8. t
9. t
or t
must be satisfied for a read cycle.
RCH
RRH
, t
, t
, t
and t
are not restrictive operating parameters. They are
WCS CWD RWD AWD
CPWD
included in the data sheet as electrical characteristics only. If t
≥t
(Min.), then
WCS WCS
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t ≥ t (Min.) , t ≥ t (Min.),
CWD
CWD
RWD
RWD
t
≥ t
(Min.) and t
≥ t
(Min.), then the cycle is a read modify write
AWD
AWD
CPWD
CPWD
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the UCAS and LCAS, leading edges in an early
write cycle, and to the WE leading edge in an OE control write cycle, or a read modify
write cycle.
11. These parameters are determined by the falling edge of either UCAS or LCAS,
whichever is earlier.
12. These parameters are determined by the rising edge of either UCAS or LCAS,
whichever is later.
13. t
should be satisfied by both UCAS and LCAS.
CWL
14. t is determined by the time both UCAS and LCAS are high.
CP
15. Only SL version.
8/16
E2G0103-29-41P
¡ Semiconductor
MSM5116160D/DSL
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
tCRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
CAS
tRAD
tASC
tASR
Row
tRAH
tRAL
tCAH
Column
VIH
VIL
–
–
Address
tRCH
tRCS
tRRH
VIH
VIL
–
–
tAA
WE
OE
tROH
tOEA
VIH
VIL
–
–
tOFF
tCAC
tRAC
tOEZ
VOH
VOL
–
–
DQ
Open
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
VIH
VIL
–
–
tCRP
RAS
CAS
tCSH
tCRP
tRCD
tRAD
tRAH
tASC
tRSH
tCAS
VIH
VIL
–
–
tRAL
tASR
Row
tCAH
Column
tWCH
VIH
VIL
–
–
Address
tWCS
tCWL
VIH
VIL
–
–
tWP
WE
tRWL
VIH
VIL
–
–
OE
tDS
tDH
VIH
VIL
–
–
DQ
Open
Valid Data-in
"H" or "L"
9/16
¡ Semiconductor
MSM5116160D/DSL
Read Modify Write Cycle
tRWC
tRAS
tRP
VIH
VIL
–
–
RAS
CAS
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
tRAH
tASC
tASR
tCAH
Column
VIH
VIL
–
–
Row
Address
tCWL
tRWL
tWP
tCWD
tAWD
tRAD
tRWD
tOEA
VIH
VIL
–
–
tAA
WE
OE
tRCS
VIH
VIL
–
–
tOED
tOEZ
tOEH
tDH
tCAC
tDS
tRAC
VI/OH
–
Valid
Data-out
Valid
Data-in
DQ
–
tCLZ
VI/OL
"H" or "L"
10/16
¡ Semiconductor
MSM5116160D/DSL
Fast Page Mode Read Cycle
tRASP
tRP
tRHCP
VIH
VIL
–
–
RAS
CAS
tCRP
tPC
tRSH
tCAS
tCRP
tRCD
tRAD
tRAH tASC
tCP
tCP
tCAS
tCAS
VIH
VIL
–
–
tRAL
tASC tCAH
tCSH
tCAH
tASR
Row
tASC
tCAH
VIH
VIL
–
–
Column
Column
Column
tRCS
Address
tRCH
tRCS
tRCS
tRCH
tRCH
VIH
VIL
–
–
WE
tAA
tAA
tAA
tRRH
tCPA
tCPA
tOEA
tOEA
tOEA
VIH
VIL
–
–
OE
tOFF
tOEZ
tOFF
tOEZ
tCAC
tCLZ
tCAC
tCLZ
tOFF
tCAC
tRAC
tOEZ
VOH
VOL
–
–
Valid
Data-out
Valid
Data-out
Valid
Data-out
DQ
tCLZ
"H" or "L"
Fast Page Mode Write Cycle (Early Write)
tRASP
tPC
tRP
tCRP
tRHCP
VIH
VIL
–
–
RAS
CAS
tRSH
tCAS
tRAL
tCRP
tRCD
tCP
tCP
tCAS
tCAS
tCAH
Column
VIH
VIL
–
–
tCSH
tCAH
tASR
Row
tASC
tASC
tASC
tRAH
tCAH
VIH
VIL
–
–
Column
tCWL
tWCH
tWP
Column
Address
tRAD
tWCS
tCWL
tWCH
tWP
tRWL
tCWL
tWCH
tWP
tWCS
tWCS
VIH
VIL
–
–
WE
tDS
tDS
tDS
tDH
tDH
tDH
VIH
VIL
–
–
Valid
Data-in
Valid
Data-in
Valid Data-in
DQ
Note: OE = "H" or "L"
"H" or "L"
11/16
¡ Semiconductor
MSM5116160D/DSL
Fast Page Mode Read Modify Write Cycle
tRASP
VIH
VIL
–
–
RAS
CAS
tRP
tCSH
tPRWC
tCAS
tRSH
tCAS
tCRP
tCP
tCP
tRCD
tRAD
tRAH
tCAS
VIH
VIL
–
–
tASC
tCAH
tASC
tRAL
tCAH
tCAH
tASR
tASC
VIH
VIL
–
–
Column
tRWD
Column
tRCS
Column
tRCS
Address
Row
tCPWD
tCWD
tCPWD
tRWL
tCWL
tCWD
tCWD
tRCS
tCWL
tCWL
VIH
VIL
–
–
WE
tAWD
tAWD
tAWD
tROH
tWP
tWP
tDH
tWP
tDH
tDH
tDS
tDS
tDS
tRAC
tCPA
tAA
tCPA
tAA
tAA
tOEA
tOEA
tOEA
tOED
tOED
tOED
VIH
VIL
–
–
OE
tOEZ
tOEZ
tOEZ
tCAC
tCAC
tCAC
VI/OH
–
DQ
Out
In
Out
In
Out
In
–
VI/OL
tCLZ
tCLZ
tCLZ
"H" or "L"
RAS-Only Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tCRP
tRPC
VIH
VIL
–
–
tASR tRAH
VIH
VIL
–
–
Address
DQ
Row
tOFF
VOH
VOL
–
–
Open
Note: WE, OE = "H" or "L"
"H" or "L"
12/16
¡ Semiconductor
MSM5116160D/DSL
CAS before RAS Refresh Cycle
tRC
tRP
tRP
tRAS
VIH
VIL
–
–
RAS
tRPC
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
CAS
tOFF
VOH
VOL
–
–
DQ
Open
Note: WE, OE, Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRAS
tRP
tRP
VIH
VIL
–
–
RAS
tCRP
tRSH
tRCD
tCHR
VIH
VIL
–
–
tRAD
tASC
tRAH
CAS
tCAH
tASR
VIH
VIL
–
–
Address
Row
Column
tRCS
tRRH
tRAL
VIH
VIL
–
–
tAA
WE
OE
tROH
tOEA
VIH
VIL
–
–
tCAC
tCLZ
tOFF
tRAC
tOEZ
VOH
VOL
–
–
DQ
Valid Data-out
"H" or "L"
13/16
¡ Semiconductor
MSM5116160D/DSL
Hidden Refresh Write Cycle
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
–
–
RAS
tCRP
tRCD
tRSH
tCHR
VIH
VIL
–
–
tRAD
tASC
CAS
tCAH
Column
tASR
Row
tRAH
tRAL
VIH
VIL
–
–
Address
tWRP
tWRH
tWCS
tWCH
tWP
VIH
VIL
–
–
WE
OE
VIH
VIL
–
–
tDS
tDH
Valid Data-in
VIH
VIL
–
–
DQ
"H" or "L"
CAS before RAS Self-Refresh Cycle
tRASS
tRPS
tRP
VIH
VIL
–
–
RAS
CAS
tRPC
tCP
tRPC
tCHS
tCSR
VIH
VIL
–
–
tOFF
VOH
VOL
–
–
DQ
Open
Note: WE, OE, Address = "H" or "L"
"H" or "L"
Only SL version
14/16
¡ Semiconductor
PACKAGE DIMENSIONS
SOJ42-P-400-1.27
MSM5116160D/DSL
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.86 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
15/16
¡ Semiconductor
MSM5116160D/DSL
(Unit : mm)
TSOPII50/44-P-400-0.80-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.60 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
16/16
E2Y0002-29-11
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
相关型号：
MSM5116160D-50JS
Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO42, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-42
OKI
MSM5116160D-50TS-L
Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, REVERSE, TSOP-50/44
OKI
MSM5116160D-60TS-K
Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP-50/44
OKI
MSM5116160D-70TS-K
Fast Page DRAM, 1MX16, 70ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP-50/44
OKI
MSM5116160D-70TS-L
Fast Page DRAM, 1MX16, 70ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, REVERSE, TSOP-50/44
OKI
MSM5116160DSL-50JS
Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO42, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-42
OKI
MSM5116160DSL-50TS-K
Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP-50/44
OKI
MSM5116160DSL-50TS-L
Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, REVERSE, TSOP-50/44
OKI
MSM5116160DSL-60JS
Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO42, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-42
OKI
MSM5116160DSL-60TS-K
Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP-50/44
OKI
MSM5116160DSL-60TS-L
Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, REVERSE, TSOP-50/44
OKI
©2020 ICPDF网 联系我们和版权申明