MSM514100D-70TS-K [OKI]
暂无描述;
| 型号： | MSM514100D-70TS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 暂无描述 |
| 文件： | 总17页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2G0022-17-41
This version: Jan. 1998
Previous version: May 1997
¡ Semiconductor
MSM514100D/DL
4,194,304-Word ¥ 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM514100D/DL is a 4,194,304-word ¥ 1-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM514100D/DL achieves high integration, high-speed operation, and
low-powerconsumptionbecauseOkimanufacturesthedeviceinaquadruple-layerpolysilicon/
single-layer metal CMOS process. The MSM514100D/DL is available in a 26/20-pin plastic SOJ, 20-
pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514100DL (the low-power version) is specially
designed for lower-power applications.
FEATURES
• 4,194,304-word ¥ 1-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Package options:
26/20-pin 300 mil plastic SOJ
20-pin 400 mil plastic ZIP
(SOJ26/20-P-300-1.27)
(ZIP20-P-400-1.27)
(Product : MSM514100D/DL-xxSJ)
(Product : MSM514100D/DL-xxZS)
26/20-pin 300 mil plastic TSOP
(TSOPII26/20-P-300-1.27-K) (Product : MSM514100D/DL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Cycle Time
(Min.)
Power Dissipation
Family
tRAC
50 ns
60 ns
70 ns
tAA
tCAC
13 ns
15 ns
20 ns
Standby (Max.)
Operating (Max.)
25 ns
30 ns
35 ns
MSM514100D/DL-50
MSM514100D/DL-60
MSM514100D/DL-70
90 ns
110 ns
130 ns
550 mW
495 mW
440 mW
5.5 mW/
1.1 mW (L-version)
1/17
¡ Semiconductor
MSM514100D/DL
PIN CONFIGURATION (TOP VIEW)
A9 1
DIN
1
26 VSS
25 DOUT
24 CAS
23 NC
22 A9
DIN
1
26 VSS
25 DOUT
24 CAS
23 NC
22 A9
2
4
6
8
CAS
VSS
WE
DOUT
DIN
3
5
WE 2
RAS 3
NC 4
WE 2
RAS 3
NC 4
RAS 7
NC 9
A0 11
A2 13
VCC 15
A5 17
A7 19
A10
A10 5
A10 5
10 NC
12 A1
14 A3
16 A4
18 A6
20 A8
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
26/20-Pin Plastic SOJ
20-Pin Plastic ZIP
26/20-Pin Plastic TSOP
(K Type)
Pin Name
Function
A0 - A10
RAS
CAS
DIN
Address Input
Row Address Strobe
Column Address Strobe
Data Input
DOUT
WE
Data Output
Write Enable
VCC
Power Supply (5 V)
Ground (0 V)
VSS
NC
No Connection
2/17
¡ Semiconductor
MSM514100D/DL
BLOCK DIAGRAM
Timing
Generator
RAS
CAS
Timing
Generator
Write
Column
Address
Buffers
WE
Column
Decoders
Clock
11
11
Generator
Internal
Address
Counter
I/O
Selector
Refresh
Control Clock
Sense
Amplifiers
Output
Buffer
DOUT
A0 - A10
Row
Address
Buffers
Row
De-
Word
Drivers
Memory
Cells
11
11
Input
Buffer
DIN
coders
VCC
On Chip
Generator
V
BB
VSS
3/17
¡ Semiconductor
MSM514100D/DL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VT
Rating
–1.0 to 7.0
50
Unit
V
IOS
mA
W
PD
*
1
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Symbol
VCC
Min.
4.5
0
Typ.
5.0
0
Max.
Unit
5.5
0
V
V
V
V
VSS
Input High Voltage
Input Low Voltage
VIH
2.4
–1.0
—
6.5
0.8
VIL
—
Capacitance
(VCC = 5 V 10ꢀ, Ta = 25°C, f = 1 MHꢁ)
Parameter
Symbol
CIN1
Typ.
Max.
Unit
pF
Input Capacitance (A0 - A10, DIN)
—
—
—
6
7
7
Input Capacitance (RAS, CAS, WE)
CIN2
pF
Output Capacitance (DOUT
)
COUT
pF
4/17
¡ Semiconductor
MSM514100D/DL
DC Characteristics
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C)
MSM514100 MSM514100 MSM514100
D/DL-50 D/DL-60 D/DL-70
Parameter
Symbol
Condition
Unit Note
Min. Max. Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
VOH IOH = –5.0 mA
VOL IOL = 4.2 mA
0 V £ VI £ 6.5 V;
ILI All other pins not
under test = 0 V
2.4
0
VCC
0.4
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
Input Leakage Current
–10
–10
—
10
10
–10
–10
—
10
10
90
–10
–10
—
10
10
80
mA
DOUT disable
Output Leakage Current ILO
Average Power
mA
0 V £ VO £ 5.5 V
RAS, CAS cycling,
Supply Current
(Operating)
ICC1
100
mA 1, 2
tRC = Min.
RAS, CAS = VIH
—
—
—
2
1
—
—
—
2
1
—
—
—
2
1
Power Supply
mA
1
ICC2 RAS, CAS
≥ VCC –0.2 V
RAS cycling,
ICC3 CAS = VIH,
tRC = Min.
Current (Standby)
200
200
200
mA 1, 5
Average Power
Supply Current
—
—
—
—
—
100
5
—
—
—
—
—
90
5
—
—
—
—
—
80
5
mA 1, 2
(RAS-only Refresh)
RAS = VIH,
Power Supply
ICC5 CAS = VIL,
DOUT = enable
mA
1
Current (Standby)
Average Power
Supply Current
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
Supply Current
(Battery Backup)
RAS cycling,
ICC6
100
80
90
70
300
80
60
300
mA 1, 2
mA 1, 3
CAS before RAS
RAS = VIL,
ICC7 CAS cycling,
tPC = Min.
tRC = 125 ms,
1, 4,
ICC10
300
mA
CAS before RAS,
tRAS £ 1 ms
5
Notes : 1. I Max. is specified as I for output open condition.
CC
CC
2. The address can be changed once or less while RAS = V .
IL
3. The address can be changed once or less while CAS = V
4. V – 0.2 V £ V £ 6.5 V, –1.0 V £ V £ 0.2 V.
.
IH
CC
IH
IL
5. L-version.
5/17
¡ Semiconductor
MSM514100D/DL
AC Characteristics (1/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
MSM514100 MSM514100 MSM514100
D/DL-50
D/DL-60
D/DL-70
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
tRC
tRWC
tPC
90
108
35
—
—
—
110
130
40
—
—
—
130
155
45
—
—
—
ns
ns
ns
tPRWC
53
—
60
—
70
—
ns
Access Time from RAS
tRAC
tCAC
tAA
—
—
—
—
0
50
13
—
—
—
—
0
60
15
—
—
—
—
0
70
20
35
40
—
20
50
16
128
—
ns 4, 5, 6
Access Time from CAS
ns
ns
ns
ns
ns
ns
ms
ms
ns
4, 5
4, 6
4
Access Time from Column Address
Access Time from CAS Precharge
Output Low Impedance Time from CAS
25
30
tCPA
tCLZ
30
35
—
—
4
CAS to Data Output Buffer Turn-off Delay Time tOFF
0
13
0
15
0
7
Transition Time
tT
3
50
3
50
3
3
Refresh Period
tREF
tREF
tRP
—
—
30
50
50
13
10
13
50
5
16
—
—
40
60
60
15
10
15
60
5
16
—
—
50
70
70
20
10
20
70
5
Refresh Period (L-version)
RAS Precharge Time
128
—
128
—
RAS Pulse Width
tRAS
tRASP
tRSH
tCP
10,000
100,000
—
10,000
100,000
—
10,000 ns
100,000 ns
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
—
—
ns
ns
CAS Precharge Time (Fast Page Mode)
CAS Pulse Width
—
—
tCAS
tCSH
tCRP
tRHCP
tRCD
tRAD
tASR
tRAH
tASC
tCAH
tAR
10,000
—
10,000
—
10,000 ns
CAS Hold Time
—
—
—
50
35
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
—
—
30
20
15
0
—
35
20
15
0
—
40
20
15
0
37
45
5
6
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
Column Address Hold Time from RAS
Column Address to RAS Lead Time
25
30
—
—
10
0
—
10
0
—
10
0
—
—
10
45
25
—
15
50
30
—
15
55
35
—
—
tRAL
—
—
6/17
¡ Semiconductor
MSM514100D/DL
AC Characteristics (2/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
MSM514100 MSM514100 MSM514100
D/DL-50
D/DL-60
D/DL-70
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Read Command Set-up Time
Read Command Hold Time
tRCS
tRCH
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
9
Read Command Hold Time referenced to RAS tRRH
0
0
0
Write Command Set-up Time
Write Command Hold Time
Write Command Hold Time from RAS
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
tWCS
tWCH
tWCR
tWP
0
0
0
10
40
10
13
13
0
10
45
10
15
15
0
10
50
10
20
20
0
tRWL
tCWL
tDS
10
10
Data-in Hold Time
tDH
10
45
13
25
50
30
10
5
15
50
15
30
60
35
10
5
15
55
20
35
70
40
10
5
Data-in Hold Time from RAS
CAS to WE Delay Time
tDHR
tCWD
tAWD
tRWD
tCPWD
9
9
9
9
Column Address to WE Delay Time
RAS to WE Delay Time
CAS Precharge WE Delay Time
CAS Active Delay Time from RAS Precharge tRPC
RAS to CAS Set-up Time (CAS before RAS) tCSR
RAS to CAS Hold Time (CAS before RAS) tCHR
WE to RAS Precharge Time (CAS before RAS) tWRP
WE Hold Time from RAS (CAS before RAS) tWRH
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
RAS to WE Set-up Time (Test Mode)
RAS to WE Hold Time (Test Mode)
tWTS
tWTH
7/17
¡ Semiconductor
MSM514100D/DL
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of
eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before
proper device operation is achieved.
2. The AC characteristics assume t = 5 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.
IH
IL
Transition times (t ) are measured between V and V .
T
IH
IL
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t (Max.) limit ensures that t (Max.) can be met.
RCD
RAC
t
t
(Max.)isspecifiedasareferencepointonly. Ift
(Max.) limit, then the access time is controlled by t
isgreaterthanthespecified
RCD
RCD
RCD
.
CAC
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RAD
RAC
t
t
(Max.)isspecifiedasareferencepointonly. Ift
(Max.) limit, then the access time is controlled by t
isgreaterthanthespecified
RAD
RAD
RAD
.
AA
7. tOFF (Max.)definesthetimeatwhichtheoutputachievestheopencircuitconditionand
is not referenced to output voltage levels.
8. t
9. t
or t
must be satisfied for a read cycle.
RCH
RRH
, t
, t
, t
and t
are not restrictive operating parameters. They are
WCS CWD RWD AWD
CPWD
included in the data sheet as electrical characteristics only. If t
≥t
(Min.), then
WCS WCS
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t ≥t (Min.) , t ≥t (Min.),
CWD CWD
RWD RWD
t
≥t
(Min.) and t
≥t
(Min.), then the cycle is a read modify write
AWD AWD
CPWD CPWD
cycleanddataoutwillcontaindatareadfromtheselectedcell;ifneitheroftheabove
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. TheseparametersarereferencedtotheCASleadingedgeinanearlywritecycle,and
to the WE leading edge in a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. RA10,
CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data
output pin will indicate a high level. If any internal bits are not equal, the data
output pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specifiedvalue.Theseparametersshouldbespecifiedintestmodecyclebyaddingthe
above value to the specified value in this data sheet.
8/17
E2G0090-17-41C
¡ Semiconductor
MSM514100D/DL
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
tRAD
tRAL
tCAH
tASR
tRAH
Row
tASC
VIH
VIL
–
–
Address
Column
tAR
tRCH
tRRH
tRCS
VIH
VIL
–
–
WE
tCAC
tCLZ
tAA
tOFF
tRAC
VOH
VOL
–
–
DOUT
Open
Valid Data
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tRCD
tRSH
tCAS
tCRP
tCRP
tCSH
VIH
VIL
–
–
tAR
tRAD
tRAL
tCAH
tASR
tRAH
Row
tASC
VIH
VIL
–
–
Address
Column
tCWL
tWCR
tWCS
tWCH
VIH
VIL
–
–
tWP
tRWL
WE
tDHR
tDS
tDH
VIH
VIL
–
–
DIN
Valid Data
VOH
VOL
–
–
DOUT
Open
"H" or "L"
9/17
¡ Semiconductor
MSM514100D/DL
Read Modify Write Cycle
tRWC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tRSH
tCRP
tCRP
tRWL
tRCD
tCAS
VIH
VIL
–
–
tCSH
tRAL
tCAH
tAR
tCWL
tRAD
tRAH
tASR
tASC
VIH
VIL
–
–
Address
Row
Column
tAWD
tRWD
tWP
tCWD
VIH
VIL
–
–
WE
tRCS
tDS
tDH
Valid Data
VIH
VIL
–
–
DIN
tCAC
tAA
tOFF
tRAC
VOH
VOL
–
–
DOUT
Open
Valid Data
tCLZ
"H" or "L"
Fast Page Mode Read Cycle
tRASP
tRP
VIH –
tRHCP
RAS
VIL
–
tCSH
tRCD
tPC
tCAS
tRSH
tCAS
tCRP
tCP
tCAS
tCP
tCRP
VIH –
CAS
VIL
–
tAR
tASC
tRAL
tCAH
tASR
tASC
tCAH
tRAH
Row
tCAH
tASC
VIH
VIL
–
–
Address
Column
Column
Column
tRRH
tRCH
tRAD
tRCH
tRCH
tRCS
tRCS
tRCS
VIH –
WE
tCAC
tCAC
tCAC
VIL
–
tAA
tCPA
tAA
tCPA
tAA
tRAC
VOH –
Valid
Data
Valid
Data
Valid
Data
DOUT
VOL
–
tOFF
tCLZ
tOFF
tCLZ
tOFF
tCLZ
"H" or "L"
10/17
¡ Semiconductor
MSM514100D/DL
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
VIH
VIL
–
–
tRHCP
RAS
CAS
tRSH
tCAS
tPC
tCAS
tCRP
tCAS
tCP
tRCD
tCP
tCRP
VIH
VIL
–
–
tAR
t
tRAL
tCAH
tASR
tCAH
Column
tCAH
Column
tRAH
Row
tASC
tASC
ASC
VIH
VIL
–
–
Address
Column
tRWL
tCWL
tRAD
tWCR
tWCS
tCWL
tCWL
tWCH
tWCH
tWCS
tWCS
tWCH
VIH
VIL
–
–
tWP
tWP
tWP
WE
tDS
tDS
tDS
tDH
tDH
tDH
VIH
VIL
–
–
DIN
Valid Data
tDHR
Valid Data
Valid Data
VOH
VOL
–
–
DOUT
Open
"H" or "L"
Fast Page Mode Read Modify Write Cycle
tRASP
VIH
–
tRHCP
tRSH
tCAS
RAS
tRP
VIL
–
tCSH
tPRWC
tCAS
tCRP
tRCD
tCP
tCP
tCAS
VIH
VIL
–
–
CAS
tAR
tRAH
tASC
tRAL
tCAH
tCAH
tCAH
tASR
tASC
tASC
VIH
VIL
–
–
Address
Column
Column
Row
Column
tRWD
tCPWD
tCPWD
tCWL
tRCS
tRCS
tCWL
tRCS
tCWL
tCWD
tCWD
tCWD
VIH
VIL
–
–
tAWD
tAWD
tAWD
tAA
WE
tCPA
tCPA
tWP
tWP
tWP
tAA
tAA
tCAC
tRAD
tCAC
tCAC
tOFF
tOFF
tOFF
VOH
VOL
–
–
DOUT
Valid Data
tDH
Valid Data
tDH
Valid Data
tRAC
tCLZ
tRWL
tCLZ
tCLZ
tDH
tDS
tDS
tDS
VIH
VIL
–
–
Valid
Data
Valid
Data
Valid
Data
DIN
"H" or "L"
11/17
¡ Semiconductor
MSM514100D/DL
RAS-Only Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
tRPC
tCRP
VIH
VIL
–
–
CAS
tASR
tRAH
VIH
VIL
–
–
Address
Row
tOFF
VOH
VOL
–
–
DOUT
Open
Note: WE = "H" or "L"
"H" or "L"
CAS before RAS Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
tRPC
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
CAS
WE
tWRP
tWRH
tWRP
VIH
VIL
–
–
tOFF
VOH
VOL
–
–
DOUT
Open
Note: Address = "H" or "L"
"H" or "L"
12/17
¡ Semiconductor
MSM514100D/DL
Hidden Refresh Read Cycle
tRC
tRAS
tRAS
tRP
VIH
VIL
–
–
RAS
CAS
tRCD
tRSH
tCHR
tCRP
VIH
VIL
–
–
tRAD
tRAH
tRAL
tASC tCAH
tASR
Row
VIH
VIL
–
–
Address
Column
tAR
tRRH tWRP
tRCS
tWRH
VIH
VIL
–
–
tCAC
WE
tAA
tOFF
tRAC
VOH
VOL
–
–
DOUT
Valid Data
tCLZ
"H" or "L"
Hidden Refresh Write Cycle
tRC
tRAS
tRAS
tRP
VIH
VIL
–
–
RAS
CAS
tRCD
tRAD
tRSH
tCHR
tCRP
VIH
VIL
–
–
tAR
tRAL
tASC tCAH
tRAH
Row
tASR
VIH
VIL
–
–
Address
Column
tWCR
tWCS
tRWL
tWCH
tWP
tWRP
tWRH
VIH
VIL
–
–
WE
tDS
tDH
VIH
VIL
–
–
DIN
Valid Data
tDHR
VOH
VOL
–
–
DOUT
Open
"H" or "L"
13/17
¡ Semiconductor
MSM514100D/DL
Test Mode Initiate Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
CAS
WE
tWTS
tWTH
VIH
VIL
–
–
tOFF
VOH
VOL
–
–
DOUT
Open
Note: Address, DIN = "H" or "L"
"H" or "L"
14/17
¡ Semiconductor
PACKAGE DIMENSIONS
SOJ26/20-P-300-1.27
MSM514100D/DL
(Unit : mm)
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
15/17
¡ Semiconductor
MSM514100D/DL
(Unit : mm)
ZIP20-P-400-1.27
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
1.50 TYP.
16/17
¡ Semiconductor
MSM514100D/DL
(Unit : mm)
TSOPII26/20-P-300-1.27-K
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
0.38 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/17
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