MSM514102DL-70SJ [OKI]
4,194,304-Word X 1-Bit DYNAMIC RAM : STATIC COLUMN MODE TYPE; 4194304字X 1位动态RAM ：静态列模式类型
| 型号： | MSM514102DL-70SJ |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 4,194,304-Word X 1-Bit DYNAMIC RAM : STATIC COLUMN MODE TYPE |
| 文件： | 总18页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2G0149-29-41
This version: Apr. 1999
¡ Semiconductor
MSM514102D/DL
4,194,304-Word ¥ 1-Bit DYNAMIC RAM : STATIC COLUMN MODE TYPE
DESCRIPTION
The MSM514102D/DL is a 4,194,304-word ¥ 1-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM514102D/DL achieves high integration, high-speed operation, and
low-powerconsumptionbecauseOkimanufacturesthedeviceinaquadruple-layerpolysilicon/
single-layer metal CMOS process. The MSM514102D/DL is available in a 26/20-pin plastic SOJ, 20-
pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514102DL (the low-power version) is specially
designed for lower-power applications.
FEATURES
• 4,194,304-word ¥ 1-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
• Static Column mode, read modify write capability
• CS before RAS refresh, hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Package options:
26/20-pin 300 mil plastic SOJ
20-pin 400 mil plastic ZIP
(SOJ26/20-P-300-1.27)
(ZIP20-P-400-1.27)
(Product : MSM514102D/DL-xxSJ)
(Product : MSM514102D/DL-xxZS)
26/20-pin 300 mil plastic TSOP
(TSOPII26/20-P-300-1.27-K) (Product : MSM514102D/DL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Cycle Time
(Min.)
Power Dissipation
Family
tRAC
60 ns
70 ns
80 ns
tAA
tCAC
15 ns
20 ns
20 ns
Standby (Max.)
Operating (Max.)
30 ns
35 ns
40 ns
MSM514102D/DL-60
MSM514102D/DL-70
MSM514102D/DL-80
110 ns
130 ns
150 ns
495 mW
440 mW
385 mW
5.5 mW/
1.1 mW (L-version)
1/17
¡ Semiconductor
MSM514102D/DL
PIN CONFIGURATION (TOP VIEW)
A9 1
DIN
1
26 VSS
25 DOUT
24 CS
23 NC
22 A9
DIN
1
26 VSS
25 DOUT
24 CS
23 NC
22 A9
2
4
6
8
CS
DOUT
DIN
3
5
WE 2
RAS 3
NC 4
WE 2
RAS 3
NC 4
VSS
WE
A10
RAS 7
NC 9
A0 11
A2 13
VCC 15
A5 17
A7 19
A10 5
A10 5
10 NC
12 A1
14 A3
16 A4
18 A6
20 A8
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
26/20-Pin Plastic SOJ
20-Pin Plastic ZIP
26/20-Pin Plastic TSOP
(K Type)
Pin Name
Function
A0 - A10
RAS
CS
Address Input
Row Address Strobe
Chip Select Input
Data Input
DIN
DOUT
WE
Data Output
Write Enable
VCC
Power Supply (5 V)
Ground (0 V)
VSS
NC
No Connection
2/17
¡ Semiconductor
MSM514102D/DL
BLOCK DIAGRAM
Timing
Generator
RAS
CS
Timing
Generator
Write
Column
Address
Buffers
WE
Column
Decoders
Clock
11
11
Generator
Internal
Address
Counter
I/O
Selector
Refresh
Control Clock
Sense
Amplifiers
Output
Buffer
DOUT
A0 - A10
Row
Address
Buffers
Row
De-
Word
Drivers
Memory
Cells
11
11
Input
Buffer
DIN
coders
VCC
On Chip
Generator
V
BB
VSS
3/17
¡ Semiconductor
MSM514102D/DL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VT
Rating
–1.0 to 7.0
50
Unit
V
IOS
mA
W
PD
*
1
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Symbol
VCC
Min.
4.5
0
Typ.
5.0
0
Max.
Unit
5.5
0
V
V
V
V
VSS
Input High Voltage
Input Low Voltage
VIH
2.4
–1.0
—
6.5
0.8
VIL
—
Capacitance
(VCC = 5 V 10ꢀ, Ta = 25°C, f = 1 MHꢁ)
Parameter
Symbol
CIN1
Typ.
Max.
Unit
pF
Input Capacitance (A0 - A10, DIN)
—
—
—
6
7
7
Input Capacitance (RAS, CS, WE)
CIN2
pF
Output Capacitance (DOUT
)
COUT
pF
4/17
¡ Semiconductor
MSM514102D/DL
DC Characteristics
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C)
MSM514102 MSM514102 MSM514102
D/DL-60 D/DL-70 D/DL-80
Parameter
Symbol
Condition
Unit Note
Min. Max. Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
VOH IOH = –5.0 mA
VOL IOL = 4.2 mA
0 V £ VI £ 6.5 V;
ILI All other pins not
under test = 0 V
2.4
0
VCC
0.4
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
Input Leakage Current
–10
–10
—
10
10
90
–10
–10
—
10
10
80
–10
–10
—
10
10
70
mA
DOUT disable
Output Leakage Current ILO
Average Power
mA
0 V £ VO £ 5.5 V
RAS, CS cycling,
Supply Current
(Operating)
ICC1
mA 1, 2
tRC = Min.
RAS, CS = VIH
—
—
—
2
1
—
—
—
2
1
—
—
—
2
1
Power Supply
mA
1
ICC2 RAS, CS
≥ VCC –0.2 V
RAS cycling,
ICC3 CS = VIH,
Current (Standby)
200
200
200 mA 1, 5
Average Power
Supply Current
—
—
—
—
—
90
5
—
—
—
—
—
80
5
—
—
—
—
—
70
5
mA 1, 2
(RAS-only Refresh)
tRC = Min.
RAS = VIH,
Power Supply
ICC5 CS = VIL,
DOUT = enable
mA
1
Current (Standby)
Average Power
RAS cycling,
ICC6
Supply Current
90
80
300
80
70
300
70
60
mA 1, 2
CS before RAS
(CS before RAS Refresh)
Average Power
RAS = VIL,
ICC9 Address cycling,
tSC = Min.
Supply Current
mA 1, 3
1, 4,
(Static Column Mode)
Average Power
tRC = 125 ms,
ICC10
300 mA
Supply Current
CS before RAS,
tRAS £ 1 ms
5
(Battery Backup)
Notes : 1. I Max. is specified as I for output open condition.
CC
CC
2. The address can be changed once or less while RAS = V .
IL
3. The address can be changed once or less while CS = V
4. V – 0.2 V £ V £ 6.5 V, –1.0 V £ V £ 0.2 V.
.
IH
CC
IH
IL
5. L-version.
5/17
¡ Semiconductor
MSM514102D/DL
AC Characteristics (1/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13
MSM514102 MSM514102 MSM514102
D/DL-60
D/DL-70
D/DL-80
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Static Column Mode Cycle Time
Static Column Mode Read Modify Write
Cycle Time
tRC
tRWC
tSC
110
130
35
—
—
—
130
155
40
—
—
—
150
175
45
—
—
—
ns
ns
ns
tSRWC
60
—
70
—
80
—
ns
Access Time from RAS
tRAC
tCAC
tAA
—
—
—
—
—
0
60
15
30
55
15
—
—
—
—
—
—
0
70
20
35
65
20
—
—
—
—
—
—
0
80
20
40
75
20
—
ns 4, 5, 6
Access Time from CS
ns
4, 5
Access Time from Column Address
Access Time from Last Write
Output Enable Time referenced to WE
Output Low Impedance Time from CS
Data Output Hold Time referenced to
Column Address
ns 4, 6, 7
tALW
tOW
tCLZ
ns
ns
ns
4, 7
4
4
tAOH
5
—
5
—
5
—
ns
Data Output Hold Time from WE
tWOH
0
—
15
0
—
20
0
—
20
ns
ns
CS to Data Output Buffer Turn-off Delay Time tOFF
0
0
0
8
3
Transition Time
tT
3
50
3
50
3
50
ns
Refresh Period
tREF
tREF
tRP
—
—
40
60
60
15
10
15
60
5
16
—
—
50
70
70
20
10
20
70
5
16
—
—
60
80
80
20
10
20
80
5
16
ms
ms
ns
Refresh Period (L-version)
RAS Precharge Time
RAS Pulse Width
128
—
128
—
128
—
tRAS
tRASC
tRSH
10,000
100,000
—
10,000
100,000
—
10,000 ns
100,000 ns
RAS Pulse Width (Static Column Mode)
RAS Hold Time
—
—
ns
ns
CS Precharge Time (Static Column Mode) tCP
—
—
CS Pulse Width
tCS
10,000
—
10,000
—
10,000 ns
CS Hold Time
tCSH
tCRP
tRCD
tRAD
tASR
tRAH
tASC
tCAH
—
—
60
40
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
CS to RAS Precharge Time
RAS to CS Delay Time
—
—
20
15
0
45
20
15
0
50
20
15
0
5
6
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
Column Address Hold Time from RAS
(Write Cycle)
30
35
—
—
10
0
—
10
0
—
10
0
—
—
15
—
15
—
15
tAWR
50
—
55
—
60
—
ns
Column Address Hold Time from RAS
Column Address to RAS Lead Time
Column Address Hold Time from RAS
Precharge
tAR
75
30
—
—
85
35
—
—
95
40
—
—
ns
ns
tRAL
tAH
10
—
10
—
10
—
ns
6/17
¡ Semiconductor
MSM514102D/DL
AC Characteristics (2/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13
MSM514102 MSM514102 MSM514102
D/DL-60
D/DL-70
D/DL-80
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Column Address Hold Time
tAHLW
55
20
0
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
65
20
0
—
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
75
20
0
—
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
Last Write to Column Address Delay Time tLWAD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
Read Command Set-up Time
Read Command Hold Time
tRCS
tRCH
0
0
0
9
9
Read Command Hold Time referenced to RAS tRRH
0
0
0
Write Command Set-up Time
Write Command Hold Time
Write Command Hold Time from RAS
Write Command Pulse Width
Write Invalid Time
tWCS
tWCH
tWCR
tWP
0
0
0
10
10
45
10
10
0
10
50
10
10
0
15
60
15
10
0
tWI
Write Command Hold Time (DOUT Disable) tWH
10
Write Command to RAS Lead Time
Write Command to CS Lead Time
Data-in Set-up Time
tRWL
tCWL
tDS
15
15
0
20
20
0
20
20
0
11
11
Data-in Hold Time
tDH
15
50
15
30
60
10
5
15
55
20
35
70
10
5
15
60
20
40
80
10
5
Data-in Hold Time from RAS
CS to WE Delay Time
tDHR
tCWD
tAWD
tRWD
10
10
10
Column Address to WE Delay Time
RAS to WE Delay Time
CS Active Delay Time from RAS Precharge tRPC
RAS to CS Set-up Time (CS before RAS)
RAS to CS Hold Time (CS before RAS)
tCSR
tCHR
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
WE to RAS Precharge Time (CS before RAS) tWRP
WE Hold Time from RAS (CS before RAS) tWRH
RAS to WE Set-up Time (Test Mode)
RAS to WE Hold Time (Test Mode)
tWTS
tWTH
7/17
¡ Semiconductor
MSM514102D/DL
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of
eightinitializationcycles(RAS-onlyrefreshorCSbeforeRASrefresh)beforeproper
device operation is achieved.
2. The AC characteristics assume t = 5 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.
IH
IL
Transition times (t ) are measured between V and V .
T
IH
IL
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t (Max.) limit ensures that t (Max.) can be met.
RCD
RAC
t
t
(Max.)isspecifiedasareferencepointonly. Ift
(Max.) limit, then the access time is controlled by t
isgreaterthanthespecified
RCD
RCD
RCD
.
CAC
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RAD
RAC
t
t
(Max.)isspecifiedasareferencepointonly. Ift
(Max.) limit, then the access time is controlled by t
isgreaterthanthespecified
RAD
RAD
RAD
.
AA
7. Operating within the t
(Max.) limit ensures that t
(Max.) can be met.
LWAD
ALW
t
(Max.) is specified as a reference point only. If t
is greater than the
LWAD
LWAD
specified t
(Max.) limit, then the access time is controlled by t
.
LWAD
AA
8. tOFF (Max.)definesthetimeatwhichtheoutputachievestheopencircuitconditionand
is not referenced to output voltage levels.
9. t
or t
must be satisfied for a read cycle.
RCH
RRH
10. t
, t
, t
and t
are not restrictive operating parameters. They are
WCS CWD RWD
AWD
included in the data sheet as electrical characteristics only. If t
≥ t
(Min.), then
WCS WCS
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t ≥ t (Min.) , t ≥ t (Min.)
CWD CWD
RWD
RWD
andt
≥t
(Min.), thenthecycleisareadmodifywritecycleanddataoutwill
AWD AWD
contain data read from the selected cell; if neither of the above sets of conditions is
satisfied, then the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to the CS leading edge in an early write cycle, and
to the WE leading edge in a read modify write cycle.
12. ThetestmodeisinitiatedbyperformingaWEandCSbeforeRASrefreshcycle. This
mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. RA10,
CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data
output pin will indicate a high level. If any internal bits are not equal, the data
output pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a RAS-only refresh cycle or a CS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specifiedvalue.Theseparametersshouldbespecifiedintestmodecyclebyaddingthe
above value to the specified value in this data sheet.
8/17
E2G0150-18-41U
¡ Semiconductor
MSM514102D/DL
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
tCSH
VIH
VIL
–
–
RAS
tCRP
tCRP
tRCD
tRAD
tRSH
tCS
VIH
VIL
–
–
CS
tAH
tRAL
Column
tRAH
Row
tASR
VIH
VIL
–
–
Address
tAR
tRCH
tRRH
tRCS
VIH
VIL
–
–
tCAC
WE
tAA
tOFF
tRAC
VOH
VOL
–
–
DOUT
Valid Data
Open
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
tAWR
tCSH
tCRP
tCRP
tRSH
tCS
VIH
VIL
–
–
CS
tRCD
tASR
tRAH
Row
VIH
VIL
–
–
Address
Column
tCAH
tWCR
tRAD
tASC
tWH
tWCS
tWP
VIH
VIL
–
–
WE
tDS
tDH
VIH
VIL
–
–
DIN
Valid Data
tDHR
VOH
VOL
–
–
DOUT
Open
"H" or "L"
9/17
¡ Semiconductor
MSM514102D/DL
Read Modify Write Cycle
tRWC
tRP
tRAS
VIH
VIL
–
–
RAS
CS
tRCD
tRAD
tCRP
tCRP
tRAL
tCS
VIH
VIL
–
–
tRCS
tCWD
tAWD
tCWL
tRWL
tCAH
tRAH
Row
tASR
VIH
VIL
–
–
Address
Column
tRWD
tWP
VIH
VIL
–
–
WE
tCSH
tDH
tDS
Valid Data
tCAC
VIH
VIL
–
–
DIN
tWOH
tOFF
"H" or "L"
tRP
tAA
tRAC
VOH
VOL
–
–
DOUT
Valid Data
Open
tCLZ
Static Column Mode Read Cycle
tRASC
VIH
VIL
–
–
RAS
CS
tCRP
tCP
tRSH
tCS
tCS
VIH
VIL
–
–
tRCD
tAH
tRAH
Row
tASR
tSC
Column
tAR
tSC
tRAL
VIH
VIL
–
–
Column
Column
tRRH
Address
tRAD
tRCS
tRCH
tRCH
tRCS
tCSH
VIH
VIL
–
–
tAA
tCAC
tAA
tAOH
tOFF
WE
tAA
tCAC
tOFF
tRAC
VOH
VOL
–
–
Valid
Data
Valid
Data
Valid
Data
DOUT
tCLZ
tCLZ
"H" or "L"
10/17
¡ Semiconductor
MSM514102D/DL
Static Column Mode Write Cycle (Early Write)
tRP
tRASC
VIH
VIL
–
–
RAS
CS
tRSH
tCP
tRAD
tRCD
tCRP
tASC
VIH
VIL
–
–
tRAL
tASR
tRAH
Row
tCAH
VIH
VIL
–
–
Address
Column
tAWR
tWCS
Column
tCAH
tCWL
tWP
Column
tASC tCAH
tASC
tWCH
tWH
tWCS
VIH
VIL
–
–
WE
tWI
tSC
tDS
tDS
tDH
tDH
Valid Data
tDS
tDH
Valid
VIH
VIL
–
–
DIN
Valid Data
Data
tDHR
VOH
VOL
–
–
DOUT
Open
"H" or "L"
Static Column Mode Read Modify Write Cycle
tRASC
tRP
VIH
VIL
–
–
RAS
CS
tCRP
tCWD
tAWD
tRCS
VIH
VIL
–
–
tCWL
tRWL
tLWAD
tRAL
tRAH
Row
tASR
tCAH
VIH
VIL
–
–
Address
Column
Column
tRAD
tRWD
tSRWC
tWP
tAWD
VIH
VIL
–
–
WE
tDS
tDH
Valid
tRCD
VIH
VIL
–
–
Valid
Data
DIN
Data
tWOH
tALW
tAA
tCAC
tAA
tOW
tOFF
tRAC
VOH
VOL
–
–
DOUT
Valid Data
Valid Data
tCLZ
"H" or "L"
11/17
¡ Semiconductor
MSM514102D/DL
Static Column Mode Read/Write Mixed Cycle
VIH
VIL
–
–
RAS
tRCD
tASC
tCP
VIH
VIL
–
–
tCS
tRAD
tRAH
CS
tASR
Row
VIH
VIL
–
–
Address
Column
tAWR
Column
tSC
Column
tCAH
tWCR
tWCS
tAWD
tWP
tDH
VIH
VIL
–
–
WE
tLWAD
tDH
tDS
tDS
VIH
VIL
–
–
Valid
Valid Data
tDHR
DIN
Invalid Data
tCAC
Data
tWOH
tAOH
tAA
tAA
VOH
VOL
–
–
Valid
Data
Valid
Data
DOUT
tALW
(Read/Write)
(Read)
"H" or "L"
RAS-Only Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
tRPC
tCRP
VIH
VIL
–
–
CS
tASR
Row
tOFF
tRAH
VIH
VIL
–
–
Address
VOH
VOL
–
–
DOUT
Open
Note: WE = "H" or "L"
"H" or "L"
12/17
¡ Semiconductor
MSM514102D/DL
CS before RAS Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
tRPC
tRPC
tCSR
tCP
tCSR
tCHR
VIH
VIL
–
–
CS
tWRP
tWRH
tWRP
VIH
VIL
–
–
WE
tOFF
VOH
VOL
–
–
DOUT
Open
Note : Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRP
tRAS
VIH
VIL
–
–
RAS
CS
tRCD
tRSH
tAR
tCHR
tCRP
tCRP
VIH
VIL
–
–
tRAH
tRAD
tASR
tAH
tRAL
VIH
VIL
–
–
Address
Row
Column
tWRP
tRRH
tRCS
tWRH
VIH
VIL
–
–
tCAC
WE
tAA
tOFF
tRAC
VOH
VOL
–
–
DOUT
Valid Data
tCLZ
"H" or "L"
13/17
¡ Semiconductor
MSM514102D/DL
Hidden Refresh Write Cycle
tRC
tRC
tRAS
tRP
tRP
tRAS
VIH
VIL
–
–
tAR
tRCD
RAS
CS
tRSH
tCRP
tCHR
tCRP
VIH
VIL
–
–
tRAH
tASR
tASC
tRAD
tCAH
VIH
VIL
–
–
Row
Column
tWCS
Address
tWH
tWRP
tWRH
VIH
VIL
–
–
WE
tDS
tDH
VIH
VIL
–
–
Valid Data
tDHR
DIN
VOH
VOL
–
–
Open
DOUT
"H" or "L"
Test Mode Initiate Cycle
tRC
tRAS
tRP
VIH
VIL
–
–
RAS
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
CS
tWTS
tWTH
VIH
VIL
–
–
WE
tOFF
VOH
VOL
–
–
DOUT
Open
Note: Address, DIN = "H" or "L"
"H" or "L"
14/17
¡ Semiconductor
PACKAGE DIMENSIONS
SOJ26/20-P-300-1.27
MSM514102D/DL
(Unit : mm)
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
15/17
¡ Semiconductor
MSM514102D/DL
(Unit : mm)
ZIP20-P-400-1.27
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
1.50 TYP.
16/17
¡ Semiconductor
MSM514102D/DL
(Unit : mm)
TSOPII26/20-P-300-1.27-K
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
0.38 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
17/17
E2Y0002-29-11
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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