MSM514222B-30RS [OKI]
Memory Circuit, 256KX4, CMOS, PDIP16, 0.300 INCH, 2.54 MM PITCH, PLASTIC, DIP-16;
| 型号： | MSM514222B-30RS |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Memory Circuit, 256KX4, CMOS, PDIP16, 0.300 INCH, 2.54 MM PITCH, PLASTIC, DIP-16 光电二极管 |
| 文件： | 总15页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2L0030-17-Y1
This version: Jan. 1998
Previous version: Dec. 1996
¡ Semiconductor
MSM514222B
262,263-Word ¥ 4-Bit Field Memory
DESCRIRTION
The OKI MSM514222B is a high performance 1-Mbit, 256K ¥ 4-bit, Field Memory. It is designed
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital
movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity
TVs and VTRs, exclusively. The MSM514222B is not designed for the other use or high end use
in medical systems, professional graphics systems which require long term picture, and data
storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen
and cascaded directly without any delay devices among the MSM514222B. (Cascading of
MSM514222B provides larger storage depth or a longer delay).
Each of the 4-bit planes has separate serial write and read ports. These employ independent
control clocks to support asynchronous read and write operations. Different clock rates are also
supported that allow alternate data rates between write and read data streams.
The MSM514222B provides high speed FIFO, First-In First-Out, operation without external
refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the
users.
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial
access operation, so that the serial read and/or write control clock can be halted high or low for
any duration as long as the power is on. Internal conflicts of memory access and refreshing
operations are prevented by special arbitration logic.
The MSM514222B's function is simple, and similar to a digital delay device whose delay-bit-
length is easily set by reset timing. The delay length, number of read delay clocks between write
and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 4-bit enable high
speed first-bit-access with no clock delay just after the write or read reset timings.
The MSM514222B is similar in operation and functionality to OKI 2-Mbit Field Memory
MSM518222.
1/15
¡ Semiconductor
MSM514222B
FEATURES
• Single power supply: 5 V ±10%
• 512 Rows ¥ 512 Column ¥ 4 bits
• Fast FIFO (First-in First-out) operation
• High speed asynchronous serial access
Read/Write cycle time
Access time
30 ns/40 ns/60 ns
25 ns/30 ns/50 ns
• Functional compatibility with OKI MSM518222
• Self refresh (No refresh control is required)
• Package options:
16-pin 300 mil plastic DIP
(DIP16-P-300-2.54-W1) (Product : MSM514222B-xxRS)
26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27)
(Product : MSM514222B-xxJS)
20-pin 400 mil plastic ZIP
(ZIP20-P-400-1.27)
(Product : MSM514222B-xxZS)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
Cycle Time (Min.)
Package
MSM514222B-30RS
MSM514222B-40RS
MSM514222B-60RS
MSM514222B-30JS
MSM514222B-40JS
MSM514222B-60JS
MSM514222B-30ZS
MSM514222B-40ZS
MSM514222B-60ZS
25 ns
30 ns
50 ns
25 ns
30 ns
50 ns
25 ns
30 ns
50 ns
30 ns
40 ns
60 ns
30 ns
40 ns
60 ns
30 ns
40 ns
60 ns
300 mil 16-pin DIP
300 mil 26/20-pin SOJ
400 mil 20-pin ZIP
2/15
¡ Semiconductor
MSM514222B
PIN CONFIGURATION (TOP VIEW)
WE 1
RSTW 2
SWCK 3
DIN0 4
DIN1 5
DIN2 6
DIN3 7
16 VCC
WE 1
RSTW 2
SWCK 3
DIN0 4
NC 5
26 VCC
25 RE
SRCK
RE
1
3
5
7
9
2
4
6
8
RSTR
VCC
15 RE
24 RSTR
23 SRCK
22 NC
WE
14 RSTR
13 SRCK
RSTW
DIN0
SWCK
NC
NC 9
DIN1 10
DIN2 11
DIN3 12
VSS 13
18 NC
NO LEAD
12 NC
12 DOUT
11 DOUT
10 DOUT
9 DOUT
0
17 DOUT
16 DOUT
15 DOUT
0
NC 11
DIN1 13
DIN3 15
OUT3 17
1
2
1
2
3
14 DIN2
16 VSS
14 DOUT3
D
VSS
8
18 DOUT
2
26/20-Pin Plastic SOJ
DOUT1 19
20 DOUT0
16-Pin Plastic DIP
20-Pin Plastic ZIP
Pin Name
SWCK
SRCK
WE
Function
Serial Write Clock
Serial Read Clock
Write Enable
RE
Read Enable
RSTW
RSTR
DIN0 - 3
DOUT0 - 3
VCC
Write Reset Clock
Read Reset Clock
Data Input
Data Output
Power Supply (5 V)
Ground (0 V)
VSS
NC
No Connection
3/15
¡ Semiconductor
MSM514222B
BLOCK DIAGRAM
DOUT (¥ 4)
RE
RSTR
SRCK
Data-Out
Buffer (¥ 4)
Serial
Read
Controller
512 Word Serial Read Register (¥ 4)
Read Line Buffer Read Line Buffer
Low-Half (¥ 4)
High-Half (¥ 4)
256 (¥ 4)
256 (¥ 4)
120 Word
Sub-Register (¥ 4)
256K (¥ 4)
Memory
Array
Read/Write
and Refresh
Controller
X
Decoder
120 Word
Sub-Register (¥ 4)
Clock
Oscillator
256 (¥ 4)
256 (¥ 4)
Write Line Buffer Write Line Buffer
Low-Half (¥ 4) High-Half (¥ 4)
512 Word Serial Write Register (¥ 4)
VBB
Generator
Data-In
Buffer (¥ 4)
Serial
Write
Controller
DIN (¥ 4)
WE
RSTW SWCK
4/15
¡ Semiconductor
MSM514222B
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset
operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 130 active write cycles, i.e.
SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time
is stored in the serial data registers attached to the DRAM array, an RSTW operation is required
after the last SWCK cycle.
Write Reset : RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters
tozero. RSTWsetupandholdtimesarereferencedtotherisingedgeofSWCK. Becausethewrite
resetfunctionissolelycontrolledbytheSWCKrisingedgeafterthehighlevelofRSTW,thestates
of WE are ignored in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Data Inputs : D 0 - 3
IN
Write Clock : SWCK
TheSWCKlatchestheinputdataonchipwhenWEishigh, andalsoincrementstheinternalwrite
address pointer. Data-in setup time t , and hold time t
are referenced to the rising edge of
DS
DH
SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low
level disables the input and holds the internal write address pointer. There are no WE disable
time (low) and WE enable time (high) restrictions, because the MSM514222B is in fully static
operation as long as the power is on. Note that WE setup and hold times are referenced to the
rising edge of SWCK.
5/15
¡ Semiconductor
MSM514222B
Read Operation
The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is
accomplished by cycling SRCK, and holding RE high after the read address pointer reset
operation or RSTR.
Each read operation, which begins after RSTR, must contain at least 130 active read cycles, i.e.
SRCK cycles while RE is high.
Read Reset : RSTR
The first positive transition of SRCK after RSTR becomes high resets the read address counters
to zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Because the read
reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states
of RE are ignored in the read reset cycle.
Before RSTR may be brought high again for a further reset operation, it must be low for at least
two SRCK cycles.
Data Out : D
0 - 3
OUT
Read Clock : SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high
during a read operation. The SRCK input increments the internal read address pointer when RE
is high.
The three-state output buffer provides direct TTL compatibility ( no pullup resistor required).
Data out is the same polarity as data in. The output becomes valid after the access time interval
t
AC
that begins with the rising edge of SRCK. There are no output valid time restriction on
MSM514222B.
Read Enable : RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is
high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read
pointer is not incremented. RE setup times (t
and t
) and RE hold times (t and
RENS
RDSS
RENH
t
) are referenced to the rising edge of the SRCK clock.
RDSH
6/15
¡ Semiconductor
MSM514222B
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100 ms after V has
CC
stabilized to a value within the range of recommended operating conditions. After this 100 ms
stabilization interval, the following initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 130
dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed,
followed by an RSTW operation and an RSTR operation, to properly initialize the write and the
read address pointer. Dummy write cycles/RSTW and dummy read cycles/RSTR may occur
simultaneously.
If these dummy read and write operations start while V and/or the substrate voltage has not
CC
stabilized, it isnecessarytoperformanRSTRoperationplusaminimumof130SRCKcyclesplus
another RSTR operation, and an RSTW operation plus a minimum of 130 SRCK cycles plus
another RSTW operation to properly initialize read and write address pointers.
Old/New Data Access
There must be a minimum delay of 600 SWCK cycles between writing into memory and reading
out from memory. If reading from the first field starts with an RSTR operation, before the start
of writing the second field (before the next RSTW operation), then the data just written will be
read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the
second field of data for as many as 119 SWCK cycles. If the RSTR operation for the first field read-
outoccurslessthan119SWCKcyclesaftertheRSTWoperationforthesecondfieldwrite-in, then
the internal buffering of the device assures that the first field will still be read out. The first field
of data that is read out while the second field of data is written is called “old data”.
In order to read out “new data”, i.e., the second field written in, the delay between an RSTW
operation and an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW
and RSTR operations is more than 120 but less than 600 cycles, then the data read out will be
undetermined. It may be “old data” or “new” data, or a combination of old and new data. Such
a timing should be avoided.
Cascade Operation
The MSM514222B is designed to allow easy cascading of multiple memory devices. This
provides higher storage depth, or a longer delay than can be achieved with only one memory
device.
7/15
¡ Semiconductor
MSM514222B
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Input Output Voltage
Output Current
Symbol
VT
Condition
at Ta = 25°C, VSS
Ta = 25°C
Ta = 25°C
—
Rating
–1.0 to 7.0
50
Unit
V
IOS
mA
W
Power Dissipation
Operating Temperature
Storage Temperature
PD
1
Topr
Tstg
0 to 70
–55 to 150
°C
—
°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VCC
Min.
Typ.
5.0
0
Max.
5.5
Unit
4.5
0
V
V
V
V
VSS
0
VIH
2.4
–1.0
VCC
0
VCC + 1
0.8
VIL
DC Characteristics
Parameter
Symbol
ILI
Condition
Min.
Max.
Unit
mA
mA
V
Input Leakage Current
Output Leakage Current
Output "H" Level Voltage
Output "L" Level Voltage
0 < VI < VCC + 1, Other Pins Tested at V = 0 V
–10
–10
2.4
—
10
10
—
0.4
50
45
35
10
ILO
0 < VO < VCC
IOH = –5 mA
IOL = 4.2 mA
-30
VOH
VOL
V
—
Minimum Cycle Time, Output Open
-40
-60
Operating Current
ICC1
ICC2
—
mA
mA
—
Standby Current
Input Pin = VIH / VIL
—
Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance (DIN, SWCK, SRCK, RSTW, RSTR, WE, RE)
Output Capacitance (DOUT
Symbol
Max.
Unit
pF
CI
7
7
)
CO
pF
8/15
¡ Semiconductor
MSM514222B
AC Characteristics
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C)
MSM514222B-30 MSM514222B-40 MSM514222B-60
Unit
Parameter
Symbol
Min.
—
6
Max.
25
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
Min.
—
6
Max.
30
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
Min.
—
6
Max.
50
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
Access Time from SRCK
tAC
tDDCK
tDECK
tDDRE
tWSWH
tWSWL
tDS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
D
D
OUT Hold Time from SRCK
OUT Enable Time from SRCK
OUT Hold Time from RE
6
6
6
9
9
9
SWCK "H" Pulse Width
SWCK "L" Pulse Width
Input Data Setup Time
Input Data Hold Time
WE Enable Setup Time
WE Enable Hold Time
WE Disable Setup Time
WE Disable Hold Time
WE "H" Pulse Width
WE "L" Pulse Width
RSTW Setup Time
12
12
5
17
17
5
17
17
5
tDH
6
6
6
tWENS
tWENH
tWDSS
tWDSH
tWWEH
tWWEL
tRSTWS
tRSTWH
tWSRH
tWSRL
tRENS
tRENH
tRDSS
tRDSH
tWREH
tWREL
tRSTRS
tRSTRH
tSWC
0
0
0
5
5
5
0
0
0
5
5
5
5
10
10
0
10
10
0
5
0
RSTW Hold Time
10
12
12
0
10
17
17
0
10
17
17
0
SRCK "H" Pulse Width
SRCK "L" Pulse Width
RE Enable Setup Time
RE Enable Hold Time
RE Disable Setup Time
RE Disable Hold Time
RE "H" Pulse Width
RE "L" Pulse Width
5
5
5
0
0
0
5
5
5
5
10
10
0
10
10
0
5
RSTR Setup Time
0
RSTR Hold Time
10
30
30
3
10
40
40
3
10
60
60
3
SWCK Cycle Time
SRCK Cycle Time
tSRC
Transition Time (Rise and Fall)
tT
9/15
¡ Semiconductor
MSM514222B
Notes: 1. Input signal reference levels for the parameter measurement are V = 2.4 V and V
IH
IL
= 0.8 V. The transition time t is defined to be a transition time that signal transfers
T
between V = 2.4 V and V = 0.8 V.
IH
IL
2. AC measurements assume t = 3 ns.
T
3. Read address must have more than a 600 address delay than write address in every
cycle when asynchronous read/write is performed.
4. Read must have more than a 600 address delay than write in order to read the data
written in a current series of write cycles which has been started at last write reset
cycle: this is called "new data read".
When read has less than a 119 address delay than write, the read data are the data
writteninapreviousseriesofwritecycleswhichhadbeenwrittenbeforeatlastwrite
reset cycle: this is called "old data read".
5. When the read address delay is between more than 120 and less than 599, read data
will be undetermined. However, normal write is achieved in this address condition.
6. Outputs are measured with a load equivalent to 2 TTL loads and 30 pF.
Output reference levels are V
= 2.4 V and V = 0.8 V.
OH
OL
10/15
¡ Semiconductor
MSM514222B
TIMING WAVEFORM
Write Cycle Timing (Write Reset)
2 Cycle
n Cycle
0 Cycle
1 Cycle
– VIH
– VIL
SWCK
RSTW
tWSWH tWSWL
tSWC
tRSTWH
tRSTWS
tT
– VIH
– VIL
tDH
n – 1
tDS
– VIH
– VIL
DIN
WE
n
0
1
2
– VIH
– VIL
Write Cycle Timing (Write Enable)
n Cycle
tWENH
Disable Cycle
Disable Cycle
n + 1 Cycle
– VIH
– VIL
SWCK
tWDSH
tWDSS
tWENS
– VIH
– VIL
WE
DIN
tWWEH
tWWEL
– VIH
– VIL
n – 1
n
n + 1
– VIH
– VIL
RSTW
11/15
¡ Semiconductor
MSM514222B
Read Cycle Timing (Read Reset)
2 Cycle
n Cycle
0 Cycle
1 Cycle
– VIH
– VIL
SRCK
RSTR
tWSRH tWSRL
tSRC
tRSTRH
tRSTRS
tT
– VIH
– VIL
tDDCK
tAC
– VOH
– VOL
DOUT
RE
n – 1
n
0
1
2
– VIH
– VIL
Read Cycle Timing (Read Enable)
n Cycle
tRENH
Disable Cycle
Disable Cycle
tRDSS
n + 1 Cycle
– VIH
– VIL
SRCK
tRDSH
tRENS
– VIH
– VIL
RE
tWREH
tWREL
tDDRE
tDECK
– VOH
– VOL
n – 1
n
Hi-Z
n + 1
DOUT
– VIH
– VIL
RSTR
12/15
¡ Semiconductor
PACKAGE DIMENSIONS
DIP16-P-300-2.54-W1
MSM514222B
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.00 TYP.
13/15
¡ Semiconductor
MSM514222B
(Unit : mm)
SOJ26/20-P-300-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
14/15
¡ Semiconductor
MSM514222B
(Unit : mm)
ZIP20-P-400-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.50 TYP.
15/15
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