MSM514265E [OKI]
262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO; 262,144字×16位动态RAM ：快速页模式输入与EDO
| 型号： | MSM514265E |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| 文件： | 总15页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Semiconductor
This version:Aug.2000
MSM514265E
262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM514265E is a 262,144-word ´ 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology.
The MSM514265E achieves high integration, high-speed operation, and low-power consumption because Oki
manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM514265E
is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP.
FEATURES
·
·
·
·
·
·
·
·
262,144-word ´ 16-bit configuration
Single 5V power supply, ±10% tolerance
Input
: TTL compatible, low input capacitance
Output
Refresh
: TTL compatible, 3-state
: 512 cycles/8ms
Fast page mode with EDO, read modify write capability
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
Package options:
40-pin 400mil plastic SOJ
(SOJ40-P-400-1.27)
(Product : MSM514265E-xxJS)
44/40-pin 400mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM514265E-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation
Cycle Time
(Min.)
Family
t
t
t
t
OEA
Operating (Max.) Standby (Max.)
RAC
AA
CAC
60ns
70ns
30ns
35ns
15ns
20ns
15ns
20ns
104ns
124ns
633mW
5.5mW
578mW
MSM514265E
MSM514265E
PIN CONFIGRATION (TOP VIEW)
VCC
1
40 VSS
VCC
1
44 VSS
DQ1 2
DQ2 3
DQ3 4
DQ4 5
39 DQ16
38 DQ15
37 DQ14
36 DQ13
35 VSS
DQ1 2
DQ2 3
DQ3 4
DQ4 5
43 DQ16
42 DQ15
41 DQ14
40 DQ13
39 VSS
VCC
6
VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
WE 13
RAS 14
NC 15
A0 16
34 DQ12
33 DQ11
32 DQ10
DQ5 7
DQ6 8
DQ7 9
DQ8 10
38 DQ12
37 DQ11
36 DQ10
35 DQ9
DQ9
31
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
NC 13
NC 14
WE 15
RAS 16
NC 17
A0 18
32 NC
31 LCAS
30 UCAS
29 OE
28 A8
25 A7
A1 17
24 A6
27 A7
A2 18
23 A5
A1 19
26 A6
A3 19
22 A4
A2 20
25 A5
VCC 20
21 VSS
A3 21
24 A4
VCC 22
23 VSS
40-Pin Plastic SOJ
44/40-Pin Plastic TSOP
(K Type)
Pin Name
A0 - A8
RAS
Function
Address Input
Row Address Strobe
Lower Byte Column Address Strobe
Upper Byte Column Address Strobe
Data Input/Data Output
Output Enable
LCAS
UCAS
DQ1–DQ16
OE
Write Enable
WE
VCC
Power Supply (5V)
VSS
Ground (0V)
NC
No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same
GND voltage level must be provided to every VSS pin.
MSM514265E
BLOCK DIAGRAM
WE
OE
Timing
Generator
RAS
I/O
Controller
LCAS
UCAS
Output
Buffers
8
8
8
I/O
Controller
DQ1～DQ8
Column
Address
Buffers
9
Input
Buffers
9
Column Decoders
Sense Amplifiers
8
I/O
Selector
Internal
Address
Counter
16
16
Refresh
Control Clock
A0～A8
Input
Buffers
8
8
8
8
Row
Address
Buffers
Row
Deco-
ders
9
9
DQ9～DQ16
Word
Drivers
Memory
Cells
Output
Buffers
VCC
On Chip
VBB Generator
VSS
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
DQ1-DQ8
High-Z
DQ9-DQ16
High-Z
RAS
H
L
LCAS
UCAS
WE
*
OE
*
*
H
L
H
L
L
H
L
L
*
H
H
L
L
H
L
L
L
Standby
Refresh
*
*
High-Z
High-Z
L
H
H
H
L
L
D
High-Z
Lower Byte Read
Upper Byte Read
Word Read
OUT
L
L
High-Z
D
OUT
L
L
D
D
OUT
OUT
L
H
H
H
H
D
Don’t Care
Lower Byte Write
Upper Byte Write
Word Write
IN
L
L
Don’t Care
D
IN
L
L
D
D
IN
IN
L
H
High-Z
High-Z
¾
* : “H” or “L”
MSM514265E
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Voltage VCC supply Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
- 0.5 to VCC + 0.5
- 0.5 to 7.0
50
Unit
V
V
IOS
mA
W
PD*
1
Topr
Operating Temperature
0 to 70
°C
°C
Tstg
Storage Temperature
- 55 to 150
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Symbol
VCC
VSS
Min.
4.5
Typ.
5.0
0
Max.
Unit
V
5.5
0
Power Supply Voltage
0
V
VCC + 0.5*1
Input High Voltage
Input Low Voltage
2.4
- 0.5*2
V
¾
VIH
0.8
V
¾
VIL
Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VCC is applied).
*2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to
the point at which VSS is applied).
Capacitance
(VCC = 5V ± 10%, Ta = 25°C, f=1MHz)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 – A8)
5
pF
¾
CIN1
Input Capacitance
7
7
pF
pF
¾
¾
CIN2
CI/O
(RAS, LCAS, UCAS, WE, OE)
Output Capacitance (DQ1 - DQ16)
MSM514265E
DC Characteristics
(VCC = 5V ± 10%, Ta = 0°C to 70°C)
MSM514265
E-60
MSM514265
E-70
Symbol
Parameter
Condition
Unit Note
Min. Max. Min. Max.
V
V
V
CC
I
I
= - 5.0mA
Output High Voltage
Output Low Voltage
2.4
0
2.4
0
V
V
OH
CC
OH
V
= 4.2mA
0.4
0.4
OL
OL
0V £ V £ 6.5V;
I
I
Input Leakage Current
Output Leakage Current
10
10
- 10
- 10
mA
LI
All other pins not
under test = 0V
DQ disable
I
LO
10
10
- 10
- 10
mA
0V £ V £ VCC
O
RAS, CAS cycling,
Average Power Supply Current
(Operating)
I
115
105
mA 1,2
¾
¾
CC1
t
= Min.
RC
RAS, CAS = V
RAS, CAS ³
2
1
2
1
¾
¾
¾
¾
IH
Power Supply Current
(Standby)
I
mA
1
CC2
V
CC
- 0.2V
RAS cycling,
Average Power Supply Current
I
CAS = V ,
115
105
mA 1,2
¾
¾
CC3
IH
(RAS-only Refresh)
t
= Min.
RC
RAS = V ,
IH
Power Supply Current
(Standby)
I
5
5
mA
1
¾
¾
¾
¾
¾
¾
CC5
CAS = V ,
IL
DQ = enable
Average Power Supply Current
RAS = cycling,
I
115
115
105
105
mA 1,2
mA 1,3
CC6
(CAS before RAS Refresh)
CAS before RAS
RAS = V ,
IL
Average Power Supply Current
(Fast Page Mode)
I
CC7
CAS cycling,
t
= Min.
HPC
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
MSM514265E
AC Characteristic (1/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3
MSM514265
E-60
MSM514265
E-70
Parameter
Symbol
Unit Note
Min.
104
135
25
68
¾
Max.
Min.
124
160
30
78
¾
Max.
¾
t
ns
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
¾
¾
RC
t
ns
¾
RWC
t
ns
¾
¾
HPC
t
ns
Fast Page Mode Read Modify Write Cycle Time
Access Time from RAS
¾
¾
HPRWC
t
60
15
30
35
15
¾
70
20
35
40
20
¾
ns 4, 5, 6
RAC
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
4,5
4,6
4,13
4
¾
¾
Access Time from CAS
CAC
t
Access Time from Column Address
Access Time from CAS Precharge
Access Time from OE
¾
¾
AA
t
¾
¾
CPA
t
¾
¾
OEA
t
0
0
4
Output Low Impedance Time from CAS
Data Output Hold After CAS Low
CAS to Data Output Buffer Turn-off Delay Time
RAS to Data Output Buffer Turn-off Delay Time
OE to Data Output Buffer Turn-off Delay Time
WE to Data Output Buffer Turn-off Delay Time
Transition Time
CLZ
t
5
5
¾
¾
DOH
t
0
15
15
15
15
50
8
0
20
20
20
20
50
8
7,8
7,8
7
CEZ
t
0
0
REZ
t
0
0
OEZ
t
0
0
7
WEZ
t
T
1
1
3
t
Refresh Period
¾
¾
REF
t
40
60
60
10
10
50
70
70
13
13
¾
¾
RAS Precharge Time
RP
t
10,000
100,000
¾
10,000 ns
100,000 ns
RAS Pulse Width
RAS
t
RAS Pulse Width (Fast Page Mode with EDO)
RAS Hold Time
RASP
t
ns
ns
¾
¾
RSH
t
¾
RAS Hold Time referenced to OE
ROH
CAS Precharge Time
(Fast Page Mode with EDO)
t
10
10
ns
15
¾
¾
CP
t
10
40
5
10,000
10
45
5
10,000 ns
CAS Pulse Width
CAS
t
ns
ns
ns
ns
ns
ns
ns
ns
¾
¾
¾
¾
CAS Hold Time
CSH
t
13
13
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
OE Hold Time from CAS (DQ Disable)
RAS to CAS Delay Time
CRP
t
35
5
40
5
¾
¾
RHCP
t
¾
¾
CHO
t
14
12
0
45
30
¾
14
12
0
50
35
¾
5
6
RCD
t
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
RAD
t
ASR
t
10
10
¾
¾
RAH
MSM514265E
AC Characteristic (2/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3
MSM514265
E-60
MSM514265
E-70
Parameter
Symbol
Unit Note
Min.
0
Max.
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Min.
0
Max.
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
t
ns
ns
ns
ns
ns
ns
12
12
Column Address Set-up Time
Column Address Hold Time
ASC
t
10
30
0
13
35
0
CAH
t
Column Address to RAS Lead Time
Read Command Set-up Time
Read Command Hold Time
RAL
t
12
9,12
9
RCS
t
0
0
RCH
t
0
0
Read Command Hold Time referenced to RAS
Write Command Set-up Time
Write Command Hold Time
RRH
t
0
0
ns 10,12
WCS
t
10
10
7
13
10
7
ns
ns
ns
ns
ns
ns
ns
ns
12
WCH
t
Write Command Pulse Width
WE Pulse Width (DQ Disable)
OE Command Hold Time
WP
t
WPE
t
10
10
10
10
10
0
13
10
10
13
13
0
OEH
t
OE Precharge Time
OEP
t
OE Command Hold Time
OCH
t
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
RWL
t
14
CWL
t
ns 11,12
ns 11,12
ns
DS
t
10
15
35
50
80
55
5
13
20
45
60
95
65
5
Data-in Hold Time
DH
t
OE to Data-in Delay Time
OED
t
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
12
12
13
CAS to WE Delay Time
CWD
t
Column Address to WE Delay Time
RAS to WE Delay Time
AWD
t
RWD
t
CAS Precharge WE Delay Time
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS)
RAS to CAS Hold Time (CAS before RAS)
CPWD
t
RPC
t
5
5
CSR
t
10
10
CHR
MSM514265E
Notes: 1. A start-up delay of 200ms is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume t = 2ns.
T
3.
V
(Min.) and V (Max.) are reference levels for measuring input timing signals. Transition times
IH IL
(t ) are measured between VIH and VIL.
T
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF.
The output timing reference levels are V = 2.0V (I = - 2mA) and V = 0.8V (I = 2mA).
OH
OH
OL
OH
5. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RCD
RAC
t
(Max.) is specified as a reference point only. If t
is greater than the specified t
(Max.)
(Max.)
RCD
RCD
RCD
RAD
limit, then the access time is controlled by t
.
CAC
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
is greater than the specified t
RAD
RAC
RAD
t
(Max.) is specified as a reference point only. If t
RAD
limit, then the access time is controlled by t
.
AA
7.
t
(Max.), t
(Max.), t
(Max.), and t
(Max.) define the time at which the output
OEZ
CEZ
REZ
WEZ
achieved the open circuit condition and are not referenced to output voltage levels.
8.
9.
t
CEZ
, and t must be satisfied for open circuit condition.
REZ
t
or t
must be satisfied for a read cycle.
RRH
RCH
10. t
, t
, t
, t
and t
are not restrictive operating parameters. They are included in
CPWD
WCS CWD RWD AWD
the data sheet as electrical characteristics only. If t
³ t
(Min.), then the cycle is an early
WCS
WCS
write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle.
If t ³ t (Min.), t ³ t (Min.), t ³ t (Min.) and t ³ t (Min.), then
CWD
CWD
RWD
RWD
AWD
AWD
CPWD
CPWD
the cycle is a read modify write cycle and data out will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, then the condition of the data out (at access time)
is indeterminate.
11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle,
and to the WE leading edge in an OE control write cycle, or a read modify write cycle.
12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is
earlier.
13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.
14. t
should be satisfied by both UCAS and LCAS.
CWL
15. t is determined by the time both UCAS and LCAS are high.
CP
MSM514265E
Timing Chart
·
Read Cycle
tRC
tRAS
VIH
RAS
tRP
tCRP
VIL
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
VIL
tRAL
tASR tRAH
tASC
tCAH
VIH
Address
VIL
Row
Column
tRCS
tRRH
tRCH
VIH
WE
tAA
VIL
tROH
tREZ
tAOE
tCAC
VIH
OE
VIL
tCEZ
tRAC
tOEZ
tCLZ
VOH
DQ
Valid Data-out
Open
VOL
“H” or “L”
·
Write Cycle (Early Write)
tRC
tRAS
VIH
RAS
tRP
tCRP
VIL
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
VIL
tRAL
tASR tRAH
tASC
tCAH
VIH
VIL
Row
Column
Address
tCWL
tWCH
tWCS
tWP
VIH
VIL
WE
OE
DQ
tRWL
VIH
VIL
tDS
tDH
VIH
VIL
Valid Data-in
Open
“H” or “L”
9/14
MSM514265E
·
Read Modify Write Cycle
tRWC
tRAS
tCSH
VIH
RAS
tRP
tCRP
VIL
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
tRAH
VIL
tCWL
tRWL
tASR
tASC
tCAH
VIH
Row
Column
Address
VIL
tRCS
tCWD
tWP
tRWD
VIH
VIL
WE
OE
tAWD
tAA
tOEH
tOEA
VIH
VIL
tOED
tOEZ
tDH
tDS
tCAC
tRAC
tCLZ
VI/OH
VI/OL
Valid
Data-out
Valid
Data-in
DQ
“H” or “L”
10/14
MSM514265E
tRP
·
Fast Page Mode Read Cycle (Part-1)
tRASP
tRCD
tHPC
tRHCP
VIH
RAS
VIL
tCSH
tCP
tCP
tCRP
tCAS
tCAH
tCAS
tCAS
VIH
CAS
tRAD
VIL
tASC
tASR
tASC
tASC
tCAH
tRAH
tCAH
VIH
VIL
Row
Column
Column
Column
Address
WE
tRCS
tOCH
tRRH
VIH
VIL
tAA
tCHO
tOEP
tCAC
tOEP
tCAC
tRAC
tOEA
tAA
tAA
VIH
VIL
OE
tCPA
tDOH
tOEA
tOEA
tOEZ
tREZ
tOEZ
tCAC
VOH
VOL
Valid
Data-out
Valid*
Data-out
Valid*
Data-out
Valid
Data-out
DQ
tCLZ
* : Same Dada,
“H” or “L”
·
Fast Page Mode Read Cycle (Part-2)
tRASP
tRP
tRCD
tHPC
tRHCP
VIH
RAS
VIL
tCRP
tCSH
tCP
tCP
tCAS
tCAH
tCAS
tCAH
tCAS
VIH
VIL
CAS
Address
WE
tRAD
tRAH
tASR
tASC
tASC
tASC
tCAH
VIH
VIL
Row
Column
Column
Column
tRCS
tRCS
VIH
VIL
tAA
tRCH
tWPE
tOEA
tRAC
tCPA
tAA
tAA
VIH
VIL
OE
tCAC
tCEZ
tCAC
tWEZ
tCAC
tDOH
VOH
VOL
Valid
Data-out
Valid
Data-out
Valid
Data-out
DQ
tCLZ
“H” or “L”
11/14
MSM514265E
tRP
·
Fast Page Mode Write Cycle (Early Write)
tRASP
tCSH
tHPC
tHPC
VIH
RAS
VIL
tCRP
tRCD
tCP
tCP
tRSH
tCAS
tCAS
tCAH
tCAS
tCAH
VIH
VIL
CAS
Address
WE
tRAD
tRAH
tASR
tASC
tASC
tASC
tCAH
VIH
VIL
Row
Column
Column
Column
tWCS
tWCH
tWCS tWCH
tWCS tWCH
VIH
VIL
VIH
VIL
OE
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ
“H” or “L”
·
Fast Page Mode Read Modify Write Cycle
tRASP
tRWD
tCPWD
VIH
RAS
VIL
tCRP
tRCD
tCP
tRWL
tCWD
VIH
VIL
CAS
tASC
tASC
tRAD
tRAH
tHPRWC
tCAH
tCAH
tCPA
tASR
tCWL
VIH
VIL
Row
Column
Column
Address
WE
tCWD
tAWD
tRCS
tRCS
VIH
VIL
tAWD
tAA
tWP
tWP
tDS
tDS
tRAC
tOEA
VIH
VIL
OE
DQ
tOED
tOEH
tOED
tOEH
tCAC
tOEZ
tDH
tCAC
tOEZ
tDH
VI/OH
VI/OL
Valid *
Data-out
Valid *
Data-in
Valid *
Data-out
Valid *
Data-in
tCLZ
tCLZ
“H” or “L”
12/14
MSM514265E
·
RAS-Only Refresh Cycle
tRC
tRAS
VIH
RAS
tRP
VIL
tCRP
tRPC
VIH
VIL
CAS
Address
DQ
tASR tRAH
VIH
VIL
Row
tCEZ
VOH
VOL
Open
Note: WE, OE = “H” or “L”
“H” or “L”
·
CAS before RAS Refresh Cycle
tRP
tRC
tRAS
VIH
RAS
tRPC
VIL
tRP
tCP
tCSR
tRPC
tCHR
VIH
CAS
VIL
tCEZ
VOH
VOL
Open
Note: WE, OE, Address = “H” or “L”
DQ
13/14
MSM514265E
·
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRAS
VIH
RAS
VIL
tCRP
tRP
tRCD
tRSH
tRP
tCHR
VIH
CAS
tRAD
tRAH
VIL
tASR
tASC
tCAH
VIH
VIL
Row
Column
Address
WE
tRCS
tCAC tRRH
tRAL
VIH
VIL
tWRH
tWRP
tAA
tROH
tOEA
VIH
VIL
OE
DQ
tRAC
tOEZ
tCLZ
VOH
VOL
Open
Valid Data-out
“H” or “L”
·
Hidden Refresh Write Cycle
tRC
tRC
tRAS
tRAS
VIH
RAS
VIL
tCRP
tRP
tRCD
tRSH
tRP
tCHR
VIH
CAS
tRAD
tRAH
VIL
tASR
tASC
tCAH
VIH
VIL
Row
Column
Address
tRAL
tRWL
tWP
VIH
VIL
WE
OE
DQ
tWCH
tWCS
VIH
VIL
tDS
tDH
VIH
VIL
Valid Data-in
“H” or “L”
14/14
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit and assembly designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. OKI assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
oraccident,improperhandling,orunusualphysicalorelectricalstressincluding,butnot
limitedto,exposuretoparametersbeyondthespecifiedmaximumratingsoroperation
outside the specified operating range.
5. Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurementequipment, consumerelectronics, etc.). Theseproductsarenotauthorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to:traffic control, automotive, safety, aerospace,
nuclear power control, and medical, including lift support and maintenance.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8. Nopartofthecontentscontainedhereinmaybereprintedorreproducedwithoutourprior
permission.
Copyright 1997 OKI ELECTRIC INDUSTRY CO.,LTD.
相关型号：
©2020 ICPDF网 联系我们和版权申明