MSM518200-80TS-K [OKI]
4,194,304-Word X 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE; 4,194,304字×2位的动态RAM ：快速页面模式类型
| 型号： | MSM518200-80TS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 4,194,304-Word X 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| 文件： | 总17页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2G0028-17-41
This version: Jan. 1998
Previous version: May 1997
¡ Semiconductor
MSM518200
4,194,304-Word ¥ 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM518200 is a 4,194,304-word ¥ 2-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MSM518200 achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer
metal CMOS process. The MSM518200 is available in a 26/24-pin plastic SOJ or 26/24-pin plastic
TSOP.
FEATURES
• 4,194,304-word ¥ 2-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 4096 cycles/64 ms
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Package options:
26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM518200-xxSJ)
26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM518200-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
tRAC tAA tCAC tOEA
60 ns 30 ns 15 ns 15 ns
70 ns 35 ns 20 ns 20 ns
80 ns 40 ns 20 ns 20 ns
Cycle Time
(Min.)
Power Dissipation
Family
Standby (Max.)
Operating (Max.)
MSM518200-60
MSM518200-70
MSM518200-80
110 ns
130 ns
150 ns
385 mW
358 mW
330 mW
5.5 mW
1/17
¡ Semiconductor
MSM518200
PIN CONFIGURATION (TOP VIEW)
VCC
1
26 VSS
25 NC
VCC
1
26 VSS
25 NC
DQ1 2
DQ2 3
WE 4
DQ1 2
DQ2 3
WE 4
24 CAS1
23 CAS2
24 CAS1
23 CAS2
5
22
5
22
OE
RAS
OE
RAS
A11R 6
21 A9
A11R 6
21 A9
A10R 8
A0 9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
A10R 8
A0 9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
A1 10
A2 11
A3 12
VCC 13
A1 10
A2 11
A3 12
VCC 13
26/24-Pin Plastic SOJ
26/24-Pin Plastic TSOP
(K Type)
Pin Name
A0 - A9,
A10R, A11R
RAS
Function
Address Input
Row Address Strobe
Column Address Strobe
Data Input/Data Output
Output Enable
CAS1, CAS2
DQ1, DQ2
OE
WE
Write Enable
VCC
Power Supply (5 V)
Ground (0 V)
VSS
NC
No Connection
Note :
The same power supply voltage must be provided to every V pin, and the same GND
CC
voltage level must be provided to every V pin.
SS
2/17
¡ Semiconductor
MSM518200
BLOCK DIAGRAM
Timing
Generator
RAS
Timing
Generator
CAS1
CAS2
Write
Clock
Generator
Column
Address
Column
Decoders
WE
10
10
OE
Buffers
Output
Buffers
2
2
2
Internal
Address
Counter
I/O
Selector
Refresh
Control Clock
Sense
Amplifiers
2
2
A0 - A9
2
DQ1, DQ2
Input
Buffers
2
10
2
Row
Address
Buffers
Row
De-
coders
Word
Drivers
Memory
Cells
12
A10R, A11R
VCC
On Chip
VBB Generator
VSS
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS
CAS1
CAS2
WE
OE
DQ1
DQ2
High-Z
High-Z
High-Z
DOUT
Standby
Refresh
H
L
L
L
L
L
L
L
L
High-Z
High-Z
DOUT
*
H
*
H
H
*
*
*
H
*
L
DQ1 Read
DQ2 Read
DQ1, DQ2 Read
DQ1 Write
DQ2 Write
DQ1, DQ2 Write
—
L
H
L
L
H
L
L
High-Z
DOUT
L
L
H
L
L
L
H
H
L
L
L
DOUT
DIN
H
H
H
H
Don't Care
DIN
Don't Care
DIN
L
DIN
L
High-Z
High-Z
H
*: "H" or "L"
3/17
¡ Semiconductor
MSM518200
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VT
Rating
–1.0 to 7.0
50
Unit
V
IOS
mA
W
PD
*
1
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Symbol
VCC
Min.
4.5
0
Typ.
5.0
0
Max.
5.5
0
Unit
V
V
V
V
VSS
Input High Voltage
Input Low Voltage
VIH
2.4
–1.0
—
6.5
0.8
VIL
—
Capacitance
(VCC = 5 V 10ꢀ, Ta = 25°C, f = 1 MHꢁ)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance
(A0 - A9, A10R, A11R)
CIN1
—
6
pF
Input Capacitance
CIN2
CI/O
—
—
7
pF
pF
(RAS, CAS1, CAS2, WE, OE)
Output Capacitance (DQ1, DQ2)
10
4/17
¡ Semiconductor
MSM518200
DC Characteristics
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C)
MSM518200 MSM518200 MSM518200
-60 -70 -80
Parameter
Symbol
Condition
Unit Note
Min. Max. Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
VOH IOH = –5.0 mA
VOL IOL = 4.2 mA
0 V £ VI £ 6.5 V;
ILI All other pins not
under test = 0 V
DQ disable
2.4
0
VCC
0.4
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
Input Leakage Current
–10
–10
—
10
10
70
–10
–10
—
10
10
65
–10
–10
—
10
10
60
mA
Output Leakage Current ILO
mA
0 V £ VO £ 5.5 V
RAS, CAS1, CAS2
Average Power
Supply Current
(Operating)
ICC1 cycling,
mA 1, 2
tRC = Min.
RAS, CAS1, CAS2 = VIH
ICC2 RAS, CAS1, CAS2
≥ VCC –0.2 V
—
—
2
1
—
—
2
1
—
—
2
1
Power Supply
mA
1
Current (Standby)
Average Power
RAS cycling,
Supply Current
ICC3 CAS1, CAS2 = VIH,
tRC = Min.
—
—
—
—
70
5
—
—
—
—
65
5
—
—
—
—
60
5
mA 1, 2
(RAS-only Refresh)
RAS = VIH,
Power Supply
ICC5 CAS1, CAS2 = VIL,
DQ = enable
mA
1
Current (Standby)
Average Power
RAS cycling,
Supply Current
ICC6 CAS1, CAS2
before RAS
70
60
65
55
60
50
mA 1, 2
mA 1, 3
(CAS before RAS Refresh)
Average Power
RAS = VIL,
Supply Current
ICC7 CAS1, CAS2 cycling,
(Fast Page Mode)
tPC = Min.
Notes : 1. I Max. is specified as I for output open condition.
CC
CC
2. The address can be changed once or less while RAS = V .
IL
3. The address can be changed once or less while CAS1, CAS2 = V
.
IH
5/17
¡ Semiconductor
MSM518200
AC Characteristics (1/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
MSM518200 MSM518200 MSM518200
-60
-70
-80
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
tRC
tRWC
tPC
110
155
40
—
—
—
130
185
45
—
—
—
150
205
50
—
—
—
ns
ns
ns
Fast Page Mode Read Modify Write
Cycle Time
85
—
100
—
105
—
ns
tPRWC
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precharge
tRAC
tCAC
tAA
—
—
—
60
15
30
—
—
—
70
20
35
—
—
—
80
20
40
ns 4, 5, 6
ns
ns
4, 5
4, 6
tCPA
—
—
0
35
15
—
15
15
50
64
—
—
—
0
40
20
—
20
20
50
64
—
—
—
0
45
20
—
20
20
50
64
—
ns 4, 14
Access Time from OE
Output Low Impedance Time from CAS
tOEA
tCLZ
ns
ns
ns
ns
ns
ms
ns
4
4
7
7
3
CAS to Data Output Buffer Turn-off Delay Time tOFF
OE to Data Output Buffer Turn-off Delay Time
Transition Time
0
0
0
tOEZ
tT
tREF
tRP
0
3
—
40
0
3
—
50
0
3
—
60
Refresh Period
RAS Precharge Time
RAS Pulse Width
tRAS
60 10,000 70 10,000 80 10,000 ns
60 100,000 70 100,000 80 100,000 ns
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
RAS Hold Time referenced to OE
CAS Precharge Time (Fast Page Mode)
CAS Pulse Width
tRASP
tRSH
tROH
tCP
15
10
10
—
—
—
20
10
10
—
—
—
20
10
10
—
—
—
ns
ns
ns
16
14
tCAS
tCSH
tCRP
tRHCP
tRCD
tRAD
tASR
tRAH
tASC
tCAH
tAR
15 10,000 20 10,000 20 10,000 ns
CAS Hold Time
60
10
35
20
15
0
—
—
—
45
30
—
—
—
—
—
—
—
—
—
70
10
40
20
15
0
—
—
—
50
35
—
—
—
—
—
—
—
—
—
80
10
45
20
15
0
—
—
—
60
40
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
5
6
10
0
10
0
10
0
Column Address Set-up Time
Column Address Hold Time
Column Address Hold Time from RAS
Column Address to RAS Lead Time
Read Command Set-up Time
Read Command Hold Time
13
13
15
50
30
0
15
55
35
0
15
60
40
0
tRAL
tRCS
tRCH
13
0
0
0
ns 8, 13
Read Command Hold Time referenced to RAS tRRH
0
0
0
ns
8
6/17
¡ Semiconductor
MSM518200
AC Characteristics (2/2)
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
MSM518200 MSM518200 MSM518200
-60
-70
-80
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Write Command Set-up Time
tWCS
0
—
0
—
0
—
ns 9, 13
Write Command Hold Time
Write Command Hold Time from RAS
tWCH
tWCR
10
45
—
—
15
55
—
—
15
60
—
—
ns
ns
13
Write Command Pulse Width
OE Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
tWP
tOEH
tRWL
tCWL
10
15
15
15
—
—
—
—
10
20
20
20
—
—
—
—
10
20
20
20
—
—
—
—
ns
ns
ns
ns
15
Data-in Set-up Time
tDS
tDH
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
15
55
20
50
65
100
70
10
10
20
10
10
10
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
15
60
20
50
70
110
75
10
10
20
10
10
10
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns 10, 13
Data-in Hold Time
15
50
15
40
55
85
ns 10, 13
Data-in Hold Time from RAS
OE to Data-in Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
RAS to WE Delay Time
tDHR
tOED
tCWD
tAWD
tRWD
ns
ns
ns
ns
ns
9
9
9
CAS Precharge WE Delay Time
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS) tCSR
RAS to CAS Hold Time (CAS before RAS) tCHR
WE to RAS Precharge Time (CAS before RAS) tWRP
WE Hold Time from RAS (CAS before RAS) tWRH
RAS to WE Set-up Time (Test Mode)
RAS to WE Hold Time (Test Mode)
tCPWD 60
ns 9, 14
tRPC
10
10
20
10
10
10
20
ns
ns
ns
ns
ns
ns
ns
13
13
14
tWTS
tWTH
7/17
¡ Semiconductor
MSM518200
Notes: 1. Astart-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume t = 5 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.
IH
IL
Transition times (t ) are measured between V and V .
T
IH
IL
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t (Max.) limit ensures that t (Max.) can be met.
RCD
RAC
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
is greater than the specified
.
CAC
RCD
RCD
t
RCD
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RAD
RAC
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
is greater than the specified
RAD
RAD
t
.
RAD
AA
7. t
(Max.) and t
(Max.) define the time at which the output achieves the open
OFF
OEZ
circuit condition and are not referenced to output voltage levels.
8. t
9. t
or t
must be satisfied for a read cycle.
RCH
RRH
, t
, t
, t
and t
are not restrictive operating parameters. They are
WCS CWD RWD AWD
CPWD
included in the data sheet as electrical characteristics only. If t
≥t
(Min.), then
WCS WCS
the cycle is an early write cycle and the data out will remain open circuit (high
impedance)throughouttheentirecycle. Ift ≥t (Min.), t ≥t (Min.),
CWD CWD
RWD RWD
t
≥t
(Min.) and t
≥t
(Min.), then the cycle is a read modify write
AWD AWD
CPWD CPWD
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated. In a test mode
CA0 and CA1 are not used and each DQ pin now accesses 4-bit locations. Since all 2 DQ
pins are used, a total of 8 data bits can be written in parallel into the memory array. In
a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data
bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the
memory device returned to its normal operating state by performing a RAS-only
refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specifiedvalue.Theseparametersshouldbespecifiedintestmodecyclebyaddingthe
above value to the specified value in this data sheet.
13. These parameters are determined by the falling edge of either CAS1 or CAS2,
whichever is earlier.
14. These parameters are determined by the rising edge of either CAS1 or CAS2,
whichever is later.
15. t
should be satisfied by both CAS1 and CAS2.
CWL
16. t is determined by the time both CAS1 and CAS2 are high.
CP
8/17
¡ Semiconductor
MSM518200
Notes concerning CAS1 and CAS2 control
Overlap the active-low timings of CAS1 and CAS2. Skew between CAS1 and CAS2 is allowed
under the following conditions:
(1) The timing specification for CAS1 and CAS2 should be met individually.
(2) Different operation modes for CAS1/CAS2 are not allowed (as shown below).
RAS
CAS1
CAS2
WE
Delayed write
Early write
(3) Closely separated CAS1/CAS2 control is not allowed. However, when the condition
(t ≤ t ) is satisfied, fast page mode can be performed.
CP
UL
RAS
CAS1
CAS2
tUL
9/17
E2G0094-17-41G
¡ Semiconductor
MSM518200
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
tAR
tCRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
CAS
tRAD
tASC
tASR
Row
tRAH
tRAL
tCAH
Column
VIH
VIL
–
–
Address
tRCH
tRCS
tRRH
VIH
VIL
–
–
tAA
WE
OE
tROH
tOEA
VIH
VIL
–
–
tOFF
tCAC
tRAC
tOEZ
VOH
VOL
–
–
DQ
Open
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
VIH
VIL
–
–
tAR
tCRP
RAS
CAS
tCSH
tCRP
tRCD
tRAD
tRAH
tASC
tRSH
tCAS
VIH
VIL
–
–
tRAL
tASR
Row
tCAH
Column
tWCH
VIH
VIL
–
–
Address
tWCS
tCWL
VIH
VIL
–
–
tWP
WE
tRWL
tWCR
VIH
VIL
–
–
OE
tDHR
tDS
tDH
VIH
VIL
–
–
DQ
Open
Valid Data-in
"H" or "L"
10/17
¡ Semiconductor
MSM518200
Read Modify Write Cycle
tRWC
tRAS
tRP
VIH
VIL
–
–
tAR
RAS
CAS
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
tRAH
tASC
tASR
tCAH
Column
VIH
VIL
–
–
Row
Address
tCWL
tRWL
tWP
tCWD
tAWD
tRAD
tRWD
tOEA
VIH
VIL
–
–
tAA
WE
OE
tRCS
VIH
VIL
–
–
tOED
tOEZ
tOEH
tDH
tCAC
tDS
tRAC
VI/OH
–
Valid
Data-out
Valid
Data-in
DQ
–
tCLZ
VI/OL
"H" or "L"
11/17
¡ Semiconductor
MSM518200
Fast Page Mode Read Cycle
tRASP
tRP
tAR
tRCD
tRAD
tRAH tASC
tRHCP
VIH
VIL
–
–
RAS
CAS
tCRP
tPC
tRSH
tCRP
tCP
tCP
tCAS
tCAS
tCAS
tRAL
VIH
VIL
–
–
tCSH
tCAH
tASR
Row
tASC
tCAH
tASC tCAH
VIH
VIL
–
–
Column
Column
Column
tRCS
Address
tRCH
tRCS
tRCS
tRCH
tRCH
VIH
VIL
–
–
WE
tAA
tAA
tAA
tRRH
tCPA
tCPA
tOEA
tOEA
tOEA
VIH
VIL
–
–
OE
tOFF
tOEZ
tOFF
tOEZ
tCAC
tCLZ
tCAC
tCLZ
tOFF
tCAC
tRAC
tOEZ
VOH
VOL
–
–
Valid
Data-out
Valid
Data-out
Valid
Data-out
DQ
tCLZ
"H" or "L"
Fast Page Mode Write Cycle (Early Write)
tRASP
tPC
tRP
tCRP
tAR
tRHCP
tRSH
tCAS
tRAL
VIH
VIL
–
–
RAS
CAS
tCRP
tRCD
tCP
tCP
tCAS
tCAS
tCAH
Column
VIH
VIL
–
–
tCSH
tCAH
tASR
Row
tASC
tASC
tASC
tRAH
tCAH
VIH
VIL
–
–
Column
tCWL
tWCH
tWP
Column
Address
tRAD
tWCS
tCWL
tWCH
tWP
tRWL
tCWL
tWCH
tWP
tWCS
tWCS
VIH
VIL
–
–
WE
tWCR
tDS
tDS
tDS
tDH
tDH
tDH
VIH
VIL
–
–
Valid
Data-in
Valid
Data-in
Valid Data-in
tDHR
DQ
Note: OE = "H" or "L"
"H" or "L"
12/17
¡ Semiconductor
MSM518200
Fast Page Mode Read Modify Write Cycle
tRASP
VIH
VIL
tAR
–
–
RAS
CAS
tRP
tCSH
tPRWC
tCAS
tRSH
tCAS
tCRP
tCP
tCP
tRCD
tCAS
VIH
VIL
–
–
tRAD
tRAH
tASC
tCAH
tASC
tRAL
tCAH
tCAH
tASR
tASC
VIH
VIL
–
–
Column
tRWD
Column
tRCS
Column
Address
Row
tRCS
tCPWD
tCPWD
tCWD
tRWL
tCWL
tCWD
tCWD
tRCS
tCWL
tCWL
VIH
VIL
–
–
WE
tAWD
tAWD
tAWD
tROH
tWP
tWP
tDH
tWP
tDH
tDH
tDS
tDS
tDS
tRAC
tCPA
tAA
tCPA
tAA
tAA
tOEA
tOEA
tOEA
tOED
tOED
tOED
VIH
VIL
–
–
OE
tOEZ
tOEZ
tOEZ
tCAC
tCAC
tCAC
VI/OH
–
DQ
Out
In
Out
In
Out
In
–
VI/OL
tCLZ
tCLZ
tCLZ
"H" or "L"
RAS-Only Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tCRP
tRPC
VIH
VIL
–
–
tASR tRAH
VIH
VIL
–
–
Address
DQ
Row
tOFF
VOH
VOL
–
–
Open
Note: WE, OE = "H" or "L"
"H" or "L"
13/17
¡ Semiconductor
MSM518200
CAS before RAS Refresh Cycle
tRC
tRP
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tRPC
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
tWRP
tWRP
tWRH
VIH
VIL
–
–
WE
tOFF
VOH
VOL
DQ
–
–
Open
Note: OE, Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRAS
tRP
tRP
VIH
VIL
–
–
tAR
tRCD
RAS
tCRP
tRSH
tCHR
VIH
VIL
–
–
tRAD
tASC
tRAH
CAS
tCAH
tASR
VIH
VIL
–
–
Address
Row
Column
tRCS
tRRH
tRAL
VIH
VIL
–
–
tAA
WE
OE
tROH
tOEA
VIH
VIL
–
–
tCAC
tCLZ
tOFF
tRAC
tOEZ
VOH
VOL
–
–
DQ
Valid Data-out
"H" or "L"
14/17
¡ Semiconductor
MSM518200
Hidden Refresh Write Cycle
tRC
tRC
tRAS
tRAS
tRP
tRP
tAR
tRCD
VIH
VIL
–
–
RAS
tCRP
tRSH
tCHR
VIH
VIL
–
–
tRAD
tASC
CAS
tCAH
Column
tASR
Row
tRAH
tRAL
VIH
VIL
–
–
Address
tWRP
tWRH
tWCS
tWCH
tWP
VIH
VIL
–
–
WE
OE
VIH
VIL
–
–
tDS
tDH
VIH
VIL
–
–
Valid Data-in
tDHR
DQ
"H" or "L"
Test Mode Initiate Cycle
tRC
tRAS
tRP
VIH
VIL
–
–
RAS
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
CAS
WE
tWTS
tWTH
VIH
VIL
–
–
tOFF
VOH
VOL
–
–
DQ
Open
Note: OE, Address = "H" or "L"
"H" or "L"
15/17
¡ Semiconductor
PACKAGE DIMENSIONS
SOJ26/24-P-300-1.27
MSM518200
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/17
¡ Semiconductor
MSM518200
(Unit : mm)
TSOPII26/24-P-300-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.29 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/17
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