MSM51V16165DSL-70TS-K [OKI]
EDO DRAM, 1MX16, 70ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-50/44;
| 型号： | MSM51V16165DSL-70TS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | EDO DRAM, 1MX16, 70ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-50/44 动态存储器 光电二极管 |
| 文件： | 总17页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2G0132-17-61
Preliminary
This version: Mar. 1998
¡ Semiconductor
MSM51V16165D/DSL
1,048,576-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM51V16165D/DSL is a 1,048,576-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-
gateCMOStechnology.TheMSM51V16165D/DSLachieveshighintegration,high-speedoperation,
andlow-powerconsumptionbecauseOkimanufacturesthedeviceinaquadruple-layerpolysilicon/
double-layer metal CMOS process. The MSM51V16165D/DSL is available in a 42-pin plastic SOJ or
50/44-pin plastic TSOP. The MSM51V16165DSL (the self-refresh version) is specially designed for
lower-power applications.
FEATURES
• 1,048,576-word ¥ 16-bit configuration
• Single 3.3 V power supply, ±0.3 V tolerance
• Input
: LVTTL compatible, low input capacitance
• Output : LVTTL compatible, 3-state
• Refresh : 4096 cycles/64 ms, 4096 cycles/128 ms (SL version)
• Fast page mode with EDO, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• CAS before RAS self-refresh capability (SL version)
• Package options:
42-pin 400 mil plastic SOJ
(SOJ42-P-400-1.27)
(Product : MSM51V16165D/DSL-xxJS)
50/44-pin 400 mil plastic TSOP
(TSOPII50/44-P-400-0.80-K) (Product : MSM51V16165D/DSL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Cycle Time
(Min.)
Power Dissipation
Family
tRAC tAA tCAC tOEA
50 ns 25 ns 13 ns 13 ns
60 ns 30 ns 15 ns 15 ns
70 ns 35 ns 20 ns 20 ns
Standby (Max.)
Operating (Max.)
MSM51V16165D/DSL-50
MSM51V16165D/DSL-60
MSM51V16165D/DSL-70
84 ns
104 ns
124 ns
360 mW
324 mW
288 mW
1.8 mW/
0.72 mW (SL version)
1/17
¡ Semiconductor
MSM51V16165D/DSL
PIN CONFIGURATION (TOP VIEW)
VCC
1
42 VSS
VCC
1
50 VSS
DQ1 2
DQ2 3
DQ3 4
DQ4 5
41 DQ16 DQ1 2
40 DQ15 DQ2 3
39 DQ14 DQ3 4
38 DQ13 DQ4 5
49 DQ16
48 DQ15
47 DQ14
46 DQ13
45 VSS
VCC
6
37 VSS
VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
36 DQ12 DQ5 7
35 DQ11 DQ6 8
34 DQ10 DQ7 9
44 DQ12
43 DQ11
42 DQ10
41 DQ9
40 NC
33 DQ9
32 NC
DQ8 10
NC 11
NC 12
31 LCAS
30 UCAS
29 OE
WE 13
RAS 14
A11R 15
A10R 16
A0 17
28 A9R
27 A8R
26 A7
NC 15
NC 16
36 NC
35 LCAS
34 UCAS
33 OE
WE 17
RAS 18
A11R 19
A10R 20
A0 21
A1 18
25 A6
A2 19
24 A5
32 A9R
31 A8R
30 A7
A3 20
23 A4
VCC 21
22 VSS
A1 22
29 A6
42-Pin Plastic SOJ
A2 23
28 A5
A3 24
27 A4
VCC 25
26 VSS
50/44-Pin Plastic TSOP
(K Type)
Pin Name
A0 - A7,
A8R - A11R
RAS
Function
Address Input
Row Address Strobe
Lower Byte Column Address Strobe
Upper Byte Column Address Strobe
Data Input/Data Output
Output Enable
LCAS
UCAS
DQ1 - DQ16
OE
WE
Write Enable
VCC
Power Supply (3.3 V)
Ground (0 V)
VSS
NC
No Connection
Note :
The same power supply voltage must be provided to every V pin, and the same GND
CC
voltage level must be provided to every V pin.
SS
2/17
¡ Semiconductor
MSM51V16165D/DSL
BLOCK DIAGRAM
WE
OE
Timing
Generator
RAS
I/O
Controller
LCAS
UCAS
Output
8
8
Buffers
I/O
Controller
DQ1 - DQ8
Input
Column
Address
Buffers
Column Decoders
8
8
8
8
Buffers
I/O
Selector
Internal
Address
Counter
Sense Amplifiers
16
16
Refresh
Control Clock
A0 - A7
Input
8
8
8
8
Buffers
8
4
Row
Address
Buffers
Row
Memory
Cells
12
DQ9 - DQ16
Deco-
Word
Drivers
ders
A8R - A11R
VCC
Output
Buffers
On Chip
V
Generator
BB
VSS
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS
LCAS
UCAS
WE
OE
DQ1 - DQ8
High-Z
High-Z
DOUT
DQ9 - DQ16
High-Z
Standby
Refresh
H
L
L
L
L
L
L
L
L
*
H
*
H
H
*
*
High-Z
*
H
*
L
High-Z
Lower Byte Read
Upper Byte Read
Word Read
L
H
L
L
H
L
L
High-Z
DOUT
L
L
H
L
L
L
H
H
L
L
L
DOUT
DOUT
DIN
Lower Byte Write
Upper Byte Write
Word Write
—
H
H
H
H
Don't Care
DIN
Don't Care
DIN
L
DIN
L
High-Z
High-Z
H
*: "H" or "L"
3/17
¡ Semiconductor
MSM51V16165D/DSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VT
Rating
–0.5 to 4.6
50
Unit
V
IOS
mA
W
PD
*
1
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Symbol
VCC
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Unit
V
V
V
V
VSS
0
Input High Voltage
Input Low Voltage
VIH
2.0
–0.3
—
VCC + 0.3
0.8
VIL
—
Capacitance
(VCC = 3.3 V 0.3 V, Ta = 25°C, f = 1 MHꢀ)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance
(A0 - A7, A8R - A11R)
CIN1
—
5
pF
Input Capacitance
CIN2
CI/O
—
—
7
7
pF
pF
(RAS, LCAS, UCAS, WE, OE)
Output Capacitance (DQ1 - DQ16)
4/17
¡ Semiconductor
MSM51V16165D/DSL
DC Characteristics
(VCC = 3.3 V 0.3 V, Ta = 0°C to 70°C)
MSM51V16165MSM51V16165MSM51V16165
D/DSL-50 D/DSL-60 D/DSL-70
Parameter
Symbol
Condition
Unit Note
Min. Max. Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
VOH IOH = –2.0 mA
VOL IOL = 2.0 mA
0 V £ VI £ VCC + 0.3 V;
ILI All other pins not
under test = 0 V
2.4
0
VCC
0.4
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
Input Leakage Current
–10
–10
—
10
10
75
–10
–10
—
10
10
70
–10
–10
—
10
10
65
mA
DQ disable
Output Leakage Current ILO
Average Power
mA
0 V £ VO £ VCC
RAS, CAS cycling,
Supply Current
(Operating)
ICC1
mA 1, 2
tRC = Min.
RAS, CAS = VIH
—
—
—
2
—
—
—
2
—
—
—
2
Power Supply
mA
1
ICC2 RAS, CAS
≥ VCC –0.2 V
RAS cycling,
ICC3 CAS = VIH,
tRC = Min.
0.5
200
0.5
200
0.5
200
Current (Standby)
mA 1, 5
Average Power
Supply Current
—
—
—
—
—
75
5
—
—
—
—
—
70
5
—
—
—
—
—
65
5
mA 1, 2
(RAS-only Refresh)
RAS = VIH,
Power Supply
ICC5 CAS = VIL,
DQ = enable
mA
1
Current (Standby)
Average Power
Supply Current
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
Supply Current
(Battery Backup)
Average Power
Supply Current
(CAS before RAS
Self-Refresh)
RAS cycling,
ICC6
75
70
90
400
65
80
400
mA 1, 2
mA 1, 3
CAS before RAS
RAS = VIL,
ICC7 CAS cycling,
tHPC = Min.
100
400
tRC = 31.3 ms,
1, 4,
ICC10 CAS before RAS,
tRAS £ 1 ms
mA
5
RAS £ 0.2 V,
ICCS
—
300
—
300
—
300
mA 1, 5
CAS £ 0.2 V
Notes : 1. I Max. is specified as I for output open condition.
CC
CC
2. The address can be changed once or less while RAS = V .
IL
3. The address can be changed once or less while CAS = V
.
IH
4. V – 0.2 V £ V £ V + 0.3 V, –0.3 V £ V £ 0.2 V.
CC
IH
CC
IL
5. SL version.
5/17
¡ Semiconductor
MSM51V16165D/DSL
AC Characteristics (1/2)
(VCC = 3.3 V 0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3
MSM51V16165MSM51V16165MSM51V16165
D/DSL-50 D/DSL-60 D/DSL-70
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
tRC
tRWC
tHPC
84
110
20
—
—
—
104
135
25
—
—
—
124
160
30
—
—
—
ns
ns
ns
Fast Page Mode Read Modify Write
Cycle Time
tHPRWC 58
—
68
—
78
—
ns
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precharge
tRAC
tCAC
tAA
—
—
—
—
50
13
25
30
—
—
—
—
60
15
30
35
—
—
—
—
70
20
35
40
ns 4, 5, 6
ns
ns
4, 5
4, 6
tCPA
ns 4, 13
Access Time from OE
Output Low Impedance Time from CAS
Data Output Hold After CAS Low
tOEA
tCLZ
tDOH
—
0
13
—
—
13
13
13
13
50
64
128
—
—
0
15
—
—
15
15
15
15
50
64
128
—
—
0
20
—
—
20
20
20
20
50
64
128
—
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
4
4
5
5
5
CAS to Data Output Buffer Turn-off Delay Time tCEZ
RAS to Data Output Buffer Turn-off Delay Time tREZ
0
0
0
7, 8
7, 8
7
0
0
0
OE to Data Output Buffer Turn-off Delay Time
WE to Data Output Buffer Turn-off Delay Time tWEZ
tOEZ
0
0
0
0
0
0
7
Transition Time
Refresh Period
tT
1
1
1
3
tREF
tREF
tRP
—
—
30
—
—
40
—
—
50
Refresh Period (SL version)
RAS Precharge Time
RAS Pulse Width
16
tRAS
50 10,000 60 10,000 70 10,000 ns
50 100,000 60 100,000 70 100,000 ns
RAS Pulse Width (Fast Page Mode with EDO) tRASP
RAS Hold Time
RAS Hold Time referenced to OE
tRSH
tROH
7
7
—
—
—
10
10
10
—
—
—
13
13
10
—
—
—
ns
ns
ns
CAS Precharge Time (Fast Page Mode with EDO) tCP
7
15
CAS Pulse Width
tCAS
tCSH
tCRP
tRHCP
tCHO
tRCD
tRAD
tASR
tRAH
tASC
tCAH
tRAL
7
10,000 10 10,000 13 10,000 ns
CAS Hold Time
35
5
—
—
—
—
37
25
—
—
—
—
—
40
5
—
—
—
—
45
30
—
—
—
—
—
45
5
—
—
—
—
50
35
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
OE Hold Time from CAS (DQ Disable)
RAS to CAS Delay Time
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
13
13
30
5
35
5
40
5
11
9
14
12
0
14
12
0
5
6
0
7
10
0
10
0
Column Address Set-up Time
Column Address Hold Time
Column Address to RAS Lead Time
0
12
12
7
10
30
13
35
25
6/17
¡ Semiconductor
MSM51V16165D/DSL
AC Characteristics (2/2)
(VCC = 3.3 V 0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3
MSM51V16165MSM51V16165MSM51V16165
D/DSL-50 D/DSL-60 D/DSL-70
Unit Note
Parameter
Symbol
Min. Max. Min. Max. Min. Max.
Read Command Set-up Time
Read Command Hold Time
tRCS
tRCH
0
0
—
—
0
0
—
—
0
0
—
—
ns
ns 9, 12
ns
ns 10, 12
12
Read Command Hold Time referenced to RAS tRRH
Write Command Set-up Time
0
0
—
—
0
0
—
—
0
0
—
—
9
tWCS
Write Command Hold Time
tWCH
7
—
10
—
13
—
ns
12
Write Command Pulse Width
WE Pulse Width (DQ Disable)
OE Command Hold Time
tWP
tWPE
tOEH
tOEP
tOCH
tRWL
tCWL
7
7
7
7
7
7
7
—
—
—
—
—
—
—
10
10
10
10
10
10
10
—
—
—
—
—
—
—
10
10
13
10
10
13
13
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
OE Precharge Time
OE Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
14
Data-in Set-up Time
tDS
tDH
tOED
tCWD
tAWD
tRWD
0
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
ns 11, 12
ns 11, 12
ns
Data-in Hold Time
OE to Data-in Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
RAS to WE Delay Time
7
10
15
34
49
79
54
5
13
20
44
59
94
64
5
13
30
42
67
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
12
12
13
CAS Precharge WE Delay Time
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS) tCSR
RAS to CAS Hold Time (CAS before RAS)
RAS Pulse Width
tCPWD 47
tRPC
5
5
5
5
tCHR
10
10
10
tRASS 100
—
—
—
100
110
–50
—
—
—
100
130
–50
—
—
—
ms
ns
ns
16
16
16
(CAS before RAS Self-Refresh)
RAS Precharge Time
tRPS
tCHS
90
(CAS before RAS Self-Refresh)
CAS Hold Time
–50
(CAS before RAS Self-Refresh)
7/17
¡ Semiconductor
MSM51V16165D/DSL
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume t = 2 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.
IH
IL
Transition times (t ) are measured between V and V .
T
IH
IL
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.
The output timing reference levels are V = 2.0 V and V = 0.8 V.
OH
OL
5. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
is greater than the specified
RCD
RAC
t
(Max.) is specified as a reference point only. If t
RCD
RCD
t
(Max.) limit, then the access time is controlled by t
.
RCD
CAC
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
is greater than the specified
RAD
RAC
t
(Max.) is specified as a reference point only. If t
RAD
RAD
t
(Max.) limit, then the access time is controlled by t
.
RAD
AA
7. t
(Max.), t
(Max.), t
(Max.) and t
(Max.) define the time at which the
CEZ
REZ
WEZ
OEZ
output achieves the open circuit condition and are not referenced to output voltage
levels.
8. t
9. t
and t
must be satisfied for open circuit condition.
CEZ
REZ
or t
must be satisfied for a read cycle.
RCH
RRH
10. t
, t
, t
, t
and t
are not restrictive operating parameters. They are
WCS CWD RWD AWD
CPWD
included in the data sheet as electrical characteristics only. If t
≥t
(Min.), then
WCS WCS
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t ≥ t (Min.) , t ≥ t (Min.),
CWD
CWD
RWD
RWD
t
≥ t
(Min.) and t
≥ t
(Min.), then the cycle is a read modify write
AWD
AWD
CPWD
CPWD
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the UCAS and LCAS, leading edges in an early
write cycle, and to the WE leading edge in an OE control write cycle, or a read modify
write cycle.
12. These parameters are determined by the falling edge of either UCAS or LCAS,
whichever is earlier.
13. These parameters are determined by the rising edge of either UCAS or LCAS,
whichever is later.
14. t
should be satisfied by both UCAS and LCAS.
CWL
15. t is determined by the time both UCAS and LCAS are high.
CP
16. Only SL version.
8/17
E2G0104-17-41Q
¡ Semiconductor
MSM51V16165D/DSL
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
tCRP
RAS
tCSH
tCRP
tRCD
tASC
tRCS
tRSH
tCAS
VIH
VIL
–
–
CAS
tRAD
tRAH
tASR
Row
tRAL
tCAH
Column
VIH
VIL
–
–
Address
tRCH
tRRH
VIH
VIL
–
–
tAA
WE
OE
tROH
tREZ
tOEA
VIH
VIL
–
–
tCEZ
tCAC
tRAC
tOEZ
VOH
VOL
–
–
DQ
Open
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
VIH
VIL
–
–
tCRP
RAS
CAS
tCSH
tCRP
tRCD
tRAD
tRAH
tASC
tRSH
tCAS
VIH
VIL
–
–
tRAL
tASR
Row
tCAH
Column
VIH
VIL
–
–
Address
tWCS
tCWL
tWCH
tWP
VIH
VIL
–
–
WE
tRWL
VIH
VIL
–
–
OE
tDS
tDH
VIH
VIL
–
–
DQ
Open
Valid Data-in
"H" or "L"
9/17
¡ Semiconductor
MSM51V16165D/DSL
Read Modify Write Cycle
tRWC
tRAS
tRP
VIH
VIL
–
–
RAS
CAS
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
tRAH
tASC
tASR
tCAH
Column
VIH
VIL
–
–
Row
Address
tCWL
tRWL
tWP
tCWD
tAWD
tRAD
tRWD
tOEA
VIH
VIL
–
–
tAA
WE
OE
tRCS
VIH
VIL
–
–
tOED
tOEZ
tOEH
tDH
tCAC
tDS
tRAC
VI/OH
–
Valid
Data-out
Valid
Data-in
DQ
–
tCLZ
VI/OL
"H" or "L"
10/17
¡ Semiconductor
MSM51V16165D/DSL
Fast Page Mode Read Cycle (Part-1)
tRASP
tRP
VIH
VIL
–
–
tRHCP
RAS
CAS
tHPC
tCAS
tCRP
tRCD
tRAD
tCP
tCP
tCAS
tCAS
–
–
VIH
VIL
tCSH
tCAH
tASR
Row
tASC
Column
tASC
Column
tCAH
tCAH
tASC
tRAH
–
–
VIH
VIL
Column
Address
tRCS
tRRH
VIH
VIL
–
–
tCHO
tOEP
tOCH
tOEP
WE
tRAC
tAA
tAA
tAA
VIH
VIL
–
–
OE
tOEA
tCPA
tOEA
tCAC
tOEA
tOEZ
tCAC
tCAC tOEZ
tREZ
tDOH
Valid
Data-out
Valid*
Data-out
Valid*
Data-out
VOH
VOL
–
–
Valid
Data-out
DQ
tCLZ
* : Same Data,
"H" or "L"
Fast Page Mode Read Cycle (Part-2)
tRASP
tRP
tCRP
VIH
VIL
–
–
tRHCP
RAS
CAS
tHPC
tCAS
tCRP
tRCD
tRAD
tCP
tCP
tCAS
tCAS
–
–
VIH
VIL
tCSH
tASR
Row
tASC
Column
tASC
Column
tCAH
tCAH
tCAH
tASC
tRAH
–
–
VIH
VIL
Column
Address
tRCS
tRCS
VIH
VIL
–
–
tRCH
WE
tRAC
tAA
tAA
tAA
tWPE
VIH
VIL
–
–
tCPA
OE
tOEA
tCAC tWEZ
tCAC
tDOH
tCAC
tCEZ
VOH
VOL
–
–
Valid
Data-out
Valid
Data-out
Valid
Data-out
DQ
tCLZ
"H" or "L"
11/17
¡ Semiconductor
MSM51V16165D/DSL
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
VIH
VIL
–
–
RAS
CAS
tHPC
tCAS
tHPC
tCAS
tRSH
tCRP
tRCD
tRAD
tCP
tCP
tCAS
–
–
VIH
VIL
tCSH
tASC tCAH
Column
tASC tCAH
Column
tASC tCAH
tASR
tRAH
Row
–
–
VIH
VIL
Column
Address
tWCS
tWCH
tWCS tWCH
tWCS tWCH
VIH
VIL
–
–
WE
VIH
VIL
–
–
OE
tDS
tDH
Valid
tDS tDH
tDS tDH
VIH
VIL
–
–
Valid
Data-in
Valid
Data-in
DQ
Data-in
"H" or "L"
Fast Page Mode Read Modify Write Cycle
tRASP
tRWD
VIH
VIL
–
–
RAS
CAS
tCP
tCRP
tRCD
tRAD
tRAH
–
–
tCWD
tHPRWC
VIH
VIL
tCPWD
tCPA
tRWL
tCWL
tASC
tASR
tASC tCAH
tCAH
–
–
VIH
VIL
Row
Column
Column
Address
tRCS
tAWD
tCWD
tRCS
VIH
VIL
–
–
WE
OE
tAWD
tRAC
tDS tWP
tAA
tDS
tWP
tAA
VIH
VIL
–
–
tOEH
tDH
tOEH
tDH
tOED
tOED
tOEA
tOEA
tCAC
tOEZ
tOEZ
tCAC
VI/OH
VI/OL
–
–
Valid
Data-out
Valid
Data-in
Valid
Data-out
Valid
Data-in
DQ
tCLZ
tCLZ
"H" or "L"
12/17
¡ Semiconductor
MSM51V16165D/DSL
RAS-Only Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tCRP
tRPC
VIH
VIL
–
–
tASR tRAH
VIH
VIL
–
–
Address
DQ
Row
tCEZ
VOH
VOL
–
–
Open
Note: WE, OE = "H" or "L"
"H" or "L"
CAS before RAS Refresh Cycle
tRC
tRP
tRAS
tRP
VIH
VIL
–
–
RAS
tRPC
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
CAS
tCEZ
VOH
VOL
–
–
DQ
Open
Note: WE, OE, Address = "H" or "L"
13/17
¡ Semiconductor
MSM51V16165D/DSL
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRAS
tRP
tRP
VIH –
RAS
VIL
–
tCRP
tRSH
tRCD
tCHR
VIH –
tRAD
tASC
CAS
VIL
–
tCAH
Column
tASR
Row
tRAH
VIH
VIL
–
–
Address
tRCS
tRRH
tRAL
tAA
VIH –
VIL
WE
OE
–
tROH
tOEA
VIH –
VIL
–
tCAC
tCLZ
tOEZ
tRAC
VOH
VOL
–
–
DQ
Open
Valid Data-out
"H" or "L"
Hidden Refresh Write Cycle
tRC
tRAS
tRC
tRAS
tRP
tRP
VIH
VIL
–
–
RAS
CAS
tCRP
tRCD
tRSH
tCHR
–
–
VIH
VIL
tRAD
tASC
tASR
tCAH
tRAH
tRAL
–
–
VIH
VIL
Row
Column
tRWL
tWCH
tWP
Address
tWCS
VIH
VIL
–
–
WE
OE
VIH
VIL
–
–
tDS
tDH
Valid Data-in
VIH
VIL
–
–
DQ
"H" or "L"
14/17
¡ Semiconductor
MSM51V16165D/DSL
CAS before RAS Self-Refresh Cycle
tRASS
tRPS
tRP
VIH
VIL
–
–
tRPC
tCP
RAS
CAS
tRPC
tCHS
tCSR
–
–
VIH
VIL
tCEZ
VOH
VOL
–
–
Open
DQ
Note: WE, OE, Address = "H" or "L"
"H" or "L"
Only SL version
15/17
¡ Semiconductor
PACKAGE DIMENSIONS
SOJ42-P-400-1.27
MSM51V16165D/DSL
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.86 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/17
¡ Semiconductor
MSM51V16165D/DSL
(Unit : mm)
TSOPII50/44-P-400-0.80-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.60 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/17
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