MSM51V16405F-50SJ [OKI]
EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOJ-26/24;
| 型号： | MSM51V16405F-50SJ |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOJ-26/24 |
| 文件： | 总18页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDD51V16405F-02
Issue Date: Aug. 16, 2002
OKI Semiconductor
MSM51V16405F
4,194,304-Word × 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM51V16405F is a 4,194,304-word × 4-bit dynamic RAM fabricated in Oki’s silicon-gate
CMOS technology. The MSM51V16405F achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in
a
quadruple-layer
polysilicon/double-layer metal CMOS process. The MSM51V16405F is available in a 26/24-pin plastic
TSOP.
FEATURES
· 4,194,304-word × 4-bit configuration
· Single 3.3V power supply, ±0.3V tolerance
· Input : LVTTL compatible, low input capacitance
· Output : LVTTL compatible, 3-state
· Refresh : 4096 cycles/64ms
· Fast page mode with EDO, read modify write capability
· CAS before RAS refresh, hidden refresh, RAS-only refresh capability
· Packages
26/24-pin 300mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM51V16405F-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation
Cycle Time
(Min.)
Family
Operating
(Max.)
Standby
(Max.)
tRAC
tAA
tCAC
tOEA
50ns
60ns
70ns
25ns
30ns
35ns
13ns
15ns
20ns
13ns
15ns
20ns
84ns
104ns
124ns
360mW
324mW
288mW
MSM51V16405F
1.8mW
1/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
PIN CONFIGURATION (TOP VIEW)
VCC
1
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
21 A9
DQ1 2
DQ2 3
WE 4
RAS 5
A11R 6
A10R 8
A0 9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
A1 10
A2 11
A3 12
V
CC 13
26/24-Pin Plastic TSOP
(K Type)
Pin Name
Function
Address Input
A0–A9, A10R, A11R
RAS
CAS
Row Address Strobe
Column Address Strobe
Data Input/Data Output
Output Enable
DQ1–DQ4
OE
WE
Write Enable
VCC
Power Supply (3.3V)
Ground (0V)
VSS
NC
No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must
be provided to every VSS pin.
2/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
BLOCK DIAGRAM
Timing
Generator
RAS
CAS
Timing
Generator
WE
Write
Clock
OE
4
Column
Address
Buffers
Generator
10
10
Column Decoders
Sense Amplifiers
Output
Buffers
4
I/O
Selector
Internal
Address
Counter
4
4
4
DQ1 − DQ4
Refresh
Control Clock
A0 − A9
Input
Buffers
4
4
10
2
Row
Address 12
Buffers
Row
Deco-
ders
Word
Drivers
Memory
Cells
A10R , A11R
VCC
On Chip
VBB Generator
VSS
3/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIUM RATINGS
Parameter
Voltage on Any Pin Relative to VSS
Voltage VCC Supply relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VIN, VOUT
VCC
Value
–0.5 to VCC+ 0.5
–0.5 to 4.6
50
Unit
V
V
IOS
mA
W
PD*
1
Operating Temperature
Topr
0 to 70
°C
°C
Storage Temperature
Tstg
–55 to 150
*: Ta = 25°C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter
Symbol
VCC
VSS
Min.
3.0
Typ.
Max.
Unit
V
3.3
0
3.6
Power Supply Voltage
0
0
VCC + 0.3*1
0.8
V
Input High Voltage
Input Low Voltage
VIH
2.0
V
VIL
− 0.3*2
V
Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect
to the point at which VCC is applied).
*2. The input voltage is VSS − 1.0V when the pulse width is less than 20ns (the pulse width respect to the
point at which VSS is applied).
PIN CAPACITANCE
(Vcc = 3.3V ± 0.3V, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
CIN1
Min.
—
Min.
5
Unit
pF
Input Capacitance (A0 – A9, A10R, A11R)
Input Capacitance
CIN2
CI/O
—
—
7
7
pF
pF
(RAS, CAS, WE, OE)
Output Capacitance (DQ1 – DQ4)
4/18
FEDD51V16405F-02
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Semiconductor
MSM51V16405F
DC CHARACTERISTICS
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C)
MSM51V16405 MSM51V16405 MSM51V16405
F-50 F-60 F-70
Parameter
Symbol
Condition
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Output High Voltage
Output Low Voltage
V
I
I
= −2.0mA
2.4
0
V
2.4
0
V
2.4
0
V
CC
V
V
OH
OH
OL
CC
CC
V
= 2.0mA
0.4
0.4
0.4
OL
0V ≤ V ≤ V +0.3V;
I
CC
Input Leakage
Current
I
− 10
− 10
10
− 10
− 10
10
− 10
− 10
10
µA
µA
All other pins not
under test = 0V
LI
DQ disable
Output Leakage
Current
I
10
75
10
70
10
65
LO
0V ≤ V ≤ V
O
CC
Average Power
Supply Current
RAS, CAS cycling,
= Min.
I
mA 1,2
CC1
CC2
t
RC
(Operating)
RAS, CAS = V
RAS, CAS
2
2
2
IH
Power Supply
Current
I
I
I
mA
1
0.5
0.5
0.5
(Standby)
≥ V
− 0.2V
CC
RAS cycling,
Average Power
Supply Current
CAS = V ,
IH
75
5
70
5
65
5
mA 1,2
CC3
CC5
(RAS-only Refresh)
t
= Min.
RC
RAS = V ,
IH
Power Supply
Current
CAS = V ,
mA
1
IL
(Standby)
DQ = enable
Average Power
Supply Current
RAS = cycling,
I
I
75
70
90
65
80
mA 1,2
mA 1,3
CC6
CC7
(CAS before RAS
Refresh)
CAS before RAS
RAS = V ,
Average Power
Supply Current
IL
CAS cycling,
100
(Fast Page Mode)
t
= Min.
HPC
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
5/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
AC CHARACTERISTICS (1/3)
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13
MSM51V16405 MSM51V16405 MSM51V16405
F-50 F-60 F-70
Parameter
Symbol
Unit Note
Min.
84
Max. Max. Max.
Min.
104
135
25
Min.
124
160
30
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
t
ns
ns
ns
RC
t
110
20
RWC
t
HPC
Fast Page Mode Read Modify Write
Cycle Time
t
58
68
78
ns
HPRWC
Access Time from RAS
t
t
50
13
25
30
13
60
15
30
35
15
70
20
35
40
20
ns 4, 5, 6
RAC
CAC
Access Time from CAS
ns
ns
ns
ns
4,5
4,6
4
Access Time from Column Address
Access Time from CAS Precharge
Access Time from OE
t
AA
t
CPA
OEA
t
4
Output Low Impedance Time from
CAS
t
0
5
0
13
0
5
0
15
0
5
0
20
ns
ns
ns
4
CLZ
Data Output Hold After CAS Low
t
DOH
CAS to Data Output Buffer Turn-
off Delay Time
t
7,8
7,8
7
CEZ
REZ
OEZ
RAS to Data Output Buffer Turn-
off Delay Time
t
0
0
0
13
13
13
0
0
0
15
15
15
0
0
0
20
20
20
ns
ns
ns
OE to Data Output Buffer Turn-off
Delay Time
t
WE to Data Output Buffer Turn-
off Delay Time
t
7
3
WEZ
Transition Time
t
1
50
64
1
50
64
1
50
64
ns
ms
ns
T
Refresh Period
t
30
50
40
60
50
70
REF
RAS Precharge Time
RAS Pulse Width
t
RP
t
10,000
10,000
10,000 ns
100,000 ns
RAS
RAS Pulse Width
(Fast Page Mode with EDO)
t
50
100,000
60
100,000
70
RASP
RAS Hold Time
t
7
7
10
10
13
13
ns
ns
RSH
RAS Hold Time referenced to OE
t
ROH
CAS Precharge Time
(Fast Page Mode with EDO)
t
7
10
10
ns
CP
CAS Pulse Width
CAS Hold Time
t
7
10,000
10
40
10,000
13
45
10,000 ns
ns
CAS
t
35
CSH
6/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
AC CHARACTERISTICS (2/3)
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13
MSM51V16405 MSM51V16405 MSM51V16405
F-50 F-60 F-70
Parameter
Symbol
Unit Note
Min.
5
Max. Max. Max.
Min.
Min.
CAS to RAS Precharge Time
t
5
5
ns
ns
CRP
RAS Hold Time from CAS Precharge t
30
35
40
RHCP
OE Hold Time from CAS
(DQ Disable)
t
5
5
5
ns
CHO
RAS to CAS Delay Time
t
t
11
9
37
25
14
12
0
45
30
14
12
0
50
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
RCD
RAS to Column Address Delay Time
Row Address Set-up Time
RAD
t
0
ASR
Row Address Hold Time
t
7
10
0
10
0
RAH
Column Address Set-up Time
Column Address Hold Time
Column Address to RAS Lead Time
Read Command Set-up Time
Read Command Hold Time
t
0
ASC
t
7
10
30
0
13
35
0
CAH
t
25
0
RAL
RCS
RCH
t
t
t
0
0
0
9
9
Read Command Hold Time
referenced to RAS
0
0
0
ns
RRH
Write Command Set-up Time
Write Command Hold Time
Write Command Pulse Width
WE Pulse Width (DQ Disable)
OE Command Hold Time
OE Precharge Time
t
0
7
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
WCS
t
10
10
10
10
10
10
10
10
0
13
10
10
13
10
10
13
13
0
WCH
t
7
WP
t
7
WPE
t
7
OEH
t
7
OEP
OCH
RWL
CWL
OE Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
t
t
t
7
7
7
t
0
11
11
DS
Data-in Hold Time
t
7
10
15
34
49
79
54
13
20
44
59
94
64
DH
OE to Data-in Delay Time
CAS to WE Delay Time
t
13
30
42
67
47
OED
t
10
10
10
10
CWD
Column Address to WE Delay Time
RAS to WE Delay Time
t
AWD
t
RWD
CAS Precharge WE Delay Time
t
CPWD
7/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
AC CHARACTERISTICS (3/3)
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13
MSM51V16405 MSM51V16405 MSM51V16405
F-50 F-60 F-70
Parameter
Symbol
Unit Note
Min.
5
Max. Max. Max.
Min.
Min.
CAS Active Delay Time from RAS
Precharge
t
t
5
5
ns
ns
ns
ns
ns
RPC
CSR
CHR
RAS to CAS Set-up Time
(CAS before RAS)
5
5
5
RAS to CAS Hold Time
(CAS before RAS)
t
10
10
10
10
10
10
10
10
10
WE to CAS Hold Time
(CAS before RAS)
t
WRP
WRH
WE Hold Time from RAS
(CAS before RAS)
t
RAS to WE Set-up Time
(Test Mode)
t
10
10
10
10
10
10
ns
ns
WTS
RAS to WE Hold Time (Test Mode)
t
WTH
8/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 2ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT)
are measured between VIH and VIL.
4. -50 is measured with a load circuit equivalent to 1 TTL load and 50pF, and -60/-70 is measured with a
load circuit equivalent to 1 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit,
then the access time is controlled by tCAC
.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit,
then the access time is controlled by tAA
.
7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the
open circuit condition and are not referenced to output voltage levels.
8. tCEZ, and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and
the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD
(Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify
write cycle and data out will contain data read from the selected cell; if neither of the above sets of
conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. In a test CA8 and CA9 are not used and
each DQ pin now access 4-bit locations. Since all 4 DQ pins are used, a total 16 data bits can be written
in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a
high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared
and the memory device returned to its normal operating state by performing a RAS-only refresh cycle
or a CAS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameter is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.
9/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
TIMING CHART
Read Cycle
tRC
tRAS
VIH
RAS
tRP
VIL
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
tASR tRAH
VIL
tRAL
tASC
tCAH
VIH
Address
VIL
Row
Column
tRCS
tRRH
VIH
WE
tAA
tRCH
VIL
tROH
tREZ
tOEA
VIH
OE
VIL
tCAC
tCEZ
tRAC
tOEZ
tCLZ
VOH
DQ
Valid Data-out
Open
VOL
“H” or “L”
Write Cycle (Early Write)
tRC
tRAS
VIH
RAS
tRP
tCRP
VIL
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
tASR tRAH
VIL
tRAL
tCAH
tASC
Column
tWCH
VIH
VIL
Address
Row
tCWL
tWCS
tWP
VIH
VIL
WE
OE
DQ
tRWL
VIH
VIL
tDH
Valid Data-in
tDS
VIH
VIL
Open
“H” or “L”
10/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
Read Modify Write Cycle
tRWC
tRAS
VIH
RAS
tRP
VIL
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
tASR tRAH
VIL
tCWL
tRWL
tCAH
tASC
VIH
VIL
Address
Row
Column
tRCS
tCWD
tRWD
tWP
VIH
VIL
WE
OE
tAWD
tAA
tOEH
tOEA
VIH
VIL
tOED
tOEZ
tDH
tCAC
tDS
tRAC
tCLZ
VI/OH
VI/OL
Valid
Data-out
Valid
Data-in
DQ
“H” or “L”
11/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
Fast Page Mode Read Cycle (Part-1)
tRASP
tRP
tRCD
tHPC
tRHCP
VIH
RAS
VIL
tCSH
tCP
tCP
tCRP
tCAS
tCAS
tCAS
VIH
VIL
CAS
tRAD
tRAH
tASC
tASC
tASR
tCAH
tASC
tCAH
tCAH
VIH
VIL
Row
Column
Column
Column
tOCH
Address
tRCS
tRRH
VIH
VIL
WE
OE
tAA
tCAC
tCHO
tOEP
tOEP
tCAC
tRAC
tAA
tOEA
tAA
VIH
VIL
tCPA
tDOH
tOEA
tOEA
tOEZ
tREZ
tOEZ
tCAC
VOH
VOL
Valid
Data-out
Valid *
Data-out
Valid *
Data-out
Valid Data-out
DQ
tCLZ
* : Same Data,
“H” or “L”
Fast Page Mode Read Cycle (Part-2)
tRP
tRASP
tRHCP
tHPC
VIH
RAS
VIL
tCRP
tCRP
tCSH
tRCD
tHPC
tCAS
tCP
tCP
tCAS
tCAS
VIH
VIL
CAS
tRAD
tASR
tASC
tASC
tCAH
tCAH
tRAH
tASC
tCAH
VIH
VIL
Address
Row
Column
Column
Column
tRCS
tRCS
VIH
VIL
WE
OE
tAA
tRCH
tRAC
tCPA
tAA
tWPE
tAA
tOEA
VIH
VIL
tCAC
tCEZ
tCAC
tWEZ
tCAC
tDOH
VOH
VOL
Valid
Data-out
Valid
Data-out
Valid Data-out
DQ
tCLZ
“H” or “L”
12/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
tCSH
tHPC
tHPC
VIH
RAS
VIL
tCRP
tRCD
tCP
tCP
tRSH
tCAS
tCAS
tCAS
VIH
VIL
CAS
tRAD
tRAH
tASC
tASC
tASR
tASC
tCAH
tCAH
tCAH
VIH
VIL
Address
Row
Column
tWCS tWCH
Column
tWCS
Column
tWCS
tWCH
tWCH
VIH
VIL
WE
OE
DQ
VIH
VIL
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
Valid
Data-in
Valid
Data-in
Valid
Data-in
“H” or “L”
Fast Page Mode Read Modify Write Cycle
tRASP
tRWD
tCPWD
VIH
RAS
VIL
tCRP
tRCD
tCP
tRWL
tCWD
VIH
VIL
tASC
CAS
tASC
tRAD
tHPRWC
tCAH
tCAH
tCPA
tASR
tCWL
tRAH
VIH
VIL
Address
Row
Column
Column
tCWD
tRCS
tRCS
VIH
VIL
WE
tAWD
tAWD
tAA
tWP
tAA
tWP
tDS
tDS
tRAC
tOEA
tOEA
VIH
VIL
OE
tOED
tOED
tOEH
tOEH
tCAC
tOEZ
tDH
tCAC
tOEZ
tDH
VI/OH
VI/OL
Valid
Data-out
Valid
Data-in
Valid
Data-out
Valid
Data-in
DQ
tCLZ
tCLZ
“H” or “L”
13/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
RAS-only Refresh Cycle
tRC
tRAS
VIH
RAS
tRP
VIL
tRPC
tCRP
VIH
CAS
VIL
tASR tRAH
VIH
Address
VIL
Row
tCEZ
VOH
DQ
Open
VOL
“H” or “L”
Note: WE, OE = “H” or “L”
CAS before RAS Refresh Cycle
tRP
tRC
tRAS
VIH
RAS
CAS
WE
tRPC
tCP
tRP
VIL
tCSR
tRPC
tCHR
VIH
VIL
tWRP
tWRH
tWRP
VIH
VIL
tCEZ
VOH
VOL
DQ
Open
Note: OE, Address = “H” or “L”
“H” or “L”
14/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRAS
VIH
RAS
VIL
tCRP
tRCD
tRSH
tRP
tRP
tCHR
VIH
CAS
tRAD
tRAH
VIL
tASR
tASC
tCAH
VIH
Address
Row
Column
VIL
tRCS
tCAC
tRAL
tRRH
VIH
VIL
WE
tREZ
tAA
tROH
tOEA
tWRP tWRH
tCEZ
VIH
VIL
OE
tRAC
tOEZ
tCLZ
VOH
VOL
DQ
Open
Valid Data-out
“H” or “L”
Hidden Refresh Write Cycle
tRC
tRC
tRAS
tRAS
VIH
RAS
VIL
tRP
tCRP
tRCD
tRSH
tRP
tCHR
VIH
CAS
tRAD
tRAH
VIL
tCAH
tASR
tASC
VIH
VIL
Address
Row
Column
tRAL
tRWL
tWP
VIH
VIL
WE
OE
DQ
tWCH
tWRP tWRH
tWCS
VIH
VIL
tDS
tDH
Valid Data-in
VIH
VIL
“H” or “L”
15/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
Test Mode-in Cycle
tRC
tRP
tRAS
VIH
RAS
tRPC
VIL
tCP
tCSR
tCHR
VIH
CAS
VIL
tWTS
tWTH
VIH
WE
VIL
tOFF
VIH
DQ
Open
Note: OE, Address = “H” or “L”
VIL
“H” or “L”
16/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
REVISION HISTORY
Page
Previous Current
Document
No.
Date
Description
Edition
Edition
FEDD51V16405F-01
FEDD51V16405F-02
May, 2001
Aug, 2002
–
–
Final edition 1
Deleted SOJ package
1, 2
1, 2
17/18
FEDD51V16405F-02
1
Semiconductor
MSM51V16405F
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that
the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special or
enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
18/18
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