MSM52V1017LP-12TS-K [OKI]
Standard SRAM, 128KX8, 120ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44;
| 型号： | MSM52V1017LP-12TS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Standard SRAM, 128KX8, 120ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2I0022-17-Y1
This version: Jan. 1998
Previous version: Aug. 1996
¡ Semiconductor
MSM52V1017LP
65,536-Word ¥ 16-Bit CMOS STATIC RAM
DESCRIPTION
The MSM52V1017LP is a 65,536-word by 16-bit CMOS static RAM featuring 3.0 V to 3.6 V power
supply operation in the range of –40°C to 85°C and direct LVCMOS input/output compatibility.
Since the circuitry is completely static, external clock and refreshing operations are unnecessary,
making this device very easy to use. The MSM52V1017LP can be used in the high-speed operation
of an access time 100 ns due to adopting a high-performance CMOS technology and in the low
current consumption of a standby current max. 50 mA when there is no chip selection. In addition,
theMSM52V1017LPisprovidedwithachipenablesignal(CE)suitedtotheexpansionofamemory
capacity, an output enable signal (OE) suited to the I/O bus line control, and a byte select signal (LB,
UB) that can independently control the input/output of a lower byte and an upper byte.
FEATURES
• 65,536-word ¥ 16-bit configuration
• Power supply voltage: 3.0 V to 3.6 V
• Fully static operation
• Operating temperature range: Ta = –40°C to 85°C
• (Input/Output) LVCMOS compatible
• 3-state output
• Data retention available at power supply voltage 2 V
• Equal to Mask ROM/OTP in supply pin layout
• Package options:
44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM52V1017LP-xxTS-K)
(TSOPII44-P-400-0.80-L) (Product : MSM52V1017LP-xxTS-L)
xx indicates speed rank.
PRODUCT FAMILY
Power Dissipation
Family
Access Time (Max.)
Operating (Max.)
180 mW
Standby (Max.)
MSM52V1017LP-10
MSM52V1017LP-12
100 ns
120 ns
0.18 mW
144 mW
1/9
¡ Semiconductor
MSM52V1017LP
PIN CONFIGURATION (TOP VIEW)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
CE
1
2
44 NC
43 LB
42 UB
1
2
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
CE
3
3
4
41
40
39
38
37
36
35
34
33
32
4
A14
A15
A13
WE
A8
5
5
6
6
7
7
8
8
9
9
A9
10
11
10
11
A11
A10
NC
NC 12
13
12 NC
13
VSS
OE 14
VSS
VSS
14 OE
31 I/O16
15
30
15
I/O1
I/O1
I/O15
I/O2 16
I/O3 17
I/O4 18
I/O5 19
I/O6 20
I/O7 21
I/O8 22
29 I/O14
28 I/O13
27 I/O12
26 I/O11
25 I/O10
24 I/O9
I/O14 29
I/O13 28
I/O12 27
I/O11 26
I/O10 25
I/O9 24
16 I/O2
17 I/O3
18 I/O4
19 I/O5
20 I/O6
21 I/O7
22 I/O8
23 VCC
VCC 23
44-Pin Plastic TSOP (II)
44-Pin Plastic TSOP (II)
(K Type)
(L Type)
Pin Name
Function
Address Input
A0 - A15
I/O1 - I/O16
CE
Data Input/Output
Chip Enable
WE
Write Enable
OE
Output Enable
Byte Data Select
Power Supply
No Connection
LB, UB
CC, VSS
NC
V
2/9
¡ Semiconductor
MSM52V1017LP
BLOCK DIAGRAM
A2
A3
VCC
VSS
Memory Array
256 Rows
256 Columns
¥ 16 Blocks
A0
A1
Row
Select
A8
A9
A11
A10
I/O1
Column I/O
Circuits
Column Select
:
:
Input
Data
Control
I/O8
I/O9
:
:
I/O16
A12 A14 A4 A6
A7 A15 A5 A13
:
:
CE
LB
UB
WE
OE
FUNCTION TABLE
Operating Mode CE
LB
X
H
L
UB
X
WE
X
OE
I/O1 - I/O8
High-Z
I/O9 - I/O16 Power Mode
L
X
X
L
High-Z
High-Z
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Active
Non Selectable
X
H
L
X
High-Z
H
H
H
H
H
H
H
H
L
Data Read
Data Read
High-Z
Data Read
High-Z
L
H
L
L
H
H
L
L
Data Read
High-Z
Read Cycle
H
L
H
H
H
X
X
X
High-Z
H
H
H
L
H
L
High-Z
High-Z
H
L
High-Z
High-Z
L
Data Write
Data Write
High-Z
Data Write
High-Z
Write Cycle
H
H
L
H
L
L
H
L
Data Write
X: Don't Care ("H" or "L")
3/9
¡ Semiconductor
MSM52V1017LP
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Power Supply Voltage
Pin Voltage
Symbol
VCC
Condition
Rating
Unit
–0.5 to 4.6
–0.5* to VCC + 0.5
0.7
V
V
Ta = 25°C, for VSS
VT
Power Dissipation
Operating Temperature
Storage Temperature
PD
Ta = 25°C
W
°C
°C
Topr
Tstg
—
—
–40 to 85
–55 to 125
* –1.2 V Min. for pulse width less than 30 ns.
Recommended Operating Conditions
Parameter
Symbol
VCC
VSS
VCCH
VIH
Condition
Min.
3.0
0
Typ.
—
0
Max.
Unit
V
3.6
Power Supply Voltage
—
—
0
3.6
V
Data Retention Voltage
Input High Voltage
Input Low Voltage
Load Capacitance
Fan Out
2
—
—
—
—
—
V
2.4
–0.3*
—
VCC + 0.3
0.4
V
VCC = 3.0 V to 3.6 V
VIL
V
CL
—
100
pF
—
N
LVCMOS
—
1
* –1.2 V Min. for pulse width less than 30 ns.
Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance
Input/Output Capacitance
Note:
Symbol
CI
Condition
VI = 0 V
Min.
Max.
10
Unit
pF
—
—
CI/O
VI/O = 0 V
10
pF
This parameter is periodically sampled and not 100% tested.
4/9
¡ Semiconductor
MSM52V1017LP
DC Characteristics
(VCC = 3.0 V to 3.6 V, Ta = –40°C to 85°C)
MSM52V1017LP
Unit
Parameter
Symbol
Condition
VIN = 0 to VCC
Min.
Typ.
Max.
Input Leakage Current
ILI
–1.0
—
1.0
mA
mA
CE = VIL or LB, UB = VIH
or OE = VIH or WE = VIL,
VOUT = 0 to VCC
Output Leakage Current
–1.0
—
1.0
ILO
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = –100 mA
V
CC – 0.2
—
—
—
—
V
V
I
OL = 100 mA
0.2
LB, UB ≥ VCC – 0.2 V,
CE ≥ VCC – 0.2 V
or
0 V £ CE £ 0.2 V,
VIN = 0 to VCC
ICCS
—
—
50
mA
Standby Power
Supply Current
LB, UB = VIH or
CE = VIL
ICCS1
—
—
—
—
0.6
mA
mA
LB, UB = VIL, CE = VIH,
V
IN = VIH / VIL,
TCYC = Min. cycle,
OUT = 0 mA
q
I
Operating Power
Supply Current
LB, UB £ 0.2 V,
CE ≥ VCC – 0.2 V,
VIH ≥ VCC – 0.2 V,
VIL £ 0.2 V,
ICCA
—
—
15
mA
TCYC = 1 ms,
I
OUT = 0 mA
q 52V1017LP-10 50 mA
52V1017LP-12 40 mA
AC Characteristics
Test Conditions
Parameter
Condition
Input Pulse Level
VIH = 2.4 V, VIL = 0.4 V
Input Rise and Fall Times
Input/Output Timing Level
Output Load
5 ns
1.4 V
CL = 100 pF, 1 LVCMOS
5/9
¡ Semiconductor
MSM52V1017LP
Read Cycle
(VCC = 3.0 V to 3.6 V, Ta = –40°C to 85°C)
MSM52V1017LP-10
MSM52V1017LP-12
Parameter
Symbol
Unit
Min.
100
—
—
—
—
—
10
10
10
5
Max.
—
Min.
120
—
—
—
—
—
10
10
10
5
Max.
—
Read Cycle Time
tRC
tAA
ns
ns
Address Access Time
100
100
100
100
50
120
120
120
120
60
tLB
ns
LB, UB Access Time
tUB
CE Access Time
tCO
ns
ns
OE Access Time
tOE
tLBLZ
tUBLZ
tCLZ
tOLZ
tLBHZ
tUBHZ
tCHZ
tOHZ
tOH
—
—
LB, UB to Output in Low-Z
ns
—
—
CE to Output in Low-Z
—
—
ns
ns
OE to Output in Low-Z
—
—
—
—
—
—
10
35
—
—
—
—
10
35
LB, UB to Output in High-Z
ns
35
35
CE to Output in High-Z
35
35
ns
ns
ns
OE to Output in High-Z
35
35
Output Hold Time from Address Change
—
—
tRC
ADDRESS
LB, UB
CE
tAA
tLBHZ, tUBHZ
tLB, tUB
tLBLZ, tUBLZ
tCO
tCHZ
tCLZ
OE
tOE
tOHZ
DOUT
Valid Data-out
tOLZ
tOH
Notes: 1. A read cycle occurs during the overlap of LB = "L" (or UB = "L"), CE = "H", OE = "L" and
WE = "H".
2. t
, t
, t
and t
are specified by the time when DATA is floating, not
LBHZ UBHZ CHZ
OHZ
defined by the output level.
6/9
¡ Semiconductor
MSM52V1017LP
Write Cycle
(VCC = 3.0 V to 3.6 V, Ta = –40°C to 85°C)
MSM52V1017LP-10
MSM52V1017LP-12
Parameter
Symbol
Unit
Min.
100
0
Max.
—
—
—
—
—
—
—
—
—
—
35
—
Min.
120
0
Max.
—
—
—
—
—
—
—
—
—
—
35
—
Write Cycle Time
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Setup Time
Data Hold Time
tWC
tAS
ns
ns
ns
ns
ns
ns
tWP
tWR
tDS
75
5
90
5
40
0
50
tDH
0
tLBW
tUBW
tCW
tAW
tWHZ
tWLZ
90
90
90
90
—
5
100
100
100
100
—
LB, UB to End of Write
ns
CE to End of Write
ns
ns
ns
ns
Address Valid to End of Write
WE to Output in High-Z
Output Active from End of Write
5
tWC
ADDRESS
tLBW, tUBW
LB, UB
tCW
CE
tAW
WE
tWR
tWLZ
tAS
tWP
DOUT
tDS
tDH
tWHZ
DIN
Data-in
Notes: 1. A write cycle occurs during the overlap of LB = "L" (or UB = "L"), CE = "H" and WE =
"L".
2. OE may be either of "H" or "L" in the write cycle.
3. t is specified from LB = "L" (or UB = "L"), CE = "H" or WE = "L", whichever occurs last.
AS
4. t
is an overlap time of LB = "L" (or UB = "L"), CE = "H" and WE = "L".
WP
5. t , t and t
are specified from LB = "H" (or UB = "H"), CE = "L" or WE = "H",
WR DS
DH
whichever occurs first.
6. t is specified by the time when DATA output is floating, not defined by the output
WHZ
level.
7. When I/O pins are in the output mode, don't apply the inverted input signal to the
output pins.
7/9
¡ Semiconductor
MSM52V1017LP
Data Retention Characteristics
(Ta = –40°C to 85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
LB, UB ≥ VCC – 0.2 V,
CE ≥ VCC – 0.2 V
or
0 V £ CE £ 0.2 V,
VIN = 0 to VCC
Data Retention Power
Supply Voltage
VCCH
2.0
—
—
V
VCC = 3 V,
LB, UB ≥ VCC – 0.2 V,
CE ≥ VCC – 0.2 V
or
Data Retention Power
Supply Current
ICCH
—
—
40*
mA
0 V £ CE £ 0.2 V,
VIN = 0 to VCC
Chip Deselect to Data
Retention Time
tCDR
tR
—
—
0
—
—
—
—
ns
Operation Recovery Time
50
ms
* 5 mA Max. when Ta = 0°C to 40°C.
LB, UB Control
tCDR
Data Retention Mode
tR
VCC
3.0 V
VIH
VCCH
LB, UB
0 V
LB, UB ≥ VCC – 0.2 V
CE Control
Data Retention Mode
VCC
3.0 V
tCDR
tR
CE
VCCH
VIL
CE £ 0.2 V
0 V
8/9
¡ Semiconductor
PACKAGE DIMENSIONS
TSOPII44-P-400-0.80-K
MSM52V1017LP
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
Solder plate thickness
Package weight (g)
5 mm or more
0.54 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
9/9
相关型号：
MSM52V1017LP-12TS-L
Standard SRAM, 128KX8, 120ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44
OKI
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