MSM54V16273 [OKI]
262,144-Word x 16-Bit Multiport DRAM; 262,144字×16位的多端口DRAM
| 型号： | MSM54V16273 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 262,144-Word x 16-Bit Multiport DRAM |
| 文件： | 总42页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2L0025-17-Y1
This version: Jan. 1998
Previous version: Dec. 1996
¡ Semiconductor
MSM54V16273
262,144-Word ¥ 16-Bit Multiport DRAM
DESCRIPTION
The MSM54V16273 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit
dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and
asynchronously.
It supports three types of operations: random access to RAM port, high speed serial access to
SAM port, and bidirectional transfer of data between any selected row in the RAM port and the
SAMport.InadditiontotheconventionalmultiportDRAMoperatingmodes,theMSM54V16273
features block write, flash write functions, extended page mode on the RAM port, a split data
transfer capability, and programmable stops on the SAM port. The SAM port requires no refresh
operation because it uses static CMOS flip-flops.
FEATURES
• Single power supply: 3.3 V ±0.3 V
• Full TTL compatibility
• Multiport organization
RAM : 256K word ¥ 16 bits
SAM : 512 word ¥ 16 bits
• Extended page mode
• Write per bit
• RAS only refresh
• CAS before RAS refresh
• CAS before RAS self-refresh
• Hidden refresh
• Serial read/write
• 512 tap location
• Programmable stops
• Bidirectional data transfer
• Split transfer
• Persistent write per bit
• Byte read/write
• Masked flash write
• Masked block write (8 columns)
• Package options:
• Masked write transfer
• Refresh: 512 cycles/8 ms
64-pin 525 mil plastic SSOP
(SSOP64-P-525-0.80-K) (Product:MSM54V16273-xxGS-K)
70/64-pin 400 mil plastic TSOP (Type II)(TSOPII70/64-P-400-0.65-K)(Product:MSM54V16273-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time
Cycle Time
RAM SAM
Power Dissipation
Family
RAM
60 ns
70 ns
SAM
Operating
Standby
8 mA
MSM54V16273-60
MSM54V16273-70
18 ns 120 ns 22 ns
20 ns 140 ns 22 ns
160 mA
150 mA
8 mA
1/42
¡ Semiconductor
MSM54V16273
PIN CONFIGURATION (TOP VIEW)
VCC
TRG
VSS
SDQ0
DQ0
SDQ1
DQ1
VCC
1
2
3
4
5
6
7
8
9
70 SC
69 SE
68 VSS
VCC
TRG
VSS
SDQ0
DQ0
SDQ1
DQ1
VCC
1
2
3
4
5
6
7
8
9
64 SC
63 SE
62 VSS
67 SDQ15
66 DQ15
65 SDQ14
64 DQ14
63 VCC
62 SDQ13
61 DQ13
60 SDQ12
59 DQ12
58 VSS
61 SDQ15
60 DQ15
59 SDQ14
58 DQ14
57 VCC
56 SDQ13
55 DQ13
54 SDQ12
53 DQ12
52 VSS
51 SDQ11
50 DQ11
49 SDQ10
48 DQ10
47 VCC
46 SDQ9
45 DQ9
44 SDQ8
43 DQ8
42 VSS
41 DSF
40 NC
39 CASU
38 QSF
37 A0
36 A1
35 A2
34 A3
33 VSS
SDQ2
DQ2 10
SDQ3 11
DQ3 12
VSS 13
SDQ4 14
DQ4 15
SDQ5 16
SDQ2
DQ2 10
SDQ3 11
DQ3 12
VSS 13
SDQ4 14
DQ4 15
SDQ5 16
DQ5 17
VCC 18
SDQ6 19
DQ6 20
SDQ7 21
DQ7 22
VSS 23
CASL 24
WE 25
57 SDQ11
56 DQ11
55 SDQ10
DQ5 20
VCC 21
SDQ6 22
DQ6 23
SDQ7 24
DQ7 25
VSS 26
CASL 27
WE 28
RAS 29
A8 30
51 DQ10
50 VCC
49 SDQ9
48 DQ9
47 SDQ8
46 DQ8
45 VSS
44 DSF
43 NC
42 CASU
41 QSF
40 A0
39 A1
38 A2
RAS 26
A8 27
A7 28
A6 29
A5 30
A7 31
A6 32
A5 33
A4 34
A4 31
VCC 32
37 A3
VCC 35
36 VSS
64-Pin Plastic SSOP
70/64-Pin Plastic TSOP (II)
(K Type)
Pin Name
A0 - A8
DQ0 - DQ15
SDQ0 - SDQ15
RAS
Pin Name
Function
Address Input
Function
Serial Clock
SC
SE
RAM Inputs/Outputs
SAM Port Enable
DSF
QSF
VCC
VSS
NC
SAM Inputs/Outputs
Special Function Input
Special Function Output
Power Supply (3.3 V)
Ground (0 V)
Row Address Strobe
Column Address Strobe Lower
Column Address Strobe Upper
Write Enable
CASL
CASU
WE
No Connection
TRG
Transfer/Output Enable
Note: The same power supply voltage must be provided to every V pin, and the same GND
CC
voltage level must be provided to every V pin.
SS
2/42
Column
Address
Buffer
Block Write
Control
Column Mask
Register
Column Decoder
Sense Amp.
RAM Input
Buffer
I/O Control
Color Register
Mask Register
DQ 0 - 15
RAM Output
Buffer
Row
Address
Buffer
512 ¥ 512 ¥ 16
RAM ARRAY
Flash Write
Control
SAM Input
A0 - A8
Refresh
Counter
RAS
Gate
SAM
Gate
SAM
Buffer
CASU / CASL
SDQ 0 - 15
SAM Output
Buffer
TRG
WE
DSF
SC
Timing
Serial Decoder
Generator
SAM
Address
Buffer
SAM Address
SE
QSF
Counter
SE
VCC
VSS
SAM Stop
Control
¡ Semiconductor
MSM54V16273
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Note: 1)
Parameter
Input Output Voltage
Output Current
Symbol
VT
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
—
Rating
–0.5 to 4.6
50
Unit
V
IOS
mA
W
Power Dissipation
PD
1
Topr
Tstg
Operating Temperature
Storage Temperature
0 to 70
–55 to 150
°C
—
°C
Recommended Operating Conditions
(Ta = 0°C to 70°C) (Note: 2)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VCC
Min.
3.0
Typ.
3.3
—
Max.
3.6
Unit
V
V
V
VIH
2.0
VCC + 0.3
0.8
VIL
–0.3
—
Capacitance
(VCC = 3.3 V 0.3 Vꢀ f = 1 MHꢁꢀ Ta = 25°C)
Parameter
Input Capacitance
Symbol
Ci
Min.
—
Max.
Unit
pF
6
7
7
Input/Output Capacitance
Output Capacitance
Cio
—
pF
Co(QSF)
—
pF
Note: This parameter is periodically sampled and is not 100% tested.
DC Characteristics 1
Parameter
Output "H" Level Voltage
Output "L" Level Voltage
Symbol
VOH
Condition
IOH = –2 mA
IOL = 2 mA
Min.
2.4
Max.
—
Unit
V
VOL
—
0.4
0 £ VIN £ VCC
All other pins not
under test = 0 V
Input Leakage Current
Output Leakage Current
ILI
–10
–10
10
10
mA
0 £ VOUT £ VCC
Output Disable
ILO
4/42
¡ Semiconductor
MSM54V16273
DC Characteristics 2
(VCC = 3.3 V 0.3 Vꢀ Ta = 0°C to 70°C)
-60
Max.
120
160
8
-70
Max.
110
150
8
Item (RAM)
SAM
Symbol
Unit Note
Operating Current
Standby
Active
ICC1
3ꢀ 4
17
(RASꢀ CAS Cyclingꢀ tRC = tRC min.)
Standby Current
I
CC1A
Standby
Active
ICC2
(RASꢀ CAS = VIH)
ICC2
ICC3
ICC3
ICC4
ICC4
ICC5
ICC5
ICC6
ICC6
ICC7
ICC7
ICC8
ICC8
A
55
55
3ꢀ 4
3ꢀ 4
17
RAS Only Refresh Current
(RAS Cyclingꢀ CAS = VIHꢀ tRC = tRC min.)
Page Mode Current
Standby
Active
120
160
120
160
100
140
110
150
110
150
110
150
110
150
110
150
90
A
Standby
Active
3ꢀ 4
(RAS = VILꢀ CAS Cyclingꢀ tPC = tPC min.)
CAS before RAS Refresh Current
(RAS Cyclingꢀ CAS before RASꢀ tRC = tRCmin.)
Data Transfer Current
A
18
mA
Standby
Active
3ꢀ 4
A
130
100
140
100
140
100
140
3ꢀ 4
3ꢀ 4
17
Standby
Active
(RASꢀ CAS Cyclingꢀ tRC = tRC min.)
Flash Write Current
A
Standby
Active
3ꢀ 4
3ꢀ 4
3ꢀ 4
3ꢀ 4
(RASꢀ CAS Cyclingꢀ tRC = tRC min.)
Block Write Current
A
Standby
Active
(RASꢀ CAS Cyclingꢀ tRC = tRC min.)
CAS before RAS Self-Refresh Current
(RASꢀ CAS £ 0.2 V)
A
Standby
ICC9
1
1
3ꢀ 4
5/42
¡ Semiconductor
MSM54V16273
AC Characteristics (1/3)
-60
-70
Parameter
Symbol
Unit Note
Max.
Min.
104
140
25
70
—
—
—
—
0
Max.
—
—
—
—
60
30
15
35
15
35
—
10k
100k
—
—
10k
42
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
124
170
30
74
—
—
—
—
0
Random Read or Write Cycle Time
Read Modify Write Cycle
tRC
tRWC
tHPC
tPRWC
tRAC
tAA
—
—
—
—
70
35
20
40
17
35
—
10k
100k
—
—
10k
50
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write Cycle Time
Access Time from RAS
ns
ns
ns 8ꢀ 14
ns 8ꢀ 14
ns 8ꢀ 15
ns 8ꢀ 15
Access Time from Column Address
Access Time from CAS
tCAC
tCPA
tOFF
tT
Access Time from CAS Precharge
Output Buffer Turn-off Delay
Transition Time (Rise and Fall)
RAS Precharge Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
7
2
2
tRP
40
60
60
15
45
10
15
12
30
5
50
70
70
20
55
10
15
12
35
10
10
0
RAS Pulse Width
tRAS
tRASP
tRSH
tCSH
tCAS
tRCD
tRAD
tRAL
tCRP
tCP
RAS Pulse Width (Fast Page Mode Only)
RAS Hold Time
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time
14
14
RAS to Column Address Delay Time
Column Address to RAS Lead Time
CAS to RAS Precharge Time
CAS Precharge Time (Fast Page Mode)
Row Address Set-up Time
10
0
tASR
tRAH
tASC
tCAH
tAR
Row Address Hold Time
10
0
10
0
Column Address Set-up Time
Column Address Hold Time
Column Address Hold Time referenced to RAS
Read Command Set-up Time
Read Command Hold Time
10
50
0
10
55
0
tRCS
tRCH
tRRH
tCRL
tRCL
tCOH
tWCS
tWCH
tWCR
tWP
0
0
11
11
Read Command Hold Time referenced to RAS
CAS "H" to RAS "H" Lead Time
RAS "H" to CAS "H" Lead Time
Data Output Hold after CAS Low
Write Command Set-up Time
Write Command Hold Time
0
0
0
0
0
0
3
3
19
13
0
0
10
50
10
15
15
10
55
10
15
15
Write Command Hold Time referenced to RAS
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
tRWL
tCWL
6/42
¡ Semiconductor
MSM54V16273
AC Characteristics (2/3)
-60
-70
Parameter
Symbol
Unit Note
Max.
Min.
0
Max.
—
—
—
—
—
—
—
—
15
15
—
—
—
—
—
8
Min.
0
Data Set-up Time
tDS
tDH
—
—
—
—
—
—
—
—
20
15
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
Data Hold Time
10
50
80
50
35
0
12
55
90
55
40
0
Data Hold Time referenced to RAS
RAS to WE Delay Time
tDHR
tRWD
tAWD
tCWD
tDZC
tDZO
tOEA
tOEZ
tOEH
tROH
tCSR
tCHR
tRPC
tREF
tWSR
tRWH
tFSR
tRFH
tFHR
tFSC
tCFH
tMS
13
13
13
Column Address to WE Delay Time
CAS to WE Delay Time
Data to CAS Delay Time
Data to TRG Delay Time
0
0
Access Time from TRG
—
0
—
0
Output Buffer Turn-off Delay from TRG
TRG Command Hold Time
10
10
5
10
15
5
RAS Hold Time referenced to TRG
CAS Set-up Time for CAS before RAS Cycle
CAS Hold Time for CAS before RAS Cycle
RAS Precharge to CAS Active Time
Refresh Period
10
0
10
0
—
0
—
0
WE Set-up Time
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10k
10k
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10k
10k
—
—
WE Hold Time
10
0
10
0
DSF Set-up Time referenced to RAS
DSF Hold Time referenced to RAS (1)
DSF Hold Time referenced to RAS (2)
DSF Set-up Time referenced to CAS
DSF Hold Time referenced to CAS
Write Per Bit Mask Data Set-up Time
Write Per Bit Mask Data Hold Time
RAS Pulse Width (CAS before RAS Self-Refresh)
RAS Precharge Time (CAS before RAS Self-Refresh)
CAS Hold Time (CAS before RAS Self-Refresh)
TRG High Set-up Time
10
50
0
10
55
0
10
0
10
0
tMH
10
100
120
0
10
100
140
0
tRASS
tRPS
tCHS
tTHS
tTHH
tTLS
tTLH
tRTH
tATH
tCTH
0
0
TRG High Hold Time
10
0
10
0
TRG Low Set-up Time
TRG Low Hold Time
10
50
20
15
10
60
25
20
TRG Low Hold Time referenced to RAS
TRG Low Hold Time referenced to Column Address
TRG Low Hold Time referenced to CAS
7/42
¡ Semiconductor
AC Characteristics (3/3)
Parameter
MSM54V16273
-60
-70
Symbol
Unit Note
Max.
Min.
40
20
60
30
20
5
Max.
—
—
—
—
—
—
—
—
30
—
—
—
15
—
15
—
—
15
—
—
20
20
30
70
—
—
—
—
—
—
—
—
—
Min.
50
20
70
35
20
5
TRG to RAS Precharge Time
TRG Precharge Time
tTRP
tTP
—
—
—
—
—
—
—
—
40
—
—
—
17
—
17
—
—
15
—
—
25
25
35
75
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RAS to First SC Delay Time (Read Transfer)
Column Address to First SC Delay Time
CAS to First SC Delay Time (Read Transfer)
Last SC to TRG Lead Time
tRSD
tASD
tCSD
tTSL
tTSD
tSRS
tSDZ
tSCC
tSC
TRG to First SC Delay Time (Read Transfer)
Last SC to RAS Set-up Time (Serial Input)
Serial Output Buffer Turn-off Delay from RAS
SC Cycle Time
10
20
10
18
5
10
25
10
20
5
10
SC Pulse Width (SC High Time)
SC Precharge Time (SC Low Time)
Access Time from SC
tSCP
tSCA
tSOH
tSEA
tSE
5
5
—
3
—
5
9
19
9
Serial Output Hold Time from SC
Access Time from SE
—
10
10
0
—
10
10
0
SE Pulse Width
SE Precharge Time
tSEP
tSEZ
tSTS
tSTH
tSQD
tTQD
tCQD
tRQD
tSDD
tSDS
tSDH
tSZE
tSZS
tSWS
tSWH
tSWIS
tSWIH
Serial Output Buffer Turn-off Delay from SE
Split Transfer Set-up Time
10
20
20
—
—
—
—
30
0
25
25
—
—
—
—
40
0
Split Transfer Hold Time
SC-QSF Delay Time
TRG-QSF Delay Time
CAS-QSF Delay Time
RAS-QSF Delay Time
RAS to Serial Input Delay Time
Serial Input Set-up Time
Serial Input Hold Time
10
0
10
0
Serial Input to SE Delay Time
Serial Input to First SC Delay Time
Serial Write Enable Set-up Time
Serial Write Enable Hold Time
Serial Write Disable Set-up Time
Serial Write Disable Hold Time
0
0
0
0
10
0
10
0
10
10
8/42
¡ Semiconductor
MSM54V16273
Notes: 1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage
to the device.
2. All voltages are referenced to V .
SS
3. These parameters depend on the cycle rate.
4. Theseparametersdependonoutputloading.Specifiedvaluesareobtainedwiththe
output open.
5. An initial pause of 200 ms is required after power up followed by any 8 RAS cycles
(TRG = "high") and any 8 SC cycles before proper device operation is achieved.
In the case of using an internal refresh counter, a minimum of 8 CAS before RAS
cycles instead of 8 RAS cycles are required.
6. AC measurements assume t = 5 ns.
T
7. V (Min.)andV (Max.)arereferencelevelsformeasuringtimingofinputsignals.
IH
IL
Also, transition times are measured between V and V .
IH
IL
8. RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF.
DOUT reference levels : V /V = 2.0 V/0.8 V.
OH
OL
9. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.
DOUT reference levels : V /V = 2.0 V/0.8 V.
OH
OL
10. t
(Max.), t
(Max.), t
(Max.) and t
(Max.) define the time at which the
OFF
OEZ
SDZ
SEZ
outputsachievetheopencircuitcondition, andarenotreferencedtooutputvoltage
levels. This parameter is sampled and not 100% tested.
11. Either t
or t
must be satisfied for a read cycle.
RCH
RRH
12. These parameters are referenced to CAS leading edge of early write cycles, and to
WE leading edge in TRG controlled write cycles and read modify write cycles.
13. t
, t
, t
and t
are not restrictive operating parameters.
AWD
WCS RWD CWD
They are included in the data sheet as electrical characteristics only.
If t ≥ t (Min.), the cycle is an early write cycle, and the data out pin will
WCS
WCS
remain open circuit throughout the entire cycle; If t
≥t
(Min.), t
≥t
RWD RWD
CWD CWD
(Min.) and t
≥t
(Min.), the cycle is a read modify write cycle, and the data
AWD AWD
out will contain data read from the selected cell; If neither of the above sets of
conditions are satisfied, the condition of the data out is indeterminate.
14. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RCD
RAC
t
(Max.)isspecifiedasareferencepointonly:Ift
(Max.) limit, then access time is controlled by t
isgreaterthanthespecified
RCD
RCD
t
.
RCD
CAC
15. Operation within the t
(Max.) limit ensures that t
(Max.) can be met. t
RAD
RAC
RAD
RAD
(Max.)isspecifiedasareferencepointonly:Ift
isgreaterthanthespecifiedt
RAD
(Max.) limit, then access time is controlled by t
.
AA
16. Input levels at the AC testing are 3.0 V/0 V.
17. Address (A0 - A8) may be changed two times or less while RAS = V .
IL
18. Address (A0 - A8) may be changed once or less while CAS = V and RAS = V .
IH
IL
19. This is guaranteed by design. (t
/t
= t
/t
- output transition time)
SOH COH
SCA CAC
This parameter is not 100% tested.
9/42
¡ Semiconductor
MSM54V16273
TIMING WAVEFORM
Read Cycle (Outputs Controlled by RAS)
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
CASL
CASU
tCSH
tRSH
tCAS
tCRP
tRCD
tCRL
tAR
tRAD
tRAH
tRAL
tASC
tASR
tCAH
Address
DSF
Row
Column
tFHR
tFSR tRFH
tFSC
tCFH
tRCS
tRCH
tRRH
tOFF
WE
tCAC
tAA
Open
Open
DQ0 - 7
Valid Data
Valid Data
tRAC
DQ8 - 15
tROH
tTHS
tTHH
tOEA
tOEZ
TRG
"H" or "L"
10/42
¡ Semiconductor
MSM54V16273
Read Cycle (Outputs Controlled by CAS)
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
CASL
tRCL
tCSH
tRSH
tCAS
tCRP
tRCD
CASU
tRCL
tAR
tRAD
tRAH
tRAL
tASR
Row
tASC
tCAH
Address
Column
tFHR
tFSR tRFH
tFSC
tCFH
DSF
tRCS
tRRH
WE
tRCH
tOFF
tCAC
tAA
Open
Open
DQ0 - 7
Valid Data
Valid Data
tRAC
DQ8 - 15
tROH
tTHS
tTHH
tOEA
tOEZ
TRG
"H" or "L"
11/42
¡ Semiconductor
MSM54V16273
Extended Page Mode Read Cycle
tRASP
tRP
RAS
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tRCD
tCAS
tCP
tCP
CASL
CASU
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tRCD
tCAS
tCP
tCP
tAR
tRAD
tRAH
tRAL
tASR
tASC tCAH
Column
tASC tCAH
Column
tASC tCAH
Column
Address
DSF
Row
tFHR
tFSR tRFH
tFSC tCFH
tFSC tCFH
tFSC tCFH
tRCS
tRCS
tRCS
tRRH
tRCH
tRCH
WE
tRCH
tCAC
tAA
tCAC
tCOH
tCAC
tCOH
tOFF
Valid
Data
Valid
Data
tAA
DQ0 - 7
Open
Open
Valid Data
Valid Data
Valid Data
tAA
tCPA
tRAC
tCPA
Valid
Data
Valid
Data
DQ8 - 15
Valid Data
tTHS
tTHH
tOEA
tOEZ
tOEA
TRG
"H" or "L"
12/42
¡ Semiconductor
MSM54V16273
Write Cycle Function Table
RAS Falling Edge
CAS Falling Edge
Code
A
C
D
B
E
Function
DSF WE
DQ
DSF
DQ
RWM
BWM
FWM
RW
0
0
1
0
0
1
1
0
0
0
1
1
1
1
Write Mask
0
1
X
0
1
0
1
Valid Data
Column Mask
X
Masked Write (New/Old)
Masked Block Write (New/Old)
Masked Flash Write (New/Old)
Normal Write
Write Mask
Write Mask
X
X
X
X
Valid Data
Column Mask
Write Mask Data
Color Data
BW
Block Write
LMR
LCR
Load Mask Register
Load Color Register
WRITE MASK DATA: "Low" = Mask, "High" = No Mask
Column Mask Data
DQ0 - 15
DQ0
Column Mask Data
Column 0 (A0 = 0ꢀ A1 = 0ꢀ A2 = 0)
DQ1
Column 1 (A0 = 1ꢀ A1 = 0ꢀ A2 = 0)
Column 2 (A0 = 0ꢀ A1 = 1ꢀ A2 = 0)
Column 3 (A0 = 1ꢀ A1 = 1ꢀ A2 = 0)
Column 4 (A0 = 0ꢀ A1 = 0ꢀ A2 = 1)
Column 5 (A0 = 1ꢀ A1 = 0ꢀ A2 = 1)
Column 6 (A0 = 0ꢀ A1 = 1ꢀ A2 = 1)
Column 7 (A0 = 1ꢀ A1 = 1ꢀ A2 = 1)
Column 0 (A0 = 0ꢀ A1 = 0ꢀ A2 = 0)
Column 1 (A0 = 1ꢀ A1 = 0ꢀ A2 = 0)
Column 2 (A0 = 0ꢀ A1 = 1ꢀ A2 = 0)
Column 3 (A0 = 1ꢀ A1 = 1ꢀ A2 = 0)
Column 4 (A0 = 0ꢀ A1 = 0ꢀ A2 = 1)
Column 5 (A0 = 1ꢀ A1 = 0ꢀ A2 = 1)
Column 6 (A0 = 0ꢀ A1 = 1ꢀ A2 = 1)
Column 7 (A0 = 1ꢀ A1 = 1ꢀ A2 = 1)
DQ2
DQ3
Low : Mask
Lower Byte
DQ4
High : No Mask
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Low : Mask
Upper Byte
High : No Mask
13/42
¡ Semiconductor
MSM54V16273
Early Write Cycle
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
CASL
tCSH
tRSH
tCAS
tCRP
tRCD
CASU
tAR
tRAD
tRAH
tRAL
tASR
tASC
tCAH
Address
DSF
Row
Column
tFHR
tFSR
tRFH
tFSC
tCFH
A
B
tCWL
tRWL
tWSR tRWH
C
tWP
WE
tWCR
tWCS
tWCH
tDHR
tDS
tMS
tMH
tDH
DQ0 - 7
D
D
E
E
tDHR
tDS
tMS
tMH
tDH
DQ8 - 15
tTHS
tTHH
TRG
"H" or "L"
14/42
¡ Semiconductor
MSM54V16273
Late Write Cycle
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
CASL
tCSH
tRSH
tCAS
tCRP
tRCD
CASU
tAR
tRAD
tRAH
tRAL
tASR
tASC
tCAH
Address
DSF
Row
Column
tFHR
tFSC
tFSR
tRFH
tCFH
A
B
tCWL
tRWL
tWSR tRWH
C
tRCS
tWP
WE
tWCR
tDHR
tMS
tMH
tDS
tDH
DQ0 - 7
D
D
E
E
tDHR
tMS
tMH
tDS
tDH
DQ8 - 15
tTHS
tOEH
TRG
"H" or "L"
15/42
¡ Semiconductor
MSM54V16273
Read Modify Write Cycle
tRWC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
CASL
tCSH
tRSH
tCAS
tCRP
tRCD
CASU
tAR
tRAD
tRAH
tRAL
tASR
Row
tASC
tCAH
Address
DSF
Column
tAWD
tFHR
tFSR
tRFH
tFSC
tCFH
A
B
tCWL
tRWL
tWP
tWSR tRWH
C
tRCS
tRWD
tRAC
tCWD
WE
tCAC
tMS
tMH tDZC
tDS
tDH
Valid
DQ0 - 7
D
D
E
E
Data
tMS
tMH
tDS
tDH
Valid
Data
DQ8 - 15
tDZO
tOEZ
tTHS
tTHH
tOEA
tOEH
TRG
"H" or "L"
16/42
¡ Semiconductor
MSM54V16273
Fast Page Mode Early Write Cycle
tRASP
tRP
RAS
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tRCD
tCAS
tCP
tCP
CASL
CASU
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tRCD
tCAS
tCP
tCP
tAR
tRAL
tCAH
tRAD
tRAH
tASR
tASC
tCAH
tASC
tCAH
tASC
Address
DSF
Row
Column
Column
Column
tFHR
tFSC tCFH
tFSR
tRFH
tFSC tCFH
tFSC tCFH
B
A
B
B
tCWL
tCWL
tCWL
tWP
tWSR
tRWH
tWP
tWP
WE
DQ0 - 7
C
tMS
tMH
tDS tDH
E
tDS tDH
E
tDS
tDH
tDS
tDH
D
D
E
E
E
E
tMS
tMH
tDS
tDH
tDS
tDH
DQ8 - 15
tTHS
tTHH
TRG
"H" or "L"
17/42
¡ Semiconductor
MSM54V16273
Fast Page Mode Read Modify Write Cycle
tRASP
tRP
RAS
tCSH
tPRWC
tCAS
tRSH
tCAS
tCRP
tRCD
tCAS
tCP
tCP
CASL
CASU
tCSH
tPRWC
tCAS
tRSH
tCAS
tCRP
tRCD
tCAS
tCP
tCP
tAR
tRAL
tCAH
tRAD
tASC
tASR
tRAH
tCAH
Column
tASC
tCAH
tASC
Address
DSF
Row
Column
Column
tFHR
tFSC tCFH
tFSR
tRFH
tFSC tCFH
B
tFSC tCFH
B
A
B
tCWL
tAWD
tCWL
tAWD
tCWL
tAWD
tWSR
tRWH
WE
C
tWP
tCWD
tWP
tCWD
tWP
tCWD
tRCS
tCAC
tCAC
tCAC
tDH
tDH
tDH
tAA
tAA
tAA
tMS
tMH
tDS
tDS
tDS
Out In
Out In
Out In
DQ0 - 7
D
D
tMS
tMH
Out In
Out In
Out In
DQ8 - 15
tOEZ
tOEZ
tOEZ
tTHS
tOEA
tOEA
tOEA
tTHH
TRG
"H" or "L"
18/42
¡ Semiconductor
MSM54V16273
RAS Only Refresh Cycle
tRC
tRAS
tRP
RAS
tCRP
tRPC
CASL/U
tASR
tRAH
Address
DSF
Row
tFSR
tRFH
WE
Open
DQ0 - 15
TRG
tTHS
tTHH
"H" or "L"
19/42
¡ Semiconductor
MSM54V16273
CAS before RAS Refresh Cycle
tRC
tRP
tRAS
tRP
RAS
tRPC
tCSR tCHR
tRPC
CASL/U
Address
DSF
Inhibit Falling Transition
tASR
tRAH
A
B
tFSR
tRFH
tWSR tRWH
C
WE
DQ0 - 15
TRG
tOFF
Open
"H" or "L"
Note:
The type of CBR operations are determined by the logic states of "A", "B" and "C".
CBR Cycle Function Table
RAS Falling Edge
Code
Function
A
B
0
C
1
CBRR
CBRS
CBRN
X
CBR Refresh (Reset All Options)
CBR Refresh (Set STOP Address)
CBR Refresh (No Reset Options)
STOP Address
X
1
0
1
1
20/42
¡ Semiconductor
MSM54V16273
CAS before RAS Self-Refresh Cycle
tRP
tRASS
tRPS
RAS
tRPC
tRPC tCSR
tCHS
CASL/U
tOFF
Open
DQ0 - 15
"H" or "L"
Note:
Address, DSF, WE, TRG = "H" or "L"
21/42
¡ Semiconductor
MSM54V16273
Hidden Refresh Cycle
tRC
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tRSH
tCHR
CASL/U
tAR
tRAD
tRAH
tRAL
tCAH
tASR
tASC
tASR
Row
tRAH
Address
DSF
Column
tCFH
A
tFHR
tFSC
tFSR
tFSR
tRFH
tRFH
B
tWSR
tRCS
tRWH
WE
C
tRRH
tCAC
tAA
tOFF
Open
DQ0 - 15
TRG
Valid Data
tRAC
tTHS tTHH
tOEA
tOEZ
"H" or "L"
Note:
The type of CBR operations are determined by the logic states of "A", "B" and "C".
22/42
¡ Semiconductor
MSM54V16273
Read Transfer 1
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tRCD
CASL/U
tAR
tRAD
tRAH
tRAL
tASC
SAM Start
tASR
tCAH
Address
DSF
Row
tFSR tRFH
tWSR tRWH
WE
tASD
tCSD
DQ0 - 15
TRG
Open
tRSD
tTRP
tTP
tTLS
tTLH
tSRS
tTSD
tSCC
tSC
tSCP
tSC
SC
Note 2
tSCA
tSOH
tSIS
tSZS
tSCA
tSIH
Din
SDQ0 - 15
QSF
Data Out
tTQD
tCQD
tRQD
Note 3
Note 3
"H" or "L"
Note 1: SE = "L"
Note 2: There must be no rising transitions
Note 3: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
23/42
¡ Semiconductor
MSM54V16273
Read Transfer 2 (Real Time Read Transfer)
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tRCD
CASL/U
tAR
tRAD
tRAH
tRAL
tASC
tASR
Row
tCAH
Address
DSF
SAM Start
tFSR tRFH
tWSR tRWH
WE
tCTH
tATH
DQ0 - 15
TRG
Open
tTRP
tTP
tTLS
tRTH
tSCC
tTSL
tTSD
tSCP
tSC
SC
tSCA
tSOH
tSCA
tSOH
SDQ0 - 15
Data Out
Data Out
Data Out
Data Out
tTQD
Note 2
Note 2
QSF
"H" or "L"
Note 1: SE = "L"
Note 2: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
24/42
¡ Semiconductor
MSM54V16273
Split Read Transfer
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tRCD
CASL/U
tAR
tRAD
tRAH
tRAL
tASC
SAM Start Sj
tASR
tCAH
Address
DSF
Row
tFSR tRFH
tWSR tRWH
WE
tCTH
tATH
DQ0 - 15
TRG
Open
tRTH
tTLS
tTLH
tSTS
tSCC
tSCP
tSC
SC
STOP i
tSCA
tSOH
S i
tSCA
tSOH
STOP
j - 1
STOP j
S j
SDQ0 - 15
QSF
Data Out
tSQD
Data Out
Data Out
Data Out
Data Out
tSQD
Data Out
Note 2
Note 2
Note 2
"H" or "L"
Note 1: SE = "L"
Note 2: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
Note 3: Si is the SAM start address in before SRT
Note 4: STOP i and STOP j are programmable stop addresses
25/42
¡ Semiconductor
MSM54V16273
Masked Write Transfer
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tRCD
CASL/U
tAR
tRAD
tRAH
tRAL
tASC
SAM Start
tASR
Row
tCAH
Address
DSF
tFSR tRFH
tWSR tRWH
WE
tCSD
tMS
tMH
DQ0 - 15
TRG
Open
Mask Data
tRSD
tTLS
tTLH
tSRS
tSCC
tSC
tSCP
tSC
SC
Note 2
tSDZ
tSDS
tSDH
tSDS
tSDH
Data In
tSOH
SDQ0 - 15
QSF
Dout
Dout
tRQD
Data In
tSDD
tCQD
Note 3
Note 3
"H" or "L"
Note 1: SE = "L"
Note 2: There must be no rising transitions
Note 3: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
26/42
¡ Semiconductor
MSM54V16273
Masked Split Write Transfer
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tRCD
CASL/U
tAR
tRAD
tRAH
tRAL
tASC
SAM Start Sj
tASR
Row
tCAH
Address
DSF
tFSR tRFH
tWSR tRWH
WE
tCTH
tATH
tMS
tMH
DQ0 - 15
TRG
Open
Mask Data
tRTH
tTLS
tTLH
tSTS
tSCC
tSCP
tSC
SC
STOP i
S i
tSDH
Data In
STOP
j - 1
STOP j
S j
tSDS
tSDS
Data In
tSDH
SDQ0 - 15
QSF
Data In
Data In
Data In
Data In
tSQD
Note 2
tSQD
Note 2
Note 2
"H" or "L"
Note 1: SE = "L"
Note 2: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
Note 3: Si is the SAM start address in before SWT
Note 4: STOP i and STOP j are programmable stop addresses
27/42
¡ Semiconductor
MSM54V16273
Serial Read Cycle
tSEP
SE
tSCC
tSC
SC
tSCA
tSCP
tSCA
tSOH
tSCA
tSOH
tSOH
tSEZ
tSEA
SDQ0 - 15
Data Out
Data
Data
Data Out
Data Out
Serial Write Cycle
tSEP
SE
tSWIS
tSCC
tSCP
tSWH
tSWIH
tSWS
tSC
SC
tSDS
Data In
tSDS
tSDH
tSZE
tSDH
SDQ0 - 15
Data In
Data In
Data In
"H" or "L"
28/42
¡ Semiconductor
MSM54V16273
PIN FUNCTIONS
Address Input: A0 - A8
The 18 address bits decode 16 bits of the 4,194,304 locations in the MSM54V16273 memory array.
The address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row
address bits are latched at the falling edge of RAS. The following 9 column address bits are
latched at the falling edge of CAS.
Row Address Strobe: RAS
RAS is a basic RAM control signal. The RAM port is in standby mode when the RAS level is
"high". As the standard DRAM’s RAS signal function, RAS is the control input that latches the
row address bits, and a random access cycle begins at the falling edge of RAS.
In addition to the conventional RAS signal function, the level of the input signals CAS, TRG, WE
and DSF at the falling edge of RAS, determines the MSM54V16273 operation mode.
Column Address Strobe: CASL and CASU
As the standard DRAM’s CAS signal function, CAS is the control input signal that latches the
columnaddressinput,andthestateofthespecialfunctioninputDSFtoselectinconjunctionwith
the RAS control, either read/write operations or the special block write feature on the RAM port
when the DSF is held "low" at the falling edge of RAS.
CAS also acts as a RAM port output enable signal.
Data Transfer/Output Enable: TRG
TRG is also a control input signal having multiple functions. As the standard DRAM’s OE signal
function, TRG is used as an output enable control when TRG is "high" at the falling edge of RAS.
In addition to the conventional OE signal function, a data transfer operation is started between
the RAM port and the SAM port when TRG is "low" at the falling edge of RAS.
Write Per Bit/Write Enable: WE
WE is control input signal having multiple functions. As the standard DRAM’s WE signal
function, this is used to write data into the memory on the RAM port when WE is "high" at the
falling edge of RAS.
In addition to the conventional WE signal function, the WE determines the write-per-bit
function, when WE is "low" at the falling edge of RAS during RAM port operations.
The WE also determines the direction of data transfer between the RAM and SAM. When theWE
is "high" at the falling edge of RAS, the data is transferred from RAM to SAM (read transfer).
When the WE is "low" at the falling edge of RAS, the data is transferred SAM to RAM (write
transfer).
29/42
¡ Semiconductor
MSM54V16273
Write Mask Data/Data Input and Output: DQ0 - DQ15
In conventional write-per bit mode, the DQ pins function as mask data at the falling edge of RAS.
DataiswrittenonlytohighDQpins.DataonlowDQpinsismaskedandinternaldataisretained.
After that, they function as input/output pins similar to a standard DRAM.
In persistent write-per-bit mode, DQ pins do not consider the falling edge ofRAS. The mask data
is determined in the mask register load cycle.
Serial Clock: SC
SC is a main serial cycle control input signal. All operations of the SAM port are synchronized
with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In
a serial read cycle, the output data becomes valid on the SDQ pins after the maximum specified
serial access time t
from the rising edge of SC.
SCA
In a serial write cycle, data on SDQ pins at the rising edge of SC are fetched into the SAM register.
Serial Enable: SE
The SE is a serial access enable control and serial read/write control signal. In a serial read cycle,
SE is used as an output control. In a serial write cycle, SE is used as a write enable control. When
SE is "high", serial access is disabled. However, the serial address pointer location is still
incremented when SC is clocked even when SE is "high".
Special Function Input: DSF
The DSF is latched at the falling edge of RAS and CAS. It allows for the selection of several RAM
portsandtransferoperatingmodes.InadditiontotheconventionalmultiportDRAM,thespecial
functions consisting of flash write, block write, load/read color register, and split read/write
transfer can be invoked.
Special Function Output: QSF
QSF is an output signal, which during split register mode indicates which half of the split SAM
is being accessed. QSF "low" indicates that the lower split SAM (0 - 255) is being accessed. QSF
"high" indicates that the upper SAM (256 - 511) is being accessed.
QSF is enabled by SE. When SE is "high", QSF is in high impedance.
Serial Input/Output: SDQ0 - SDQ15
Serial input/output mode is determined by the most recent read or write transfer cycle. When
a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo
write transfer cycle is performed, the SAM port is switched from output mode to input mode.
30/42
¡ Semiconductor
MSM54V16273
OPERATION MODES
Table-1 shows the function truth table for a listing of all available RAM ports, and transfer
operations of the MSM54V16273.
The RAM port and data transfer operations are determined by the state of CAS, TRG, WE and
DSF at the falling edge of RAS, and by the level of DSF at the falling edge of CAS.
Table-1. Function Truth Table
CASØ
RASØ
Address
W/IO
Register
Write Pers.
Code
CAS
Function
CBR Refresh
CAS TRG WE DSF DSF RASØ CASØ RASØ
Mask W.M. WM Color
/WEØ
CBRR
CBRS
CBRN
ROR
MWT
MSWT
RT
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
*
*
*
1
0
0
0
0
1
1
1
1
1
1
1
1
0
1
*
0
0
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
0
0
1
0
0
1
1
—
—
—
—
*
*
*
*
*
*
*
*
*
*
—
—
Reset Reset
—
—
(Register Reset)
CBR Refresh
STOP
*
—
—
—
—
—
—
(Stop Register Set)
*
*
—
—
CBR Refresh (No Reset)
RAS Only Refresh
Row
—
—
*
—
—
No/
Yes
No/
Yes
Load
Use
Row TAP WM1
Row TAP WM1
Yes
Yes
—
—
Masked Write Transfer
Load
Use
Masked Split
*
*
—
Write Transfer
*
Row TAP
Row TAP
*
*
*
—
—
—
—
—
Read Transfer
SRT
*
*
—
—
Split Read Transfer
No/
Yes
No/
Yes
No/
Yes
Load
Use
Read/Write
RWM
BWM
FWM
RW
0
Row Column WM1 DinꢀDout Yes
—
(New/Old Mask)
Masked Block Write
(New/Old)
Column
A3c - 8c
Column
Select
Load
Use
1
Row
Row
WM1
Yes
Yes
Use
Use
—
Load
Use
Masked Flash Write
(New/Old)
*
*
WM1
—
Read/Write
0
Row Column
*
*
*
*
DinꢀDout No No
—
—
(No Mask)
Column
Row
Column
Block Write
BW
1
No No
Select
Use
—
A3c - 8c
(No Mask)
Mask
Load Mask Register
(Old Mask Set)
LMR
LCR
0
Row
Row
*
*
—
—
Set Load
Data
Color
Data
1
—
—
Load Load Color Register
Notes: 1. With CBRS and SAM operations use stop register.
2. After LMR, RWM, BWM, FWM and MSWT, use the old mask which can be reset by
CBRR.
31/42
¡ Semiconductor
MSM54V16273
If the DSF is "high" at the falling edge of RAS, special functions such as split transfer, flash write,
load mask register, load color register, CBRS and CBRN can be invoked.
If the DSF is "low" at the falling edge of RAS and "high" at the falling edge of CAS, the block write
feature can be invoked.
RAM PORT OPERATION
Extended RAM Read Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L"
CAS falling edge --- DSF = "L"
The MSM54V16273 offers an accelerated page mode cycle (EXTENDED PAGE MODE) by
eliminating output disable from CAS "high", and it allows CAS precharge time (t ) to occur
CP
withouttheoutputdatabecominginvalid.Thisnewdataoutoperates(Extendeddataout)asany
RAM read or Page Mode Read, except data will be held valid after CAS goes "high", as long as
RAS is "low".
Byte read occurs if either CASL or CASU falls during the cycle.
RAM Write Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L"
CAS falling edge --- DSF = "L"
1) Write cycle with no mask: RAS falling edge -- WE = "H"
If WE is set "low" at the falling edge of CAS after RAS goes "low", a write cycle is excuted. If WE
is set "low" before the CAS falling edge, this cycle becomes an early write cycle, and all DQ pins
attain high impedance.
If WE is "low" when CAS goes "low", the write affects only those corresponding 8 bits with the
latched data.
If WE is set "low" after the CAS falling edge, this cycle becomes a late write cycle, and all 16 data
are latched on the falling edge of WE.
Byte write occurs if either CASL or CASU falls during the cycle. DQ pins don't achieve high
impedance in this cycle, so data should be entered with TRG in "high".
2) Write cycle with mask: RAS falling edge -- WE = "L"
If WE is set "low" at the falling edge of RAS, two modes of mask write can be invoked.
#1 In new mask mode mask data is loaded and used. The mask data on DQ0 - DQ15 is latched
into the write mask register at the falling edge of RAS. When the mask data is low, writing is
inhibited into the RAM and the mask data is high, data is written into the RAM. This mask data
isineffectduringtheRAS cycle. Inpagemodecyclethemaskdataisretainedduringpageaccess.
#2 If a load mask register cycle (LMR) has been performed, the mask data is not loaded from DQ
pins, and the mask data stored in the mask register is persistently used.
This operation is known as persistent write mask, set by LMR and reset by CBRR.
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¡ Semiconductor
MSM54V16273
Load/Read Color Register: RAS falling edge --- CAS = TRG = WE = DSF = "H"
CAS falling edge --- DSF = "H"
TheMSM54V16273isprovidedwithanon-chip16-bitcolorregisterforuseduringtheflashwrite
or block write operation. Each bit of the color register corresponds to one of the DRAM I/O
blocks.
The data presented on the DQi lines is subsequently latched into the color register at the falling
edge of either CAS or WE whichever occurs later.
The read color register cycle is activated by holding WE "high" at the falling edge of CAS, and
throughout the remainder of the cycle. The data in the color register becomes valid on the DQi
lines after the specified access times from RAS and TRG are satisfied.
During the load/read color register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.
Load/Read Mask Register: RAS falling edge --- CAS = TRG = WE = DSF = "H"
CAS falling edge --- DSF = "L"
The MSM54V16273 is provided with an on-chip 16-bit mask register for use during the mask
write cycle, flash write cycle, block write cycle, masked write transfer, and masked split write
transfer. Each bit of the mask register corresponds to one of the DRAM I/O blocks.
The data presented on the DQi lines is subsequently latched into the mask register at the falling
edge of either CAS or WE whichever occurs later.
The read mask register cycle is activated by holding WE "high" at the falling edge of CAS, and
throughout the remainder of the cycle. The data in the mask register becomes valid on the DQi
lines after the specified access times from RAS and TRG are satisfied.
During the load/read mask register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.
Flash Write: RAS falling edge --- CAS = TRG = DSF = "H", WE = "L"
Flash write allows for the data in the color register to be written into all the memory locations of
a selected row.
Each bit of the color register corresponds to one of the DRAM I/O blocks. The flash write
operation can be selectively controlled on an I/O basis in the same manner as the write per bit
operation. The mask data is the same as that of a RAM write cycle.
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¡ Semiconductor
MSM54V16273
Block Write: RAS falling edge --- CAS = TRG = "H", DSF = "L"
CAS falling edge --- DSF = "H"
Block write allows for the data in the color register to be written into 8 consecutive column
address locations, starting from a selected column address in a selected row.
The block write operation can be selectively controlled on an I/O basis, and a column mask
capability is also available. This function is implemented as lower byte and upper byte. During
a block write cycle, the 3 least significant column address locations (A0C, A1C and A2C) are
internally controlled, and only the 6 most significant column addresses (A3C - A8C) are latched
at the falling edge of CAS.
1) No mask block write: WE "high" at the falling edge of RAS
The data on 16 DQ pins is cleared by the data of the color register.
2) Masked block write: WE "low" at the falling edge of RAS
The mask data is the same as that of a RAM write cycle. (new mask and persistent mask)
Bit 0
Bit 15
01110011
01101011
00111100
Color Register
I/O Mask
11001110
11111010
10010011
Column Mask
Lower Byte Upper Byte
8 Column ¥ 8 DQ (Lower Byte)
8 Column ¥ 8 DQ (Upper Byte)
Column 7
Column 6
Column 5
Column 4
Column 3
Column 2
Column 1
Column 0
1
1
*
*
1
*
*
1
1
1
*
*
1
*
*
1
0
0
*
*
0
*
*
0
0
0
*
*
0
*
*
0
1
1
*
*
1
*
*
1
*
*
*
*
*
*
*
*
1
1
*
*
1
*
*
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
1
*
*
*
*
1
1
1
1
*
*
*
*
*
*
*
*
*
*
*
*
0
0
0
0
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
1
*
*
*
*
1
1
1
1
*
*
Note : Location "*" can not be loaded.
Example of Block Write
34/42
¡ Semiconductor
MSM54V16273
SAM PORT OPERATION
Single Register Mode
High speed serial read or write operations can be performed through the SAM port independent
of the RAM port operation, except during read/write transfer cycles.
The preceding transfer operation determines the direction of data flow through the SAM port.
If the preceding transfer is a read transfer, the SAM port is in the output mode. If the preceding
transfer is write transfer, the SAM port is in the input mode.
SerialdatacanbereadoutoftheSAMafterareadtransferhasbeenperformed.Thedataisshifted
out of the SAM starting at any of the 512 bits locations.
The TAP location corresponds to the column address selected at the falling edge of CAS during
the read or write transfer cycle. The SAM registers are configured as a circular data register. The
data is shifted out sequentially. It starts from the selected TAP location at the most significant bit
(511), then wraps around to the least significant bit (0).
Split Register Mode
In split register mode data can be shifted into or out of one half of the SAM, while a split read or
split write transfer is being performed on the other half of the SAM.
Conventional (non split) read, or write transfer cycle must precede any split read or split write
transfers. The split read and write transfers will not change the SAM port mode set by the
preceding conventional transfer operation. In the split register mode, serial data can be shifted
in or out of one of the split SAM registers, starting from any at the 256 TAP locations, excluding
the last address of each split SAM the data is shifted in or out sequentially starting from the
selected TAP location at the most significant bit (255 or 511) of the first split SAM, and then the
SAM pointer moves to the TAP location selected for the second split SAM to shift data in or out
sequentially, starts from this TAP location at the most significant bit (511 or 255), and finally
wraps around to the least significant bit.
TAP
TAP
0
1
2
255
256 257
511
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¡ Semiconductor
MSM54V16273
DATA TRANSFER OPERATIONS
The MSM54V16273 features two types of bidirectional data transfer capability between RAM
and SAM.
1) Conventional (non split) transfer: 512 words by 16 bits of data can be loaded from RAM to
SAM (Read transfer), or from SAM to RAM (Write transfer).
2) Split transfer: 256 words by 16 bits of data can be loaded from the lower/upper half of the
RAM to the lower/upper half of the SAM (Split read transfer), or from the lower/upper half
of SAM to the lower/upper half of RAM (Split write transfer).
The conventional transfer and split transfer modes are controlled by the DSF input signal.
Data transfer is invoked by holding the TRG signal "low" at the falling edge of RAS.
The MSM54V16273 supports 4 types of transfer operations: Read transfer, Split read transfer,
Write transfer and Split write transfer as shown in the truth table. The type of transfer operation
is determined by the state of CAS, WE and DSF latched at the falling edge of RAS. During
conventional transfer operations, the SAM port is switched from input to output mode (Read
transfer), or output to input mode (Write transfer). It remains unchanged during split transfer
operation (Split read transfer or Split write transfer).
Both RAM and SAM are divided by the most significant row address (AX8), as shown in Figure
1. Therefore, no data transfer between AX8 = 0 side RAM and AX8 = 1 side RAM can be provided
through the SAM. Care must be taken if the split read transfer on AX8 = 1 side (or AX8 = 0 side)
is provided after the read transfer or the split read transfer, is provided on AX8 = 0 side (or AX8
= 1 side).
256 ¥ 256 ¥ 16
Memory
256 ¥ 256 ¥ 16
Memory
Array
Array
256 ¥ 256 ¥ 16
Memory
256 ¥ 256 ¥ 16
Memory
Array
Array
AX8 = 0
AX8 = 1
SAM I/O Buffer
SDQ0 - 15
Figure 1. RAM and SAM Configuration
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¡ Semiconductor
MSM54V16273
Read Transfer: RAS falling edge --- CAS = WE = "H", TRG = DSF = "L"
Read transfer consists of loading a selected row of data from the RAM into the SAM register. A
read transfer is invoked by holding CAS "high", TRG "low", WE "high", and DSF "low" at the
fallingedgeofRAS. TherowaddressselectedatthefallingedgeofRASdeterminestheRAMrow
to be transferred into the SAM. The transfer cycle is completed at the rising edge of TRG. When
the transfer is completed, the SAM port is set into the output mode. In a read/real time read
transfer cycle, the transfer of a new row of data is completed at the rising edge of TRG, and this
data becomes valid on the SDQ lines after the specified access time t
from the rising edge of
SCA
the subsequent SC cycles. The start address of the serial pointer of the SAM is determined by the
column address selected at the falling edge of CAS. In a read transfer cycle (which is preceded
by a write transfer cycle), SC clock must be held at a constant V or V after the SC high time
IL
IH
has been satisfied. A rising edge of the SC clock must not occur until after the specified delay t
TSD
from the rising edge of TRG.
In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous
row data appears on the SQD lines until the TRG signal goes "high", and the serial access time
t
for the following serial clock is satisfied. This feature allows for the first bit of the new row
SCA
of data to appear on the serial output as soon as the last bit of the previous row has been strobed
withoutanytimingloss. Tomakethiscontinuousdataflowpossible, therisingedgeofTRGmust
be synchronized with RAS, CAS, and the subsequent rising edge of SC (t
, t
and t /t
RTH CTH TSL TSD
must be satisfied).
Masked Write Transfer: RAS falling edge --- CAS = "H", TRG = DSF = "L"
WE = "L"
Write transfer cycle consists of loading the content of the SAM register into a selected row of the
RAM. This write transfer is the same as a mask write operation in RAM, so new and persistent
(old) mask modes can be supported. (Masked write transfer)
If the SAM data to be transferred must first be loaded through the SAM, a Masked write transfer
operation (all DQ pins "low" at falling edge of RAS) must precede the write transfer cycles. A
masked write transfer is invoked by holding CAS "high", TRG "low", WE "low", and DSF "low"
at the falling edge of RAS. The row address selected at the falling edge of RAS determines the
RAM row address into which the data will be transferred. The column address selected at the
falling edge of CAS determines the start address of the serial pointer of the SAM. After the write
transfer is completed, the SDQ lines are set in the input mode so that serial data synchronized
with the SC clock can be loaded.
When consecutive write transfer operations are performed, new data must not be written into
the serial register until the RAScycle of the preceding write transfer is completed. Consequently,
the SC clock must be held at a constant V or V during the RAS cycle. A rising edge of the SC
IL
IH
clockisonlyallowedafterthespecifieddelayt
a new row of data can be written in the serial register.
fromthefallingedgeoftheCAS, atwhichtime
CSD
Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to the
other address of RAM by write transfer cycle. However, the address to write data must be the
same as that of the read transfer cycle (row address AX8).
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¡ Semiconductor
MSM54V16273
Split Data Transfer and QSF
The MSM54V16273 features a bidirectional split data transfer capability between the RAM and
SAM. During split data transfer operation, the serial register is split into two halves which can
be controlled independently. Split read or split write transfer operation can be performed to or
from one half of the serial register, while serial data can be shifted into or out of the other half of
the serial register. The most significant column address location (A8C) is controlled internally to
determine which half of the serial register will be reloaded from the RAM. QSF is an output
which indicates which half of the serial register is in an active state. QSF changes state when the
last SC clock is applied to active split SAM.
Split Read Transfer: RAS falling edge --- CAS = WE = DSF = "H", TRG = "L"
The MSM54V16273 supports two types of split register operation.
#1 Normal split register operation
#2 Boundary split register operation using programmable SAM stops described later.
Normal split read transfer consists of loading 256 words by 16 bits of data from a selected row
of the split RAM into the corresponding non-active split SAM register. Serial data can be shifted
out from the other half of the split SAM register simultaneously. During split read transfer
operation, the RAM port input clocks do not have to be synchronized with the serial clock SC,
thus eliminating timing restrictions as in the case of real time read transfers. A split read transfer
can be performed after a delay of t
from the change of state of the QSF output is satisfied.
STS
Conventional (non-split) read transfer operation must precede split read transfer cycles.
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¡ Semiconductor
MSM54V16273
Masked Split Write Transfer: RAS falling edge --- CAS = DSF = "H", TRG = "L"
WE = "L"
Split write transfer consists of loading 256 words by 16 bits of data from the non-active split SAM
register into a selected row of the corresponding split RAM. Serial data can be shifted into the
other half of the split SAM register simultaneously. During split write transfer operation, the
RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing
for real time transfer. This operation is the same as a mask write operation in RAM, so new and
persistent modes can be supported.
A split write transfer can be performed after a delay of t
from the change of state of the QSF
STS
output is satisfied.
A masked write transfer operation must precede split write transfer. The purpose is to switch the
SAM port from output mode to input mode, and to set the initial TAP location prior to split write
transfer operations.
Programmable SAM Stops in Split Transfer Cycle
TheMSM54V16273hasaboundarysplitregisteroperationusingprogrammablestops. IfaCBRS
cycle has been performed, the split transfer cycle performs the boundary operation.
Figure 2 shows an example of a boundary split register (4 stop points). The stop points define a
SAM location at which the access will change from one half of the SAM to the other half (at the
TAP address).
Lower SAM
TAP3
Upper SAM
TAP2
TAP1
0
255
256
511
S.T. (TAP2)
S.T. (TAP3)
Figure 2. Example of Boundary Split Register
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¡ Semiconductor
MSM54V16273
SAM Stop Set Cycle (CBRS): RAS falling edge --- CAS = "L", WE = "L", DSF = "H"
SAM stop location data (boundaries) are latched from address inputs at the falling edge of RAS.
To determine the boundary A4 - A7 are used, and A0 - A3, and A8 are ignored.
Once the CBRS is executed, the programmable SAM stop operation continues until CBRR.
SAM Stop Boundary Table
Address
Number of Stop Points
Size of Partition
A4
1
A5
1
A6
1
A7
1
1
2
256
128
64
1
1
1
0
4
1
1
0
X
8
1
0
X
X
32
16
0
X
X
X
16
Register Reset Cycle (CBRR): RAS falling edge --- CAS = "L", WE = "H", DSF = "L"
A CBRR can reset the programmable SAM stop operation, and persistent mask write operation.
The CBRR will take effect immediately; it doesn’t require a split transfer cycle.
POWER UP
Power must be applied to the RAS and TRG input signals to pull them "high" before, or at the
same time as, the V supply is turned on. After power-up, a pause of 200 ms minimum is
CC
required with RAS and TRG held "high". After the pause, a minimum of 8 RAS and 8 SC dummy
cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer
operations can begin. During the initialization period, the TRG signal must be held "high". If the
internal refresh counter is used, a minimum 8 CAS before RAS cycles are required instead of 8
RAS cycles.
(NOTE) INITIAL STATE AFTER POWER UP
The initial state can not be guaranteed for various power up conditions and input signal levels.
Therefore, it is recommended that the initial state be set (ex. Perform a CBRR cycle to select Non
Persistent Write-per-bit mode) after the initialization of the device is performed and before valid
operations begin.
40/42
¡ Semiconductor
PACKAGE DIMENSIONS
SSOP64-P-525-0.80-K
MSM54V16273
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.34 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
41/42
¡ Semiconductor
MSM54V16273
(Unit : mm)
TSOPII70/64-P-400-0.65-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.59 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
42/42
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