MSM56V16800F-8ATS-K [OKI]
Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44;
| 型号： | MSM56V16800F-8ATS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总31页 (文件大小：3088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDD56V16800F-01
This version: November. 2000
Previous version :
1
Semiconductor
MSM56V16800F
2-Bank × 1,048,576-Word × 8-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MSM56V16800F is a 2-Bank × 1,048,576-word × 8-bit Synchronous dynamic RAM fabricated in
Oki’s silicon-gate CMOS technology. The device operates at 3.3V. The inputs and outputs are LVTTL
compatible.
FEATURES
∙ Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
∙ 2-Bank × 1,048,576-word × 8-bit configuration
∙ Single 3.3V power supply, ±0.3V tolerance
∙ Input : LVTTL compatible
∙ Output : LVTTL compatible
∙ Refresh : 4096 cycles/64ms
∙ Programmable data transfer mode
- CAS Latency (1,2,3)
- Burst Length (1,2,4,8,Full Page)
- Data scramble (sequential, interleave)
∙ CBR auto-refresh, Self-refresh capability
∙ Packages:
44-pin 400mil plastic TSOP (TypeII) (TSOPII44-P-400-0.80-1K)(Product : MSM56V16800F-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Max.
Family
Frequency
t
t
AC3
AC2
MSM56V16800F-8A
MSM56V16800F-10
125MHz
100MHz
6ns
9ns
6ns
9ns
1/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
PIN CONFIGURATION (TOP VIEW)
VCC
1
44 VSS
DQ1 2
43 DQ8
VSSQ 3
42 VSSQ
DQ2 4
41 DQ7
V
CCQ 5
DQ3 6
VSSQ 7
DQ4 8
VCCQ 9
NC 10
40 VCCQ
39 DQ6
38 VSSQ
37 DQ5
36 VCC
35 NC
34 NC
Q
NC 11
12
13
14
15
33 DQM
32 CLK
31 CKE
30 NC
29 A9
28 A8
27 A7
26 A6
25 A5
A11 16
A10 17
A0 18
A1 19
A2 20
A3 21
VCC 22
24 A4
23 VSS
44-Pin Plastic TSOP
(K Type)
Pin Name
CLK
Function
System Clock
Pin Name
DQM
DQi
Function
Data Input/ Output Musk
Data Input/ Output
CS
Chip Select
CKE
Clock Enable
VCC
Power Supply (3.3V)
Ground (0V)
A0–A10
A11
Address
VSS
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
VCC
Q
Q
Data Output Power Supply (3.3V)
Data Output Ground (0V)
No Connection
RAS
VSS
CAS
NC
WE
Note : The same power supply voltage must be provided to every V pin and V Q pin.
CC
CC
The same GND voltage level must be provided to every V pin and V Q pin.
SS
SS
2/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
PIN DESCRIPTION
CLK
Fetches all inputs at the “H” edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM.
CS
Masks system clock to deactivate the subsequent CLK operation.
CKE
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Address
A11
Row address
Column Address
: RA0 – RA10
: CA0 – CA8
Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time. A11=”L” : Bank A, A11=”H” : Bank B
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
Masks the read data of two clocks later when DQM is set “H” at the “H” edge of the clock signal.
Masks the write data of the same clock when DQM is set “H” at the “H” edge of the clock signal.
DQM
DQi
Data inputs/outputs are multiplexed on the same pin.
3/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
BLOCK DIAGRAM
CKE
CLK
Progra-
ming
Register
Latency
& Burst
Controller
I/O
Controller
CS
RAS
CAS
WE
Timing
Register
DQM
Bank
Controller
A11
Internal
Col.
Address
Counter
Input
Data
Input
Buffers
A0 - A11
Register
8
8
Column
Address
Buffers
Column
Decoders
9
9
Sense
Amplifiers
DQ1
- DQ8
8
8
8
Read
Data
Output
Buffers
Internal
Row
Register
Address
Counter
Row
Decoders
Word
Drivers
8Mb
Memory
Cells
Row
Address
Buffers
Row
Decoders
Word
Drivers
8Mb
Memory
Cells
12
12
Sense
Amplifiers
Column
Decoders
4/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to VSS
)
Parameter
Voltage on Any Pin Relative to VSS
VCC Supply Voltage
Symbol
Value
Unit
V
VIN, VOUT
–0.5 to VCC+ 0.5
–0.5 to 4.6
–55 to 150
600
VCC , VCC
Tstg
Q
V
Storage Temperature
°C
mW
mA
°C
Power Dissipation
PD*
Short Circuit Output Current
Operating Temperature
IOS
50
Topr
0 to 70
*: Ta = 25°C
RECOMMENDED OPERATIING CONDITIONS
(Voltages referenced to VSS = 0V)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VCC, VCC
VIH
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
Q
2.0
VCC + 0.2
0.8
V
VIL
− 0.3
V
PIN CAPACITANCE
(VBIAS = 1.4V, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
CCLK
Min.
2.5
Max.
4
Unit
pF
Input Capacitance (CLK)
Input Capacitance
CIN
2.5
4
5
pF
pF
(RAS, CAS, WE, CS, CKE, DQM, A0 - A11)
Input/Output Capacitance (DQ1 - DQ8)
COUT
6.5
5/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
DC CHARACTERISTICS
MSM56V16800
F-8A F-10
Unit
Note
Condition
CKE
Parameter
Symbol
Bank
Others
Min.
2.4
Max.
Min. Max.
2.4
Output High
Voltage
I
=
OH
V
OH
V
V
−2.0mA
Output Low
Voltage
I
=
OL
V
OL
I
LI
0.4
10
10
0.4
2.0mA
Input Leakage
Current
− 10
− 10
− 10
− 10
10
10
µA
µA
Output Leakage
Current
I
LO
t
t
= Min.
= Min.
CC
RC
One Bank
Active
I
CKE≥VIH
CKE≥VIH
CKE≥VIH
80
115
35
70
95
30
mA
mA
mA
1,2
1,2
3
CC1
No Burst
Average Power
Supply Current
t
t
t
= Min.
= Min.
CC
Both
Banks
Active
(Operating)
RC
I
CC1D
= Min.
RRD
No Burst
Power Supply
Current
Both
Banks
Precharge
I
t
t
= Min.
= Min.
CC2
CC
CC
(Standby)
Average Power
Supply Current
Both
Banks
Active
I
CKE≤VIL
3
3
mA
2
CC3S
(Clock
Suspension)
Average Power
Supply Current
One Bank
Active
I
I
I
I
I
CKE≥VIH
CKE≥VIH
CKE≥VIH
CKE≤ VIL
CKE≤VIL
t
t
= Min.
= Min.
40
125
80
2
35
100
70
2
mA
mA
mA
mA
mA
3
1,2
2
CC3
CC4
CC5
CC6
CC7
CC
CC
(Active Standby)
Both
Banks
Active
Power Supply
Current (Burst)
Power Supply
Current
One Bank
Active
t
t
= Min.
= Min.
CC
RC
(Auto-Refresh)
Average Power
Supply Current
Both
Banks
Precharge
t
t
= Min.
= Min.
CC
CC
(Self-Refresh)
Average Power
Supply Current
Both
Banks
2
2
Precharge
(Power Down)
Notes: 1. Measured with outputs open.
2. The address and data can be changed once or left unchanged during one cycle.
3. The address and data can be changed once or left unchanged during two cycle.
6/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Mode Set Address Keys
CAS Latency
Burst Type
BT
Burst Length
A6
0
A5
0
A4
0
CL
Reserved
1
A3
0
A2
0
A1
0
A0
0
BT = 0
BT = 1
Sequential
Interleave
1
2
4
8
1
2
4
8
0
0
1
1
0
0
1
0
1
0
2
0
1
0
0
1
1
3
0
1
1
1
0
0
Reserved
Reserved
Reserved
Reserved
1
0
0
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Notes: A7, A8, A9, A10 and A11 should stay “L” during mode set cycle.
MSM56V16800F support two methods of Power on Sequence.
POWER ON SEQUENCE 1
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the V voltage has reached the specified level, pause for 200µs or more with the input kept in
CC
NOP state.
3. Issue the precharge all bank command.
4. Apply a CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
POWER ON SEQUENCE 2
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the V voltage has reached the specified level, pause for 200µs or more with the input kept in
CC
NOP state.
3. Issue the precharge all bank command.
4. Enter the mode register setting command.
5. Apply a CBR auto-refresh eight or more times.
7/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
AC CHARACTERISTICS (1/2)
Note1,2
MSM56V16800
F-8A
MSM56V16800
F-10
Parameter
CL = 3
Symbol
Unit Note
Min.
8
Max.
Min.
10
Max.
t
t
t
t
t
t
ns
ns
ns
CC3
CC2
CC1
AC3
AC2
AC1
Clock Cycle Time
CL = 2
CL = 1
CL = 3
CL = 2
CL = 1
10
20
15
30
6
6
9
9
ns
ns
ns
ns
ns
ns
ns
3,4
3,4
3,4
4
Access Time from
Clock
16
27
Clock High Pulse Time
Clock Low Pulse Time
Input Setup Time
t
3
3
2
1
3
3
3
1
CH
t
4
CL
t
SI
HI
Input Hold Time
t
Output Low Impedance Time
from Clock
t
3
3
ns
ns
OLZ
OHZ
Output High Impedance Time
from Clock
t
8
8
Output Hold from Clock
Random Read or Write Cycle Time
RAS Precharge Time
t
3
3
ns
ns
ns
ns
ns
ns
3
OH
t
70
20
48
20
8
90
30
60
30
15
RC
t
RP
RAS Pulse Width
t
t
100,000
100,000
RAS
RAS to CAS Delay Time
Write Recovery Time
RCD
t
WR
RAS to CAS Bank Active Delay
t
20
20
ns
ms
ns
RRD
Time
Refresh Time
t
64
3
64
3
REF
RDE
Power-down Exit setup Time
t
t
+1CLK
t
+1CLK
SI
SI
Input Level Transition Time
CAS to CAS Delay Time (Min.)
Clock Disable Time from CKE
t
ns
T
t
1
1
1
1
Cycle
Cycle
CCD
t
CKE
DOZ
DOD
Data Output High Impedance Time
from DQM
t
2
0
2
0
Cycle
Cycle
Dada Input Mask Time from DQM
t
8/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
AC CHARACTERISTICS (2/2)
Note1,2
MSM56V16800
F-8A
MSM56V16800
F-10
Parameter
Symbol
Unit Note
Min.
Max.
Min.
Max.
Data Input Mask Time from Write
Command
t
0
0
Cycle
Cycle
DWD
Data Output High Impedance Time
from Precharge Command
t
CL
CL
ROH
MRD
OWD
Active Command Input Time from
Mode Register Set Command Input
(Min.)
t
2
2
2
2
Cycle
Cycle
Write Command Input Time from
Outpput
t
Notes: 1. AC measurements assume that tT = 1ns.
2. The reference level for timing of input signals is 1.4V.
3. Output load.
Z=50Ω
Output
50pF (External Load)
4. The access time is defined at 1.4V.
5. If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL.
9/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
TIMING CHART
Read & Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
tRC
CKE
CS
tRP
RAS
CAS
ADDR
A11
A10
DQ
tRCD
Ra
Ca0
Rb
Rb
Cb0
Ra
tOH
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
tWR
tAC
tOHZ
WE
DQM
Row Active
Read Command
Row Active
Precharge Command
Write Command
Precharge Command
10/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=2, Burst Length=4
tCH
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
tCC
tCL
High
CS
tHI
tSI
RAS
CAS
ADDR
A11
A10
DQ
ICCD
tSI
tHI
tSI
tSI
tSI
Ra
Ca
Cb
Cc
tHI
tHI
BS
BS
BS
Db
BS
BS
Ra
tHI
tOHZ
tAC
Qa
Qc
tOLZ
tSI
tOH
tHI
lOWD
WE
tSI
DQM
Row Active
Read Command
Write Command
Precharge Command
Read Command
11/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
*Note: 1. When CS is set “High” at a clock transition from “Low” to “High”, all inputs except CKE and DQM
are invalid.
2. When issuing an active, read or write command, the bank is selected by A11.
A11
0
Active, read or write
Bank A
1
Bank B
3. The auto precharge function is enabled or disabled by the A10 input when the read or write command
is issued.
A10
0
A11
0
Operation
After the end of burst, bank A holds the idle status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the idle status.
After the end of burst, bank B is precharged automatically.
1
0
0
1
1
1
4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs.
A10
0
A11
0
Operation
Bank A is precharged.
0
1
Bank B is precharged.
1
X
Both banks A and B are precharged.
5. The input data and the write command are latched by the same clock (Write latency=0).
6. The output is forced to high impedance by (1CLK+ tOHZ ) after DQM entry.
12/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Page Read & Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4
CLK
High
CKE
CS
Bank A Active
RAS
CAS
ADDR
A11
A10
DQ
ICCD
Ca0
Cb0
Cc0
Cd0
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0
lOWD
tWR
Note 2
WE
Note 1
DQM
Read Command
Read Command
Write Command
Precharge Command
Write Command
*Note: 1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write
command to avoid bus contention.
2. To assert row precharge before a burst write ends, wait tWR after the last write data input.
Input data during the precharge input cycle will be masked internally.
13/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Read & Write Cycle with Auto Precharge @ Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
High
CS
RAS
CAS
ADDR
A11
A10
tRRD
Ra
Ra
Rb Ca
Cb
Rb
WE
CAS Latency=1
DQ
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
A-Bank Precharge Start
DQM
CAS Latency=2
DQ
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
A-Bank Precharge Start
DQM
CAS Latency=3
DQ
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
tWR
A-Bank Precharge Start
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
B Bank Write with
Auto Precharge
B Bank Precharge
Start Point
A Bank Read with
Auto Precharge
14/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Bank Interleave Random Row Read Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
High
CS
tRC
RAS
CAS
ADDR
A11
A10
DQ
tRRD
RAa
CAa
RBb
CBb
RAc
CAc
RAa
RBb
RAc
QAa0 QAa1 QAa2 QAa3
QBb1 QBb2 QBb3 QBb4
QAc0 QAc1 QAc2 QAc3
WE
DQM
Row Active
(A-Bank)
Read Command
(B-Bank)
Read Command
(A-Bank)
Row Active
(B-Bank)
Read Command
(A-Bank)
Row Active
(A-Bank)
Precharge Command
(A-Bank)
Precharge Command
(B-Bank)
15/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Bank Interleave Random Row Write Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
High
CS
RAS
CAS
ADDR
A11
A10
DQ
RAa
CAa
RBb
CBb
RAc
CAc
RAa
RBb
RAc
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3
DAc0 DAc1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Precharge Command
(A-Bank)
Write Command
(A-Bank)
Precharge Command
(A-Bank)
Write Command
(A-Bank)
Precharge Command
(B-Bank)
Write Command
(B-Bank)
Row Active
(A-Bank)
16/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Bank Interleave Page Read Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
High
Note 1
CS
RAS
CAS
ADDR
A11
RAa
CAa
RBb
CBb
CAc
CBd
CAe
A10
RAa
RBb
DQ
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
IROH
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Read Command
(B-Bank)
Precharge Command
(A-Bank)
Read Command
(A-Bank)
Read Command
(B-Bank)
Read Command
(A-Bank)
Read Command
(A-Bank)
*Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle.
17/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Bank Interleave Page Write Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
High
CKE
CS
RAS
CAS
ADDR
A11
A10
DQ
RAa
CAa
RBb
CBb
CAc
CBd
RAa
RBb
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write Command
(B-Bank)
Precharge Command
(Both Bank)
Write Command
(B-Bank)
Write Command
(A-Bank)
Write Command
(A-Bank)
18/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Bank Interleave Random Row Read/Write Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
High
CS
RAS
CAS
ADDR
A11
A10
DQ
RAa
CAa
RBb
CBb
RAc
CAc
RAa
RBb
RAc
QAa0 QAa1 QAa2 QAa3
QBb0 QBb1 QBb2 QBb3
QAc0 QAc1 QAc2 QAc3
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write Command
(B-Bank)
Read Command
(A-Bank)
Read Command
(A-Bank)
Precharge Command
(A-Bank)
Row Active
(A-Bank)
19/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Bank Interleave Page Read/Write Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
High
CS
RAS
CAS
ADDR
A11
A10
DQ
CAa0
CBb0
CAc0
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2 QAc3
WE
DQM
Read Command
(A-Bank)
Write Command
(B-Bank)
Read Command
(A-Bank)
20/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
Note 1
Note 1
CS
RAS
CAS
ADDR
A11
A10
DQ
Ra
Ca
Cb
Cc
Ra
Qa0 Qa1
Qa2
Qb0 Qb1
Dc0
Dc2
tOHZ
tOHZ
Note 3
Note 2
WE
DQM
CLOCK
Suspension
Read Command
Write
DQM
Write DQM
Read DQM
Row Active
Read Command
Write
CLOCK Suspension
Read DQM
Command
*Note: 1. When Clock Suspension is asserted, the next clock cycle is ignored.
2. When DQM are asserted, the read data after two clock cycles is masked.
3. When DQM are asserted, the write data in the same clock cycle is masked.
21/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Read to Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
CS
Note 1
RAS
CAS
ADDR
A11
A10
DQ
tRCD
Ra
Ra
Ca0
Cb0
Da0
Db0 Db1 Db2 Db3
tWR
WE
DQM
Precharge Command
Row Active
Read Command
Write Command
*Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE.
The minimum command interval is [burst length + 1] cycles.
DQM must be high at least 3 clocks prior to the write command.
22/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Read Interruption by Precharge Command @Burst Length=8
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
High
CS
RAS
CAS
ADDR
A11
A10
Ra
Ra
Ca
WE
Note 1
CAS Latency=1
DQ
Qa0
Qa4 Qa5
Qa1 Qa2 Qa3
lROH
DQM
CAS Latency=2
Note 1
DQ
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
lROH
DQM
Note 1
CAS Latency=3
DQ
Qa3 Qa4 Qa5
Qa0 Qa1 Qa2
lROH
DQM
Row Active
Read Command
Precharge Command
*Note: 1. if row precharge is asserted before a burst read ends, then the read data will not output after l
ROH
equals CAS latency.
23/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Burst Stop Command @Burst Length=8
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
High
CS
RAS
CAS
ADDR
A11
A10
Ca
Cb
WE
CAS Latency=1
DQ
Qa0 Qa1 Qa2 Qa3 Qa4
Qb0 Qb1 Qb2 Qb3 Qb4
Qb0 Qb1 Qb2 Qb3 Qb4
Qb0 Qb1 Qb2 Qb3 Qb4
DQM
CAS Latency=2
DQ
Qa0 Qa1 Qa2 Qa3 Qa4
DQM
CAS Latency=3
DQ
Qa0 Qa1 Qa2 Qa3 Qa4
DQM
Read Command
Burst Stop Command
Write Command
Burst Stop Command
24/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Power Down Mode @CAS Latency=2, Burst Length=4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
tSI
CLK
CKE
Note 2
tPDE
tSI
tSI
Note 1
t
REF (min.)
CS
RAS
CAS
ADDR
A11
A10
Ra
Ca
Ra
DQ
Qa0 Qa1 Qa2
WE
DQM
Power-down
Entry
Read Command
Row
Active
Power-down
Exit
Clock
Suspension
Entry
Clock
Suspension Exit
Precharge Command
*Note: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16800F enters
power-down mode and maintains the mode while CKE is low.
2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (tSI + 1CLK).
25/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Self Refresh Cycle
0
1
2
CLK
CKE
tRC
tSI
CS
RAS
CAS
ADDR
A11
A10
Ra
BS
Ra
Hi-Z
DQ
WE
DQM
Self Refresh Entry
Self Refresh Exit
Row Active
26/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10 11
CLK
CKE
High
High
CS
lMRD
tRC
RAS
CAS
ADDR
DQ
Key
Ra
Hi - Z
Hi - Z
WE
DQM
MRS
New Command
Auto Refresh
Auto Refresh
27/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
FUNCTION TRUTH TABLE (Table 1) (1/2)
Current
BA
ADDR
Action
CS RAS CAS WE
State1
Idle
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
NOP
NOP
2
2
BA
BA
BA
BA
X
X
ILLEGAL
ILLEGAL
X
H
L
CA
RA
A10
X
H
H
L
Row Active
4
L
NOP
5
L
H
L
Auto-Refresh or Self-Refresh
L
L
L
OP Code Mode Register Write
X
H
H
H
L
X
H
L
X
X
H
L
X
X
X
NOP
NOP
Row Active
X
BA
BA
BA
BA
X
CA, A10 Read
CA, A10 Write
L
2
H
H
L
H
L
RA
ILLEGAL
L
A10
Precharge
ILLEGAL
L
X
X
H
L
X
X
H
H
H
H
L
X
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Term Burst --> Row Active
Read
X
X
X
X
3
H
L
BA
BA
BA
BA
X
CA, A10
Term Burst, start new Burst Read
3
L
CA, A10
Term Burst, start new Burst Write
2
H
H
L
H
L
RA
ILLEGAL
L
A10
Term Burst, execute Row Precharge
ILLEGAL
L
X
X
H
L
X
X
H
H
H
H
L
X
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Term Burst --> Row Active
Write
X
X
X
X
3
H
L
BA
BA
BA
BA
X
CA, A10
Term Burst, start new Burst Read
3
L
CA, A10
Term Burst, start new Burst Write
2
H
H
L
H
L
RA
ILLEGAL
3
L
A10
Term Burst, execute Row Precharge
L
X
X
H
L
X
ILLEGAL
X
H
H
H
H
L
X
H
H
L
X
X
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
Read with
Auto
Precharge
X
X
2
BA
BA
X
X
ILLEGAL
2
H
L
CA, A10
ILLEGAL
L
X
ILLEGAL
2
H
L
X
X
X
H
L
BA
X
RA, A10
ILLEGAL
L
X
ILLEGAL
X
H
H
H
X
H
H
L
X
X
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
Write with
Auto
Precharge
X
X
X
2
BA
BA
ILLEGAL
2
H
CA, A10
ILLEGAL
28/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
FUNCTION TRUTH TABLE (Table 2) (2/2)
Current
BA
ADDR
Action
CS RAS CAS WE
State1
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
H
L
L
X
X
X
H
L
X
BA
X
X
RA, A10
X
ILLEGAL
Write with
Auto
Precharge
2
ILLEGAL
ILLEGAL
L
NOP --> Idle after t
NOP --> Idle after t
X
H
H
H
L
X
H
H
L
X
X
Precharge
RP
RP
X
X
2
BA
BA
BA
BA
X
X
ILLEGAL
2
X
H
L
CA
RA
A10
X
ILLEGAL
2
H
H
L
ILLEGAL
4
L
NOP
L
X
X
H
L
ILLEGAL
NOP
X
H
H
H
L
X
H
H
L
X
X
Write
Recovery
X
X
NOP
2
BA
BA
BA
BA
X
X
ILLEGAL
2
X
H
L
CA
RA
A10
X
ILLEGAL
2
H
H
L
ILLEGAL
2
L
ILLEGAL
L
X
X
H
L
ILLEGAL
NOP --> Row Active after t
NOP --> Row Active after t
X
H
H
H
L
X
H
H
L
X
X
Row Active
RCD
RCD
X
X
2
BA
BA
BA
BA
X
X
ILLEGAL
2
X
H
L
CA
RA
A10
X
ILLEGAL
2
H
H
L
ILLEGAL
2
L
ILLEGAL
L
X
X
X
X
X
X
X
H
L
ILLEGAL
NOP --> Idle after t
RC
NOP --> Idle after t
RC
X
H
H
L
X
H
L
X
X
Refresh
X
X
X
X
ILLEGAL
ILLEGAL
ILLEGAL
NOP
H
L
X
X
L
X
X
X
H
H
H
L
X
H
H
L
X
X
Mode
Register
Access
X
X
NOP
X
X
ILLEGAL
ILLEGAL
ILLEGAL
X
X
X
X
X
X
X
ABBREVIATIONS
RA = Row Address BA = Bank Address NOP = No OPeration command
CA = Column Address AP = Auto Precharge
Notes :1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank
selection.
3. Satisfy the timing of lCCD and tWR to prevent bus contention.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
29/31
FEDD56V16800F-01
1
Semiconductor
MSM56V16800F
FUNCTION TRUTH TABLE for CKE (Table 2)
Current State (n) CKEn-1 CKEn
ADDR Action
INVALID
Exit Self Refresh --> ABI
CS RAS CAS WE
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Self Refresh
L
Exit Self Refresh --> ABI
ILLEGAL
L
L
L
L
X
X
X
X
X
H
L
ILLEGAL
L
L
X
X
X
X
H
H
L
ILLEGAL
L
X
X
H
L
X
X
X
H
H
H
L
NOP (Maintain Self Refresh)
INVALID
H
L
X
H
H
H
H
H
L
Power Down
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
L
L
L
L
L
X
X
X
X
X
H
L
ILLEGAL
ILLEGAL 6
L
L
X
X
X
X
H
H
L
L
X
X
H
L
X
X
X
H
H
H
L
NOP (Continue power down mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
All Banks Idle 6
(ABI)
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
X
L
ILLEGAL
L
L
H
L
ILLEGAL
L
L
L
H
L
Enter Self Refresh
ILLEGAL
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
H
H
L
H
L
Refer to Operations in Table 1
Begin Clock Suspend Next Cycle
Enable Clock of Next Cycle
Continue Clock Suspension
Any State Other
than Listed
Above
H
L
L
*Notes :6. Power-down and self-refresh can be entered only when all the banks are in an idle state.
30/31
FEDD56V16800F-01
MSM56V16800F
1
Semiconductor
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that
the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special or
enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
31/31
相关型号：
MSM56V16800F-8TS-K
Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44
OKI
MSM5718B70-50GS-K
Rambus DRAM, 2MX9, CMOS, PDSO36, 11 X 25 MM, 0.65 MM PITCH, PLASTIC, SHP-32/36
OKI
MSM5718B70-53GS-K
Rambus DRAM, 2MX9, CMOS, PDSO36, 11 X 25 MM, 0.65 MM PITCH, PLASTIC, SHP-32/36
OKI
MSM5718B70-60GS-K
Rambus DRAM, 2MX9, CMOS, PDSO36, 11 X 25 MM, 0.65 MM PITCH, PLASTIC, SHP-32/36
OKI
MSM5718C50-53GS-K
Rambus DRAM, 2MX9, CMOS, PDSO36, 11 X 25 MM, 0.65 MM PITCH, PLASTIC, SHP-32/36
OKI
©2020 ICPDF网 联系我们和版权申明