MSM6242B [OKI]
DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR; 直通巴士连接的CMOS实时时钟/日历
| 型号： | MSM6242B |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR |
| 文件： | 总18页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
¡ Semiconductor
MSM6242B
DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR
DESCRIPTION
The MSM6242B is a silicon gate CMOS Real
Time Clock/Calendar for use in direct bus-
connection Microprocessor/Microcomputer
applications. An on-chip 32.768 KHz crystal
oscillator time base is divided to provide ad-
dressable 4-bit I/O data for SECONDS,
MINUTES, HOURS, DAY OF WEEK, DATE,
MONTHandYEAR. Dataaccessiscontrolled
by 4-bit address, chip selects (CSO, CS1),
WRITE, READ, and ALE. Control Registers
D, E and F provide for 30 SECOND error
adjustment, INTERRUPT REQUEST (IRQ
FLAG) and BUSY status bits, clock STOP,
HOLD, and RESET FLAG bits, 4 selectable
INTERRUPTS rates are available at the STD.P
(STANDARD PULSE) output utilizing Con-
trol Register inputs T0, T1 and the ITRPT/
STND (INTERRUPT/STANDARD). Mask-
ing of the interrupt output (STD.P) can be
accomplished via the MASK bit. The
MSM6242B can operate in a 12/24 hour for-
mat and Leap Year timing is automatic.
The MSM6242B normally operates from a 5V
±10% supply at –40 to 85°C. Battery backup
operation down to 2.0V allows continuation
of time keeping when main power is off. The
MSM6242B is offered in a 18-pin plastic DIP
and a 24-pin plastic Small Outline package.
FEATURES
DIRECT MICROPROCESSOR/MICROCONTROLLER BUS CONNECTION
TIME
MONTH
12
DATE
31
YEAR
80
DAY OF WEEK
7
23:59:59
•
•
•
4-bit data bus
4-bit address bus
READ, WRITE, ALE and CHIP SELECT
INPUTS
Status registers – IRQ and BUSY
Selectable interrupt outputs – 1/64
second, 1 second, 1 minute, 1 hour
Interrupt masking
•
•
•
•
•
•
12/24 hour format
Auto leap year
±30 second error correction
Single 5V supply
Battery backup down to VDD = 2.0V
Low power dissipation:
20µW max at VDD = 2V
150µW max at VDD = 5V
18 pin Plastic DIP (DIP18-P-300)
24 Pin-V Plastic SOP (SOP24-P-430-VK)
•
•
•
•
32.768 KHz crystal controlled operation
•
•
23
MSM6242B
¡ Semiconductor
FUNCTIONAL BLOCK DIAGRAM
XT
1 Hz
30 ADJ HOLD
32.768KHz
OSC
COUNTER
XT
BUSY
bit
RESET STOP
bit
bit
bit
bit
30 sec
24/12bit
H1 H10
ADJ bit
S10
D3
D2
D1
D0
S1
D1
W
MI1 MI10
MO1MO10
CE
WR
RD
D10
Y1 Y10
A3
A2
A1
A0
STDP
64Hz
S1
S
CF
1-sec carry
1-min carry
1-hour carry
CD
CF
CS0
ALE
CS1
•
S1~W~Y10 are time counter register
• C0~CF are control register
PIN CONFIGURATION
Address input
A0-A3:
D0-D3:
CSO , CS1:
RD:
WR:
ALE:
1
2
3
4
5
6
7
8
9
STD.P
CS0
24
23
22
21
20
19
18
17
16
15
14
13
VDD
XT
XT
NC
CS1
D0
NC
NC
D1
STD.P
1
2
3
4
5
6
7
8
9
18 VDD
Data input/output
CHIP SELECTS 0,1
READ enable
CS0
17
XT
NC
16
15
14
13
ALE
A0
XT
CS1
D0
ALE
A0
NC
A1
NC
A2
A3
WRITE enable
Address latch enable
Standard pulse output
XTAL oscillator input/output
+5V supply
A1
STD.P:
XT, XT:
VDD:
A2
D1
A3
12 D2
11 D3
10 WR
VSS:
ground
D2
D3
WR
10
11
12
RD
GND
RD
GND
18 pin Plastic DIP
24 pin Plastic Small Outline
Package
24
¡ Semiconductor
MSM6242B
REGISTER TABLE
Address Input
Address
Data
D1
Count
value
Register
Name
Description
Input
A3 A2
A1 A0
D3
S8
*
D2
S4
D0
S1
1-second digit register
10-second digit register
1-minute digit register
10-minute digit register
1-hour digit register
S1
S10
MI1
MI10
H1
S2
S20
mi2
mi20
h2
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 to 9
0 to 5
0 to 9
0 to 5
0 to 9
0
1
2
3
4
S40
mi4
mi40
h4
S10
mi1
mi10
h1
mi8
*
h8
PM/
AM
0 to 2
or 0 to 1
PM/AM, 10-hour digit
register
1
0
1
H10
h20
h10
5
0
*
d8
*
d4
*
d2
d20
mo2
*
d1
d10
mo1
MO10
y1
0 to 9
0 to 3
0 to 9
0 to 1
0 to 9
0 to 9
0 to 6
D1
D10
MO1
MO10
Y1
1-day digit register
10-day digit register
1-month digit register
10-month digit register
1-year digit register
10-year digit register
Week register
6
7
8
9
A
B
C
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
mo8
*
mo4
*
y8
y4
y2
y80
*
y40
w4
y20
w2
y10
Y10
W
w1
30
sec.
ADJ
IRQ
FLAG
1
1
0
1
CD
—
HOLD
D
BUSY
Control Register D
ITRPT
/STND
CE
CF
t1
t0
—
—
MASK
Control Register E
Control Register F
E
F
1
1
1
1
1
1
0
1
STOP REST
TEST 24/12
REST = RESET
ITRPT/STND = INTERRUPT/STANDARD
Note 1)
Note 2)
Note 3)
Bit * does not exist (unrecognized during a write and held at "0" during a read).
Be sure to mask the AM/PM bit when processing 10's of hour's data.
BUSY bit is read only. The IRQ FLAG bit can only be set to a "0". Setting the IRQ FLAG to a "1" is done by
hardware.
Note 4)
PM at 1 and AM at 0 for PM / AM bit.
Figure 1. Register Table
25
MSM6242B
¡ Semiconductor
OSCILLATOR FREQUENCY DEVIATIONS
0
1
0
Ta = 25°C
-1
-2
-3
-4
-50
5V
2V
-100
20
Ta (°C)
40
60
80
-60
0
0
1
2
3
4
5
6
-40 -20
V
DD (V)
Figure 2. Frequency Deviation (PPM) vs Temperature
Figure 3. Frequency Deviation (PPM) vs Voltage
Note:
1. The graghs above showing frequency deviation vs temperature/voltage are primarily characteristic of the
MSM6242B with the oscillation circuit described below.
XT
XT
Crystal: Type N0, P3 by kinseki (32.768 KHz)
CG, CD: 22pF (Temperature Characteristics: 0)
CG
CD
VDD
26
¡ Semiconductor
MSM6242B
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Input Voltage
Symbol
VDD
Condition
Rating
Unit
V
-0. 3 to 7
VI
Ta = 25°C
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-55 to +150
V
VO
Output Voltage
V
TSTG
Storage Temperature
°C
OPERATING CONDITIONS
Parameter
Power Supply Voltage
Standby Supply Voltage
Crystal Frequency
Symbol
VDD
Condition
Rating
Unit
—
—
—
—
4 to 6
2 to 6
V
VBAK
f(XT)
kHz
°C
32.768
TOP
Operating Temperature
-40 to +85
D.C. Characteristics
(VDD = 5V 10ꢀ, TA = -40 ~ +85)
Applicable
Terminal
Min.
Typ.
Parameter
Symbol
Condition
Max.
Unit
—
"H" Input Voltage
"L" Input Voltage
VIH1
VIL1
—
—
2.2
—
—
—
All input termin-
als except CS1, XT
V
0.8
Input terminals
other than
D0 ~ D3, XT
Input Leak Current
ILK
1
2
—
—
1/-1
VI = VDD/0V
µA
V
Input Leak Current
"L" Output Voltage
"H" Output Voltage
"L" Output Voltage
ILK
—
—
2.4
—
—
—
—
—
—
—
10/-10
0.4
D0 ~ D3
D0 ~ D3
VOL
1
IOL = 2.5mA
IOH = -400µA
IOL = 2.5mA
V = VDD/0V
VOH
—
VOL
IOFFLK
CI
2
0.4
V
STD.P
10
µA
OFF Leak Current
Input Capacitance
Input frequency
1MHz
All input
terminals
—
—
30
10
5
PF
µA
Current Con-
sumption
VDD
5V
=
f(xt)
=
IDD
1
2
—
—
—
—
32.768
KHz
~
VDD
Current Con-
sumption
VDD
2V
=
CS1
0
IDD
~
4/5VDD
—
—
—
—
"H" Input Voltage
"L" Input Voltage
VIH2
VIL2
VDD = 2 ~ 5.5V
V
CS1
1/5VDD
27
MSM6242B
¡ Semiconductor
SWITCHING CHARACTERISTICS
(1) WRITE mode (ALE = VDD
)
(VDD = 5V 10ꢀ Ta = -40 to +85°C)
Parameter
CS1 Set up Time
CS1 Hold Time
Symbol
tC1S
Condition
Min.
Max.
—
Unit
—
—
1000
1000
tC1H
—
Address Stable Before
WRITE
tAW
20
10
—
—
—
—
Address Stable After
WRITE
tWA
ns
—
—
—
—
—
—
WRITE Pulse Width
Data Set up Time
tWW
tDS
120
100
10
—
—
Data Hold Time
tDH
RD / WR Recovery Time
tRCV
60
CS1
VIH2
–
tC1H
tC1S
tAW
A0 ~ A3
VIH1
VIL1
VIH1
–
–
–
VIH1 = 2.2V
VIL1 = 0.8V
VIH2 = 4/5VDD
VIL2 = 1/5VDD
CS0
t
WA
tWW
tDS
tRCV
WR
tDH
D0 ~ D3
(INPUT)
VIH1
VIL1
–
–
Figure 4. Write Cycle — (ALE = VDD
)
(2) WRITE mode (With use of ALE)
(VDD = 5V 10ꢀ, Ta = -40 ~ +85°C)
Parameter
CS1 Set up Time
Symbol
tC1S
tAS
Condition
Min.
Max.
—
Unit
—
—
—
—
—
—
—
—
—
—
—
1000
25
Address Set up Time
Address Hold Time
ALE Pulse Width
—
tAH
—
25
tAW
—
40
ns
tALW
tWW
tWAL
tDS
—
ALE Before WRITE
WRITE Pulse Width
ALE After WRITE
DATA Set up Time
DATA Hold Time
10
—
120
20
—
—
100
10
tDH
—
tC1H
tRCV
CS1 Hold Time
—
1000
60
RD / WR Recovery Time
—
28
¡ Semiconductor
MSM6242B
tC1S
tAS
VIH2
–
CS1
tC1H
VIH1
VIL1
VIH1
VIL1
VIH1
VIL1
VIH1
VIL1
–
–
–
–
–
–
–
–
A0 ~ A3
VIH1 = 2.2V
VIL1 = 0.8V
VIH2 = 4/5VDD
VIL2 = 1/5VDD
CS0
tAH
ALE
tAW
tALW
tWAL
tWW
tDS
tRCV
WR
tDH
D0 ~ D3
(INPUT)
Figure 5. Write Cycle — (With Use of ALE)
(3) READ mode (ALE = VDD
)
(VDD = 5V 10ꢀ, Ta = -40 to +85°C)
Parameter
CS1 Set up Time
CS1 Hold Time
Symbol
tC1S
Condition
Min.
1000
1000
Max.
—
Unit
—
—
tC1H
—
Address Stable before
READ
—
—
tAR
20
—
—
ns
Address Stable after
READ
tRA
0
tRD
tDR
CL = 150pF
RD to Data
—
120
—
—
—
Data Hold
0
tRCV
—
RD / WR Recovery Time
60
VIH2
–
CS1
tC1S
tAR
tRA
tC1H
VIH1 = 2.2V
A0 ~ A3
VIH1
VIL1
VIH1
VIL1
–
–
–
–
VIL1 = 0.8V
VIH2 = 4/5VDD
VIL2 = 1/5VDD
VOH = 2.2V
VOL = 0.8V
CS0
tRCV
RD
tDR
tRD
D0 ~ D3
(OUTPUT)
VOH
VOL
–
–
"Z"
Figure 6. Read Cycle — (ALE = VDD
)
29
MSM6242B
¡ Semiconductor
(4) READ mode (With use of ALE)
(VDD = 5V 10ꢀ, Ta = -40 to +85°C)
Parameter
CS1 Set up Time
Address Set up Time
Address Hold Time
ALE Pulse Width
ALE before READ
ALE after READ
RD to Data
Symbol
tC1S
tAS
Condition
Min.
1000
25
Max.
—
Unit
—
—
—
—
tAH
—
—
—
25
—
tAW
40
ns
—
—
tALR
tRAL
tRD
10
—
10
CL = 150pF
120
—
—
tDR
—
—
—
DATA Hold
0
—
—
tC1H
tRCV
CS1 Hold Time
1000
60
RD / WR Recovery Time
VIH2
–
CS1
tAH
tAS
tC1S
tC1H
VIH1
VIL1
VIH1
VIL1
VIH1
VIL1
VOH
VOL
–
–
–
–
–
–
–
–
A0 ~ A3
VIH1 = 2.2V
CS0
VIL1 = 0.8V
VIH2 = 4/5VDD
VIL2 = 1/5VDD
VOH = 2.2V
VOL = 0.8V
tAW
ALE
tRAL
tALR
tRD
tRCV
RD
tDR
D0 ~ D3
(OUTPUT)
" Z "
Figure 7. Read Cycle — (With Use of ALE)
30
¡ Semiconductor
MSM6242B
PIN DESCRIPTION
Pin No.
Name
Description
RS
14
13
12
11
4
GS
19
16
15
14
5
D0
D1
D2
D3
A0
A1
A2
A3
Data Input/Output pins to be directly connected to a microcontroller bus for
reading and writing of the clock/calendar's registers and control registers. D0 = LSB
and D3 = MSB.
Address input pin for use by a microcomputer to select internal clock/calendar's
registers and control registers for Read/Write operations (See Function Table
Figure 1). Address input pins A0-A3 are used in combination with ALE for
addressing registers.
5
7
6
9
7
10
Address Latch Enable pin. This pin enables writing of address data when ALE = 1
and CSO = 0; address data is latched when ALE = 0 Microcontroller/Micro-
processors having an ALE output should connect to this pin; otherwise it should
be connected at VDD
ALE
4
3
10
8
Writing of data is performed by this pin.
When CS1 = 1 and CSO = 0, D0 ~ D3 data is written into the register at the rising
edge of WR.
13
11
WR
RD
Reading of register data is accomplished using this pin. When CS1 = 1, CSO = 0
and RD = 0, the data of this register is output to D0 ~ D3. If both RD and WR are
set at 0 simaltaneously, RD is to be inhibited.
2
2
CS0
Chip Select pins. These pins enable/disable ALE, RD and WR operation. CSO
and ALE work in combination with one another, while CS1 work independent
with ALE. CS1 must be connected to power failure detection as shown in Figure
18.
15
CS1
20
Output pin of N-CH OPEN DRAIN type. The output data is controlled by the
D1 data content of CE register. This pin has a priority to CSO and CS1.
Refer to Figure 9 and FUNCTIONAL DESCRIPTION OF REGISTERS.
STD.P
1
1
XT
22
23
16
17
32.768 kHz crystal is to be connected to these pins.
When an external clock of 32.768 kHz is to be used for MSM6242's oscillation
source, either CMOS output or pull-up TTL output is to be input from XT, while
XT should be left open.
XT
24
12
Power supply pin. +2 ~ +6V power is to be applied to this pin.
Ground pin.
VDD
18
9
GND
VDD
RFB 5M
Ω
XT
X'tal
STD.P OUTPUT
C1
32.768 kHz
N-CH
VDD OR GND
C2 XT
C1 = C2 = 15 ~ 30pF
The impedance of the crystal should be less than 30k
Ω
Figure 8. Oscillator Circuit
Figure 9.
31
MSM6242B
¡ Semiconductor
FUNCTIONAL DESCRIPTION OF REGISTERS
S1, S10, MI1, MI10, H1, H10, D1, D10, MO1, MO10, Y1, Y10, W
a) These are abbreviations for SECOND1, SECOND10, MINUTE1, MINUTE10, HOUR1,
HOUR10, DAY1, DAY10, MONTH1, MONTH10, YEAR1, YEAR10, and WEEK. These
values are in BCD notation.
b) All registers are logically positive. For example, (S8, S4, S2, S1) = 1001 which means 9
seconds.
c) Ifdataiswrittenwhichisoutoftheclockregisterdatalimits, itcanresultinerroneousclock
data being read back.
d) PM/AM, h20, h10
In the mode setting of 24-hour mode, PM/AM bit is ignored, while in the setting of 12-hour
mode h20 is to be set. Otherwise it causes a discrepancy. In reading out the PM/AM bit in
the24-hourmode,itiscontinuouslyreadoutas0. Inreadingouth bitinthe12-hourmode,
0 is written into this bit first, then it is continuously read out as 02u0 nless 1 is being written
into this bit.
e) Registers Y1, Y10, and Leap Year. The MSM6242B is designed exclusively for the Christian
Eraandiscapableofidentifyingaleapyearautomatically. Theresultofthesettingofanon-
existant day of the month is shown in the following example: If the date February 29 or
November 31, 1985, was written, it would be changed automatically to March 1, or
December 1, 1985 at the exact time at which a carry pulse occurs for the day's digit.
f) The Register W data limits are 0 – 6 (Tabel 1 shows a possible data definition).
TABLE 1
Day of Week
Sunday
w4
0
w2
0
w1
0
Monday
0
0
1
Tuesday
Wednesday
Thursday
Friday
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
Saturday
Using HOLD Bit
Not Using HOLD Bit
Read Register
1 ~ W
←
HOLD Bit
1
First
S
Read BUSY Bit
Data of
S1 ~ W
Register
←
DATA
*
NO
HOLD Bit
Busy Bit= O?
YES
Read Register
S1 ~ W
Second
←
0
DATA1 = DATA2
Write data into
or Read data from
registers S1 ~ W
* In the inside of LSI, the CLEAR of BUSY bit is performed when
HOLD bit = 0, but, if the period of HOLD bit =0 is extermely
narrow as compared with the period of HOLD bit = 1, there is
some case that the CLEAR of BUSY bit delays so that the
BUSY bit can be cleared by sampling HOLD bit = 0 at approximate
16KHz. It is recommended to allow an idling time of 62ms or more.
Idling Time
NO
DATA1 = DATA2
YES
←
HOLD Bit
0
Figure 10. Reading and Writing of Registers S1 ~ W
32
¡ Semiconductor
MSM6242B
Reading Method 3 when Not Using HOLD Bit
Initialization only at power ON
Reading Method 2 when Not Using HOLD Bit
Initialization only at power ON
•*1 and *2 represent the minimum required
•*1 and *2 represent the minimum required
time unit.
time out.
t1
t0
*1
*2
t1
t0
*1
*2
For example
For example
t1 = 0 and tO = 1 when required to a
unit of second;
t1 = 1 and tO = 0 when required to a
unit of minute; and
t1 = 1 and tO = 1 when required to a
unit of hour;
t1 = 0 and tO = 1 when required to a
ITRPT/STNT
MASK
1
0
ITRPT/STNT
MASK
1
0
unit of second;
t1 = 1 and tO = 0 when required to a
unit of minute; and
t1 = 1 and tO = 1 when required to a
unit of hour;
CPU senses the
interruption.
0
IRQ FLAG
WAIT t
REGISTER CD READ
See Note
below
NO
Retried the reading, since a
carry occurred during the
operation.
IRQ FLAG = 1
YES
The other IC causes
the interruption.
TIME DATA READ
The interruption is caused by
this IC due to the occurrence
of a carry.
WAIT t
REGISTER CD READ
TIME DATA READ
NO
(Note)
IRQ FLAG = 0
Do this process within the following
time requirements by combination
between t1 and t0:
The IRQ FLAG is cleared to
read the next time data.
0
IRQ FLAG
YES
Normal read
t1 = 0 and tO = 1 . . . Less than 1 second
t1 = 1 and tO = 0 . . . Less than 1 minute
t1 = 1 and tO = 1 . . . Less than 1 hour
END
t
: 12 HOUR MODE . . . 35µS
24 HOUR MODE . . . 3µS
CD REGISTER (Control D Register)
a) HOLD (D0) –
Setting this bit to a "1" inhibits the 1Hz clock to the S1 counter, at which
time the Busy status bit can be read. When Busy = 0, register's S ~ W
can be read or written. During this procedure if a carry occurs t1he S1
counterwillbeincrementedby1secondafterHOLD=0(thiscondition
is guaranteed as long as HOLD = 1 does not exceed 1 second in
duration). If CS1 = 0 then HOLD = 0 irrespective of any condition.
Status bit which shows the interface condition with microcontroller/
microprocessors. As for the method of writing into and reading from
S1 ~ W (address φ ~ C), refer to the flow chart described in Figure 10.
b) BUSY (D1) –
c) IRQ FLAG (D2) – This status bit corresponds to the output level of the STD.P output.
When STD.P = 0, then IRQ = 1; when STD.P = 1, then IRQ = 0. The IRQ
FLAG indicates that an interrupt has occurred to the microcomputer if
IRQ = 1. When D0 of register C (MASK) = 0, then the STD.P output
changes according to the timingEset by D3 (t1) and D2 (t0) of register E.
When D1 of register E (ITRPT/STND) = 1 (interrupt mode), the STD.P
output remains low until the IRQ FLAG is written to a "0". When IRQ
= 1 and timing for a new interrupt occurs, the new interrupt is ignored.
When ITRPT/STND = 0 (Standard Pulse Output mode) the STD.P
output remains low until either "0" is written to the IRQ FLAG;
otherwise, the IRQ FLAG automatically goes to "0" after 7.8125ms.
When writing the HOLD or 30 second adjust bits of register D, it is
necessary to write the IRQ FLAG bit to a "1".
d) ±30 ADJ (D3) –
When 30-second adjustment is necessary, a "1" is written to bit D3
during which time the internal clock registers should not be read from
or written to 125µs after bit D3 = 1 it will automatically return to a "0",
and at that time reading or writing of registers can occur.
33
MSM6242B
¡ Semiconductor
START
START
30-SECOND
ADJ BIT = 1
30-SECOND
ADJ BIT = 1
READ 30-SECOND
ADJ BIT
NO
125µs PASS?
YES
END
(B)
NO
30-SECOND
ADJ BIT = 0?
YES
END
(A)
Figure 11. Writing 30-Second Adj. bit (Two Ways A, B)
CE REGISTER (Control E Register)
a) MASK (D0) –
This bit controls the STD.P output. When MASK = 1, then STD.P
= 1 (open); when MASK = 0, then STD.P = output mode. The
relationship between the MASK bit and STD.P output is shown
Figure 12.
b) ITRPT/STND (D1) –
The ITRPT/STND input is used to switch the STD.P output
between its two modes of operation, interrupt and Standard
timing waveforms. When ITRPT/STND = 0 a fixed cycle wave-
form with a low-level pulse width of 7.8125ms is present at the
STD.P output. At this time the MASK bit must equal 0, while the
period in either mode is determined by T0 (D2) and T1 (D3) of
Register E.
c) T0 (D2), T1 (D3) –
These two bits determine the period of the STD.P output in both
interrupt and Fixed timing waveform modes. The tables below
show the timing associated with the T0, T1 inputs as well as their
relationship to INTRPT/STND and STD.P.
"INTERRUPT" DOES
NOT OCCUR BECAUSE
MASK BIT IS "1"
OUTPUT DOES NOT OCCUR
AT LOW LEVEL BECAUSE
MASK BIT IS "1"
"1"
"1"
"1"
"1"
MASK BIT "0"
STD.P OUTPUT
"0"
"0"
"0"
MASK BIT
STD.P
OUTPUT
OPEN
OPEN
LOW LEVEL
LOW LEVEL
"INTERRUPT" TIMING
OUTPUT TIMING
AUTOMATIC RETURN
WRITE "0" INTO IRQ FLAG BIT
INTRT/STND BIT = "1"
INTRT/STND BIT = "0"
Figure 12.
TABLE 2
Duty CYCLE of "0" level when
ITRPT/STND bit is "0".
t1
t0
Period
0
0
1
1
0
1
0
1
1/64 second
1 second
1 minute
1 hour
1/2
1/128
1/7680
1/460800
34
¡ Semiconductor
MSM6242B
The timing of the STD.P output designated by T1 and T0 occurs the moment that a carry occurs to a clock digit.
(EXAMPLE) WHEN t1 = 1, t0 = 1 and MASK = 0.
PM1:00
PM12:00
OPEN
LOW LEVEL
WHEN ITRPT/STND
BIT is "1"
STD.P OUTPUT
WHEN ITRPT/STND
BIT is "0"
OPEN
LOW LEVEL
d) The low-level pulse width of the fixed cycle waveform (ITRPT/STND = 0) is 7.8125ms
independent of T0/T1 inputs.
e) The fixed cycle waveform mode can be used for adjustment of the oscillator frequency time
base. (See Figure 14).
f) During ±30 second adjustment a carry can occur that will cause the STD.P output to go low
when T0/T1 = 1,0 or 1,1. However, when T1/T0 = 0, 0 and ITRPT/STND = 0, carry does
not occur and the STD.P output resumes normal operation.
g) The STD.P output is held (frozen) at the point at which STOP = 1 while ITRPT/STND = 0.
h) No STD.P output change occurs as a result of writing data to registers S1 ~ H1.
CF REGISTER (Control F Register)
a) REST (D0) –
"RESET"
This bit is used to clear the clock's internal divider/counter of less than a
second. When REST = 1, the counter is Reset for the duration of REST. In
order to release this counter from Reset, a "0" must be written to the REST
bit. If CSI = 0 then REST = 0 automatically.
b) STOP (D1) –
The STOP FLAG Only inhibits carries into the 8192Hz divider stage.
There may be up to 122µs delay before timing starts or stops after
changing this flag; 1 = STOP/0 = RUN.
"1"
"1"
"1"
STOP BIT
"0"
"0"
"0"
"0"
TIMING OF
"CARRY"
TO 8192Hz
"CARRY" EXECUTED
"CARRY" NOT EXECUTED
Figure 13
c) 24/12 (D2) –
This bit is for selection of 24/12 hour time modes. If D2 = 1–24 hour mode
is selected and the PM/AM bit is invalid. If D2 = 0–12 hour mode is
selected and the PM/AM bit is valid.
Setting of the 24/12 hour bit is as follows:
1) REST bit = 1
"24/HOUR/
12 HOUR"
2) 24/12 hour bit = 0 or 1
3) REST bit = 0
*
REST bit must = 1 to write to the 24/12 hour bit.
d) TEST (D3) –
When the TEST flag is a "1", the input to the SECONDS counter comes
from the counter/divider stage instead of the 15th divider stage. This
makes the SECONDS counter count at 5.4163KHz instead of 1Hz. When
TEST=1(TestMode)theSTOP&REST(Reset)flagsdonotinhibitinternal
counting. When Hold = 1 during Test (Test = 1) internal counting is
inhibited; however, when the HOLD FLAG goes inactive (Hold = 0)
counter updating is not guaranteed.
35
MSM6242B
¡ Semiconductor
TYPICAL APPLICATION INTERFACE WITH MSM6242B AND
MICROCONTROLLERS
MSM6242B
MSM6242B
8085
AD3
AD2
AD1
AD0
8085
A/D
D3
D2
D1
D0
D3
D2
D1
D0
A8 ~ A12
A3
A3
A2
A1
A0
CS0
A8 ~ A15
S1
S0
IO/M
A2
A1
A0
CS0
A8 ~ A15
S1
S0
IO/M
ALE
RD
WR
ALE
RD
WR
ALE
RD
WR
R1
R2
R1
R2
RD
WR
MEMORY MAPPED
I/O MAPPED
Note : If 8085 does not enter into the state of HALT or HOLD during CS1 = "H" of
MSM6242B, R1 and R2 are not required
.
Figure 15.
MSM6242B
MSM6242B
Z80
MCS48
D3
D2
D1
D0
D3
D2
D1
D0
BUS3
BUS2
BUS1
BUS0
D3
D2
D1
D0
A3
A2
A1
A0
A3
A2
A1
A0
A3
A2
A1
A0
DECODER
DECODER
CS0
A4 ~ A15
IORQ
MREQ
RD
VDD
BUS 4-7
CS0
ALE
ALE
RD
WR
ALE
RD
WR
G1
RD
WR
WR
G2
Note : It depends upon the switching
characterisrics decided by a X'tal used
for a Z80 that either of IORQ and MREQ
is used.
Figure 16.
Figure 17.
36
¡ Semiconductor
MSM6242B
TYPICAL APPLICATIONS — INTERFACE WITH MSM80C49
100µf
3.9V
★
4.7µf (tantalum)
LITHIUM
BATTERY
★
(VFWD = < 0.3V)
★
i.e. GERMANIUM
DIODE
26
18
18K
22pf
4.553 KHz
22pf
15pf
VDD
VDD
17
16
1
3
2
3
6
11
8
XT
SDT.P
X1
X2
INT
ALE
RD
ALE
RD
32.768 KHz
8
10
10
XT
WR
WR
5-35pf
MSM
80C49RS
MSM
6242BRS
4/14
5/13
6/12
7/11
2
12
13
14
15
19
DB
A/D0
0
1
2
3
7
40
VCC
DB
DB
DB
DB
A/D1
A/D2
A/D3
CS0
1
T0
38
15
CS1
P27
34
9
TR1
P
VSS
17
10K
VSS
20
820
TR1 = 2N2907
TR2 = 2N2907
TR3 = 2N2222
★ = 1N4148
1.8K
TR3
1.8K
1.8K
TR2
★
220
2
3
7
5
RS232
1.8K
★
1.8K
DB25
CONNECTOR
10µf
20
RS232
INTERFACE
220
5.2V
Figure 18.
37
MSM6242B
¡ Semiconductor
APPLICATION NOTE
1. Power Supply
VDD = 5V
STD.P
START
Power On
Output = undifined
←
←
TEST Bit
REST Bit
0
0
1* = 2*
(1 or 0)
←
24/12 Bit 1*
←
STOP Bit
1
←
REST Bit
0
←
24/12 Bit 2*
Set the current
time
←
←
HOLD Bit
STOP Bit
0
0
Start Operation
2. Adjustment of Frequency
VDD
Screwdriver
18 17 16
VDD XT XT
CD, CF = (0, 0, 0, 0)
CE = (t1, t0, 0, 0)
SDT.P
c
d
VDD
1
2
3
0.1 INCH
b
Frequency
counter
2
1
Eye
CD ~ CF are to be set at as described in the
figure and the capacitor is to be adjusted
to meet the settle frequency of t0 and t1.
If the right oscillation can not be obtained,
VDD XT XT
1. Check the waveform of XT
2. Check CD ~ CF content
3. Check the noise
≥ 0.3 INCH
≥ 0.2 INCH
1
2
a
a
b
: INHIBIT
38
¡ Semiconductor
MSM6242B
3. CH1 (Chip Select)
VIH and V of CH has 3 functions.
a) To acIcLomplis1h the interface with a microcontroller/microprocessor.
b) To inhibit the control bus, data bus and address bus and to reduce input gate pass
current in the stand-by mode.
c) To protect internal data when the mode is moved to and from standby mode.
To realize the above functions:
a) More than 4/5 V shoud be applied to the MSM6242B for the interface with a
microcontroller/DmDicroprocessor in 5V operation.
b) In moving to the standby mode, 1/5 V should be applied so that all data buses should
be disabled. In the standby mode, appDrDox. 0V should be applied.
c) To and from the standby mode, obey following Timing chart.
To Standby Mode
From Standby Mode
4V
4 ~ 6V
2 ~ 4V
VDD
4V
2µs (MIN)
2µs (MIN)
VDD
2
5
4
5
CS1
VDD
1
5
VDD
CS0 : H
or WR : H
4. Set SDT.P at alarm mode
Set alarm at 9:00
←
MASK BIT
0
←
ITRPT/STND BIT
1
←
t1, t0
1
Start interruption
CPU Activation
Read Register CD
D2 = 1?
NO
YES
Repeat
Read H10 and
H10 Cotent
NO
AM 9:00?
YES
CPU HALT
or
CPU STAND BY
39
MSM6242B
¡ Semiconductor
TYPICAL APPLICATION — POWER SUPPLY CIRCUIT
RIPPLE
OPERATING: 20mV P-P
BATTERY BACKUP: 0mV
VCE (SAT.) = 0.1V
RL
M
+5V
+5V
RL
4.7µf
22µf
C
100Ω
VDD
4.7µf
VDD
B
51K
10K
10K
100Ω
MSM
6242B
MSM
6242B
1.5 x 2 = 3V
DRY CELLS
1.2 x 3 = 3.6V
Ni – Cd
VSS
VSS
Figure 20.
Figure 19.
220Ω
~
~
6.5V
VDD
100Ω
RL
D1
+5V
MSM
6242B
4.7µf
1.2 x 3 = 3.6V
Ni – Cd
VSS
Figure 21.
4.7µF: tantalum
SUPPLEMENTARY DESCRIPTION
•
When "0" is written to the IRQ FLAG bit, the IRQ FLAG bit is cleared. However, if "0" is
assigned to the IRQ FLAG bit when written to the other bits, the 30-sec ADJ bit and the
HOLD bit, the IRQ FLAG = 1 and was generated before the writing and IRQ FLG = 1
generated in a moment then will be cleared. To avoid this, always set "1" to the IRQ
FLAG unless "0" is written to it intentionally. By writing "1" to it, the IRQ FLAG bit
does not become "1".
•
*
Since the IRQ FLAG bit becomes "1" in some cases when rewriting either of the t1, t0, or
ITRPT/STND bit of register CE, be sure to write "0" to the IRQ FLAG bit after writing to
make valid the IRQ FLAG = 1 to be generated after it.
The relationship between SDT.P OUT and IRQ FLAG bit is shown below:
open
"L"
STD.P OUT
IRQ FLAG bit
1
0
approx. 1.95 ms
40
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