MSM64P155L-NGS-BK [OKI]
Microcontroller, 4-Bit, OTPROM, 0.066MHz, CMOS, PQFP100, QFP-100;
| 型号： | MSM64P155L-NGS-BK |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Microcontroller, 4-Bit, OTPROM, 0.066MHz, CMOS, PQFP100, QFP-100 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总61页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSM64P155
User's Manual
CMOS 4-bit microcontroller
FIRST EDITION
ISSUE DATE: Mar. 1996
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
8.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 1996 Oki Electric Industry Co., Ltd.
Printed in Japan
Preface
MSM64P155 is a 4-bit microcontroller, which uses
built-in one time PROM (OTP) in place of built-in mask
ROM in MSM64155A.
MSM64P155ismanufacturedwiththeN-wellEPROM
process instead of the P-well CMOS process.
That is why the polarity of MSM64P155's power
supply is different than the polarity of the chip with the
P-well CMOS structure.
OTP version chips alone are not supplied to custom-
ers.
This manual explains the specific hardware of
MSM64P155 and the differences from the mask ROM
version of MSM64155A.
See "MSM64155 User's Manual" for further reference
relating to other hardware and instruction set.
TABLE OF CONTENTS
Chapter 1 General Description
1.1 Overview .................................................................................................................1-1
1.2 Features ..................................................................................................................1-1
1.3 Block Diagram ........................................................................................................1-3
1.4 Pin Configuration ....................................................................................................1-4
1.5 Explanation of Pins .................................................................................................1-5
1.5.1 Explanation of Each Pin................................................................................1-5
1.5.2 PROM-Related Pins....................................................................................1-10
1.5.3 Processing of Unused Pins ........................................................................1-11
Chapter 2 Power Supply System
2.1 Overview .................................................................................................................2-1
2.2 Power Supply System Circuit Configuration ..........................................................2-2
2.3 Logic Power Supply and Backup Circuits ..............................................................2-3
2.3.1 Configuration of Logic Power Supply...........................................................2-3
2.3.2 Operations of Optional 1.5V Logic Power Supply Circuits...........................2-4
2.3.3 Operations of Optional 3.0V Logic Power Supply Circuits...........................2-4
Chapter 3 Crystal Oscillation Circuit
3.1 Overview .................................................................................................................3-1
3.2 Configuration of Crystal Oscillation Circuit ............................................................3-1
Chapter 4 PROM
4.1 Overview .................................................................................................................4-1
4.2 Explanation of Pins .................................................................................................4-1
4.3 PROM Mode ...........................................................................................................4-3
4.3.1 Setting the PROM Mode ..............................................................................4-3
4.3.2 PROM Mode Functions ................................................................................4-3
4.3.3 Connection to the EPROM Writer.................................................................4-4
Chapter 5 TST3 Pin
5.1 Overview .................................................................................................................5-1
5.2 Registers To Be Changed By TST3 ........................................................................5-3
Appendixes
Appendix A Package Dimensional Drawing .................................................... Appendix-1
Appendix B Electrical Characteristics ............................................................. Appendix-2
Chapter 1
GENERAL DESCRIPTION
CHAPTER 1
1.1
GENERAL DESCRIPTION
Overview
MSM64P155 is a microcontroller which uses built-in one time PROM (OTP) in place of
built-in ROM of MSM64155A.
SincetheMSM64P155hasadifferentconfigurationofthemaskROMwithP-wellCMOS
configuration, it is manufactured with the N-well EPROM process. That is why the
polarity of the power source used for LCD bias generation is reversed, and the
arrangement of additional circuits is different from the arrangement of this chip.
In addition, unlike the mask ROM version, the PROM (OTP version) chip alone has no
supply.
For these reasons, this OTP version of MSM64P155 should be used mainly for
verification of application program functions.
TheMSM64P155hastwooperationmodes;microcontrolleroperationmodeandPROM
mode. The microcontroller operation mode is a mode to make the same operation as
a mask ROM and the PROM mode is a mode to write/read PROM.
The descriptions on the microcontroller operation mode are omitted in this manual.
Therefore, see "MSM64155A User's Manual". This manual explains different
specifications from the mask ROM version in Chapters 2 and 3, and Chapter 4 explains
the PROM mode.
1.2
Features
1) A Rich Set of Instructions Including Byte Calculating Instructions
• 148 types of instructions
• Byte addition and subtraction, byte transmission, byte comparing instructions
• Bit operation instructions
• Data exchange instructions
2) Rich Addressing Modes
• Two types of indirect addressing modes for HL registers and XY registers
• Bit operations for all data memory areas
• Byte calculation for all data memory areas
3) Operating Frequency
:Crystal Oscillation at 32.768 kHz
(minimum instruction execution time: 91µs)
:RC Oscillation at about 32 kHz
4) Built-In Program Memory :4064 bytes (PROM)
5) Built-In Data Memory
:256 nibbles
1-1
6) I/O Ports
:a total of 18 ports
• 4 bit input-output ports (selectable open drain output/CMOS output, selectable
additional pull-down resistance input) ¥ 2
• 2-bit input port (selectable additional pull-down resistance input)
• 4-bit input port (selectable additional pull-down resistance input)
• 4-bit output port (CMOS output)
7) Melody Output: 2 outputs
8) LCD Driver: a total of 64 drivers
• Common driver ¥ 4
• Segment driver ¥ 60
• 1/4 duty, during 1/3 bias: 240 segments (60 ¥ 4)
• 1/3 duty, during 1/3 bias: 180 segments (60 ¥ 3)
9) Event Counter: 1 channel
10) Interrupt Sources: 10 sources
• Four external sources, four time base sources, two melody sources
(When TST3="1", six time base sources)
11) External Appearance
• Flat package with 100 pins
Product name:
MSM64P155-NGS-BK (Blanked PROM)
MSM64P155L-NGS-BK (Blanked PROM)
MSM64P155-XXXGS-BK (Written PROM)
MSM64P155L-XXXGS-BK (Written PROM)
12) Operating Power Supply Voltage: (mask option)
1.5 V : MSM64P155
3.0 V : MSM64P155L
13) Clock Generation Circuit (mask option)
• Crystal/RC oscillation
1-2
BIAS
TR2
TR0
ALU
TR1
PROGRAM
COM1
COM2
COM3
COM4
DATA/ADDRESS
PROM
4064B
PCH
PCM PCL
A11~A8
C
A7~A0
SEG0
LCD
RAM
256N
B
A
H
L
X
Y
DB7~0
(8)
(8)
SEG59
OSC0
OSC1
SP
ROMR
TIMING
CONTROLLER
CLK
INTC
MD0
MD0
MD0
MD1
4
RESET
TBC
RST
TST
INT
INT
INT
TST1
TST2
TST3
MD1
MD1
PORT ADDRESS
DB7~0
INT
INT
INT
INT
VSS
CAPR
PORT2
EVENT
PORT3
PORT4
PORT6
PORT7
Items inside the dotted
line indicate the CPU core
(nX-4/20).
1.4
Pin Configuration
Figure 1-2 shows the pin configuration of MSM64P155.
RESET
OSC0
OSC1
VPP
1
2
3
4
5
6
7
8
9
80 SEG11
79 SEG12
78 SEG13
77 SEG14
76 SEG15
75 SEG16
74 SEG17
73 SEG18
72 SEG19
71 SEG20
70 SEG21
69 SEG22
68 SEG23
67 SEG24
66 SEG25
65 SEG26
64 SEG27
63 SEG28
62 SEG29
61 SEG30
60 SEG31
59 SEG32
58 SEG33
57 SEG34
56 SEG35
55 SEG36
54 SEG37
53 SEG38
52 SEG39
51 SEG40
P2.3
P2.2
P2.1
P2.0
P3.1
P3.0 10
P4.3 11
P4.2 12
P4.1 13
P4.0 14
P6.3 15
P6.2 16
P6.1 17
P6.0 18
P7.3 19
P7.2 20
P7.1 21
P7.0 22
VSS 23
MD0 24
MD0 25
MD1 26
MD1 27
TST3 28
TST2 29
TST1 30
Note: Please do not connect anything to the NC pin.
Figure 1-2 Pin Configuration of MSM64P155 (QFP)
1-4
1.5
Explanation of Pins
1.5.1 Explanation of Each Pin
Table 1-1 shows basic functions of each of the MSM64P155 pins and Table 1-2 shows
their secondary functions.
Table 1-1 (a) Explanation of Pins (Basic Functions)
Pin
Name
Pin Input/
No. Output
Type
Function
VSS
23
—
—
Digital 0V power supply
Digital plus side power supply (for 1.5V specs)
LCD drive bias output (for 3.0V specs)
Digital plus side power supply (for 3.0V specs)
LCD drive bias output (for 1.5V specs)
LCD drive bias output (+4.5V)
VDD1
100
Power
Supply
VDD2
99
—
VDD3
C1
98
97
96
4
—
—
—
—
LCD drive bias generating condenser connection pin
C2
VPP
Plus side power supply for PROM writing (+12.5V)
Clock oscillation pin:
OSC0
2
3
Input
Oscillation
Test
Connect to crystal oscillator (32.768 kHz) and condenser
(10 pF~30 pF) or resistor (1MW) are connected.
OSC1
Output
TST1
TST2
30
29
Input Input pin for tests
These are pulled down to VSS internally.
Input
When this pin is set to "H" level, the 256Hz and 4Hz interrupts are
enabled, and the MSM64P155 can be used as an OTP version of the
MSM64152A, MSM64153A and MSM64158A.
TST3
28
Input
System reset input:
When this pin reaches the level "L" fi "H", internal status initialization is
conducted and instructions are executed from address 000H.
Built-in pull-down resistance on VSS.
Reset
RESET
1
Input
1-5
Table 1-1 (b) Explanation of Pins (Basic Functions)
Pin
Name
Pin Input/
Function
Type
No. Output
P2.0
P2.1
P2.2
P2.3
8
7
6
5
Input 4-bit input port (port 2):
This is a 4-bit input port permitting selection of the pull-down resistance
input/high impedance input for each bit through the controller register
of port 2 (P2CON).
Its secondary functios are trigger input of capture circuits and an
external interrupt function.
Also, system reset is run when P2.0~P2.3 reach the "H" level.
P3.0
P3.1
10
9
Input 2-bit input port (port 3):
This is a 2-bit input port permitting selection of the pull-down resistance
input/high impedance input through the controller register of port 3
(P3CON).
Its secondary functions are input functions for the event counter by
P3.1 and an external interrupt by P3.0.
P4.0
14 Output 4-bit output port (port 4):
This is a 4-bit CMOS output port.
P4.1
P4.2
P4.3
P6.0
13
12
11
18
Port
Input/ 4-bit input/output port (port 6):
Output
This is a 4-bit input/output port permitting selection of input/output
P6.1
P6.2
P6.3
17
16
15
through the controller register (P6CON) of port 6 (P6CON), selection
of the pull-down resistance input/high impedance input during input,
and selection of open drain output/CMOS output during output
operations.
Its secondary function is to allocate external interrupt functions.
P7.0
P7.1
P7.2
P7.3
22
21
20
19
Input/ 4-bit input/output port (port 7):
Output
This is a 4-bit input/output port permitting selection of input/output
through the controller register of port 7 (P7CON), selection of the
pull-down resistance input/high impedance input during input, and
selection of open drain output/CMOS output during output.
Its secondary function is external interrupt function.
MD0
MD0
MD1
25 Output This is the output pin of melody driver 0.
24 Output This is the reversed phase output pin for MD0 output.
26 Output This is the output pin of melody driver 1.
27 Output This is the reversed phase pin of MD1 output.
95 Output These are the LCD common signal output pins.
94 Output
Melody
Driver
MD1
COM1
COM2
COM3
COM4
LCD Driver
93 Output
92 Output
1-6
Table 1-1 (c) Explanation of Pins (Basic Functions)
Pin
Name
Pin Input/
Function
Type
No. Output
SEG0
SEG1
91 Output
90 Output
89 Output
88 Output
87 Output
86 Output
85 Output
84 Output
83 Output
82 Output
81 Output
80 Output
79 Output
78 Output
77 Output
76 Output
75 Output
74 Output
73 Output
72 Output
71 Output
70 Output
69 Output
68 Output
67 Output
66 Output
65 Output
64 Output
63 Output
62 Output
61 Output
60 Output
59 Output
58 Output
57 Output
56 Output
LCD segment signal output pins
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
LCD
Driver
1-7
Table 1-1 (d) Explanation of Pins (Basic Functions)
Pin
Name
Pin Input/
Function
Type
No. Output
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
(NC)
55 Output
54 Output
53 Output
52 Output
51 Output
50 Output
49 Output
48 Output
47 Output
46 Output
45 Output
44 Output
43 Output
42 Output
41 Output
LCD segment signal output pins
LCD
Driver
40
—
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
39 Output
38 Output
37 Output
36 Output
35 Output
34 Output
33 Output
32 Output
31 Output
1-8
Table 1-2 Explanation of Pins (Secondary Functions)
Pin
Name
Pin Input/
Function
Type
No. Output
P2.0
P2.1
P2.2
P2.3
8
7
6
5
Input Secondary functions of P2.0~P2.3:
An external interrupt input pin which enables reception through a
modified level.
Also enables selection between allowed/prohibited for each bit interrupt
through the P2 interrupt enable register (P21E).
The system reset mode is activated after all P2.0~P2.3 pins reached the
"H" level for at least two seconds.
Secondary functions of P2.0 and P2.1:
Trigger input pin for capture circuits.
External
P3.0
10
Input Secondary function of P3.0:
Interrupt
External interrupt input pin
Reception of rising and falling edge signal and rising/falling
signal enable on both edges by external interrupt input pins.
Input Secondary function of P6.0~P6.3:
An external interrupt input pin which enables reception through
a modified level.
P6.0
P6.1
P6.2
P6.3
P7.0
P7.1
P7.2
P7.3
P3.1
18
17
16
15
22
21
20
19
9
Input Secondary function of P7.0~P7.3:
An external interrupt input pin which enables reception through
a modified level.
Event counter
input
Input Secondary function of P3.1:
Input pin for event counter.
1-9
1.5.2 PROM-Related Pins
Table 1-3 shows pins used to write program data to MSM64P155.
Table 1-3 Explanation of Pins (PROM Functions)
Pin
Name
Pin Input/
Function
Type
No. Output
VSS
23 Output 0V power supply
VDD1*
100
99
4
—
—
—
Plus side power supply pin (+5V supplies)
Plus side power supply pin (+5V supplies)
PROM write power supply (+12.5V supplied)
VDD2*
VPP
RESET
1
Input PROM write setting pins
PROM mode is set by H level input
TST1
30
29
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
Input
Input
I/O
TST2
SEG0/D0
SEG1/D1
SEG2/D2
SEG3/D3
SEG4/D4
SEG5/D5
SEG6/D6
SEG7/D7
SEG8/CE
SEG9/OE
SEG10/A0
SEG11/A1
SEG12/A2
SEG13/A3
SEG14/A4
SEG15/A5
SEG16/A6
SEG17/A7
SEG18/A8
SEG19/A9
SEG20/A10
SEG21/A11
SEG22
Pins for writing and reading of program data
I/O
I/O
I/O
I/O
PROM
Function
I/O
I/O
I/O
I/O
PROM chip enable pin
I/O
PROM output enable signal
Input Program address input pins
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input Normally input H level
* PROM mode should be supplied with 5V both to VDD1 and VDD2.
1-10
1.5.3 Processing of Unused Pins
Table 1-4 shows processing of unused pins.
Table 1-4 Processing of Unused Pins
Pin
Recommended Pin Connection
TST1~3
Open
P2.0~P2.3
P3.0~P3.1
P4.0~P4.3
P6.0~P6.3
"L" level or open
"L" level or open
Open
For input setting: "L" level or open (initial value is input mode)
For output setting: Open
P7.0~P7.3
For input setting: "L" level or open (initial value is input mode)
For output setting: Open
MD0, MD1
MD0, MD1
COM1~4
Open
Open
Open
SEG0~59
1-11
Chapter 2
POWER SUPPLY SYSTEM
CHAPTER 2 POWER SUPPLY SYSTEM
2.1
Overview
MSM64P155 (OTP version) is manufactured using EPROM process for the N-well that
is different from the P-well CMOS structure of the mask ROM of MSM64155A (mask
ROM). Because of this, the polarity of the power supply system is completely reversed
when compared to the mask ROM. In addition, note that the names of the power supply
pins have also been changed.
Table 2-1 shows a table of the power supply pin functions and Table 2-2 shows the
differences between MSM64155A and MSM64P155.
Table 2-1 List of Power Supply Pin Functions
Pin
Name
Pin
No.
Input/
Output
Function
VSS
23
—
—
0V power supply
Plus side power supply (for 1.5V specifications)
VDD1
100
Bias output for LCD drive (+1.5V)
(for 3.0V specifications)
VDD2
99
—
Plus side power supply (for 3.0V specifications)
Bias output for LCD drive (+3.0V)
(for 1.5V specifications)
VDD3
VPP
98
4
—
—
Bias output for LCD drive (+4.5V)
Plus side power supply for PROM write (+12.5V)
Table 2-2 Differences between MSM64P155 and MSM64155A
MSM64P155
VSS (0V)
MSM64155A
VDD (0V)
Different from MSM64P155
—
VDD1 (+1.5V)
VDD2 (+3.0V)
VDD3 (+4.5V)
VPP (+12.5V)
VSS1 (-1.5V)
VSS2 (-3.0V)
VSS3 (-4.5V)
VSSL
Power supply has reversed phase with 1.5V specifications
Power supply has reversed phase with 3.0V specifications
—
No external capacitor is required
2-1
2.2
Power Supply System Circuit Configuration
Figure 2-1 shows the circuit configuration of the power supply including the differences
between MSM64P155 and MSM64155A.
(Mask ROM)
(OTP version)
MSM64155A
1.5V option
MSM64P155
1.5V option
4
4
Condenser is
unnecessary.
VSSL
VPP
VDD3
VDD2
VDD1
VSS
98
98
99
100
23
VSS3
VSS2
VSS1
VDD
99
1.5V
1.5V
100
23
(a) Configuration of the power supply system with the 1.5V option
(Mask ROM)
(OTP version)
MSM64155A
3.0V option
MSM64P155
3.0V option
4
4
Condenser is
unnecessary.
VSSL
VPP
VDD3
VDD2
VDD1
VSS
98
98
99
100
23
VSS3
VSS2
VSS1
VDD
3.0V
3.0V
99
120
23
(b) Configuration of the power supply system with the 3.0V option
Figure 2-1 Power Supply System Circuit Configuration
2-2
2.3
Logic Power Supply and Backup Circuits
MSM64P155hasnobuilt-inlogicpowersupplyconstantvoltage(VR)orbackupcircuits.
Internal logic is driven by the VDD1 level both for the 1.5V option and 3.0V option. The
backup controller register (BUPCON) is identical to MSM64155A, it enables both
readingandwriting, andthe0bit(BUPF)ofthebackupcontrollerregister(BUPCON)has
no influence on the logic power source.
2.3.1 Configuration of the Logic Power Supply
Figure 2-2 shows the configuration of driving circuits of the logic power supply.
MSM64P155 (1.5V option)
VDD1
VDDL
1.5V
Logic circuit
VSS
Ca
VSS
MSM64P155L (3.0V option)
VDD2
VDD1
Bias generating circuit (+1.5V)
VDDL
3.0V
Ca
Logic circuit
VSS
Cb
VSS
Figure 2-2 Logic Power Supply Driving Circuits
2-3
2.3.2 Operations of Optional 1.5V Logic Power Supply Circuits
1.5V optional logic power supply circuits are supplied as a power source with ordinary
logic circuits for IC power supply voltage VDD1.
2.3.3 Operations of Optional 3.0V Logic Power Supply Circuits
With the 3.0V option, IC power supply voltage VDD2 is supplied to the logic circuit in the
system reset mode, and 1/2 descending power output voltage is supplied for other
modes.
Figure 2-3 shows the logic supply status for the system reset mode.
RESET0
(internal reset signal)
Crystal oscillation output
32.768 kHz
0.5sec
3.0V
VDD2
VDD1
Logic power source
VSS
VDD2
1.5V
Figure 2-3 Logic Power Supply Status for System Reset Mode (3.0V Option)
2-4
Chapter 3
CRYSTAL OSCILLATION
CIRCUIT
CHAPTER 3 CRYSTAL OSCILLATION CIRCUIT
3.1
Overview
The Crystal oscillation circuit, oscillating at 32.768 kHz, can be fine-adjusted with an
external capacitor, but since the phase of the power supply of MSM64P155 is reversed
against MSM64155A, location of the attachment position of an external capacitor CG
is placed between the VSS and OSC0 pin.
If RC oscillation is selected by mask option, use an external 1MW resistor like the
MSM64155A.
3.2
Configuration of Crystal Oscillation Circuit
Figure3-1showstheconfigurationsoftheCrystaloscillationcircuitbothforMSM64155A
(mask ROM) and MSM64P155.
MSM64155A (Mask ROM)
VDD
32.768 kHz
Crystal oscillation circuit
CG
OSC0
Time base clock
(32.768 kHz)
32.768 kHz
crystal
VDD
VSSL
Rf
CD
OSC1
(a) Configuration of Crystal Oscillation Circuit for MSM64155A
MSM64P155 (OTP version)
Logic power source
CG
OSC0
VSS
Time base clock
(32.768 kHz)
32.768 kHz
crystal
Rf
OSC1
CD
VSS
(b) Configuration of Crystal Oscillation Circuit for MSM64P155
Figure 3-1 Configurations of Crystal Oscillation Circuit
3-1
Chapter 4
PROM
CHAPTER 4 PROM
4.1
Overview
MSM64P155 uses built-in PROM as program memory. The capacity of this PROM is
4064bytesthatomitted32bytesfromthe0FE0Haddresstothe0FFFHaddress,forming
the test data area of the mask ROM.
In order to write the program data to this PROM, MSM64P155 uses a special adapter
(OTP 64155F-100) which is connected to a general EPROM writer for writing. See the
adapter manual for further reference.
4.2
Explanation of Pins
Table 4-1 shows PROM-related pins of MSM64P155.
Table 4-1 (a) PROM Related Pins
Pin
Name
Pin
No.
Input/
Output
Note
VSS
VDD1
VDD2
VPP
23
100
99
4
—
—
0V power supply
Plus side power supply pin (+5V supplied)
Plus side power supply pin (+5V supplied)
Power supply for PROM writing (+12.5V supplied)
PROM mode setting pins
—
—
RESET
TST1
TST2
1
Input
Input
Input
PROM mode is activated when the "H" level is input to these pins.
30
29
4-1
Table 4-1 (b) PROM-Related Pins
Pin
Name
Pin
No.
Input/
Output
Function
Program data write and read pins
SEG0/D0
SEG1/D1
SEG2/D2
SEG3/D3
SEG4/D4
SEG5/D5
SEG6/D6
SEG7/D7
SEG8/CE
SEG9/OE
SEG10/A0
SEG11/A1
SEG12/A2
SEG13/A3
SEG14/A4
SEG15/A5
SEG16/A6
SEG17/A7
SEG18/A8
SEG19/A9
SEG20/A10
SEG21/A11
SEG22
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
PROM chip enable pin
PROM output enable signal
Program address input pins
Normally input "H" level
4-2
4.3
PROM Mode
MSM64P155 has two different modes; PROM mode used to write to PROM and read
from PROM and microcontroller operation mode used to execute programs written to
PROM.WhenMSM64P155issetinthePROMmode,itsimplyoperatesasPROM.These
operations are explained under PROM mode.
4.3.1 Setting the PROM Mode
Setting of the PROM mode is done with RESET, TST1, and TST2, listed in Table 4-2.
When the PROM mode is set, LCD pins become PROM-related pins.
Table 4-2 PROM Mode Setting
RESET
TST1
TST2
MODE
H
H
H
PROM Mode
4.3.2 PROM Mode Functions
PROM Mode functions are shown in Table 4-3.
Table 4-3 PROM Mode Functions
VDD1
VDD2
MODE
CE
OE
VPP
D7~D0
Program data output
Read
L
L
L
H
L
5V
5V
5V
5V
Program
12.5V
12.5V
Program data input
Program data output
Program Verify
H
4-3
4.3.3 Connection to the EPROM Writer
Use the MSM64P155 dedicated adaptor (OTP64155F-100) when writing the program
data with a commercial general-purpose EPROM writer.
Set a ROM type for the EPROM writer to the 27C256 type Intel fast-writing mode
(V =12.5V, Program pulse width=1ms).
PP
Set the write addresses of 0000H to 0FDFH.
4-4
Chapter 5
TST3 PIN
CHAPTER 5 TST3 PIN
5.1
Overview
In the MSM64P155, when the TST pin is set to "H" level, the 256Hz and 4Hz interrupt
sources are added.
The two added interrupt sources enable the MSM64P155 to be used as an OTP version
of the MSM64152A, MSM64153A or MSM64158A.
Table 5-1 lists the interrupt sources when TST3="H" and Figure 5-1 shows the interrupt
control equivalent circuit.
Table 5-1 Interrupt sources (TST3="H")
No.
Interrupt source
Melody 0 interrupt
Symbol
MD0INT
MD1INT
P3INT
Interrupt start address
1
2
023H
026H
029H
02CH
02FH
032H
038H
03BH
03EH
041H
044H
047H
Melody 1 interrupt
Port 3 external interrupt
Port 2 external interrupt
Port 6 external interrupt
Port 7 external interrupt
256Hz interrupt
3
4
P2INT
5
P6INT
6
P7INT
7
256HzINT
128HzINT
32HzINT
16HzINT
4HzINT
1HzINT
8
128Hz interrupt
9
32Hz interrupt
10
11
12
16Hz interrupt
4Hz interrupt
1Hz interrupt
If two or more different interrupts occur at the same time, an interrupt with a smaller
interrupt start address number is serviced first.
When the TST3 pin is open or set to "L" level, the contents of interrupt sources are the
same as those of the MSM64155A.
5-1
Interrupt
request
signals
Interrupt
request
registers
Interrupt
enable
registers
IRQ0
IRQ0.1
IE0
IE0.1
MD0INT
MD1INT
P3INT
QMD0
QMD1
QP3
EMD0
EMD1
EP3
IRQ0.2
IRQ0.3
IE0.2
IE0.3
IRQ1
IE1
IRQ1.0
IRQ1.1
IRQ1.2
IE1.0
IE1.1
IE1.2
P2INT
P6INT
P7INT
QP2
QP6
QP7
EP2
EP6
EP7
Interrupt
Vector
Address
IRQ2
IE2
Interrupt
Request
IRQ2.0
IRQ2.1
IRQ2.2
IRQ2.3
IE2.0
IE2.1
IE2.2
IE2.3
256HzINT
128HzINT
32HzINT
16HzINT
Q256Hz
Q128Hz
Q32Hz
Q16Hz
E256Hz
E128Hz
E32Hz
E16Hz
IRQ3
IE3
IRQ3.0
IE3.0
IE3.1
4HzINT
1HzINT
TST3
Q4Hz
Q1Hz
E4Hz
E1Hz
IRQ3.1
MI
Figure 5-1 Interrupt Control Equivalent Circuit
5-2
5.2
Registers To Be Changed By TST3
When the TST3 pin is set to "H" level, the 256Hz interrupt and 4Hz interrupt are added
to the interrupt request registers (IRQ2, IRQ3) and interrupt enable registers (IE2, IE3),
respectively.
b
b
2
b
1
b
0
3
IRQ2 (3EH)
(R/W)
Q16Hz
Q32Hz
Q128Hz Q256Hz
16 Hz Interrupt Request Flag
0: Not requested (initial value)
1: Requested
32 Hz Interrupt Request Flag
0: Not requested (initial value)
1: Requested
128 Hz Interrupt Request Flag
0: Not requested (initial value)
1: Requested
256 Hz Interrupt Request Flag
0: Not requested (initial value)
1: Requested
Bit 3: Q16Hz
Set to "1" at the falling edge of a 16Hz output from the time base counter.
Bit 2: Q32Hz
Set to "1" at the falling edge of a 32Hz output from the time base counter.
Bit 1: Q128Hz
Set to "1" at the falling edge of a 128Hz output from the time base counter.
Bit 0: Q256Hz
Set to "1" at the falling edge of a 256Hz output from the time base counter.
5-3
b
3
b
2
b
1
b
0
IRQ3 (3FH)
(R/W)
—*
—*
Q1Hz
Q4Hz
1 Hz Interrupt Request Flag
0: Not requested (initial value)
1: Requested
4 Hz Interrupt Request Flag
0: Not requested (initial value)
1: Requested
*Researved bit: Fixed to "1". Write is disabled.
Bit 1: Q1Hz
Set to "1" at the falling edge of a 1Hz output from the time base counter.
Bit 0: Q4Hz
Set to "1" at the falling edge of a 4Hz output from the time base counter.
b
3
b
2
b
1
b
0
IE2 (3AH)
(R/W)
E16Hz
E32Hz
E128Hz E256Hz
16 Hz Interrupt Enable Flag
0: Disabled (initial value)
1: Enabled
32 Hz Interrupt Enable Flag
0: Disabled (initial value)
1: Enabled
128 Hz Interrupt Enable Flag
0: Disabled (initial value)
1: Enabled
256 Hz Interrupt Enable Flag
0: Disabled (initial value)
1: Enabled
5-4
b
3
b
2
b
1
b
0
IE3 (3BH)
(R/W)
—*
—*
E1Hz
E4Hz
1 Hz Interrupt Enable Flag
0: Disabled (initial value)
1: Enabled
4 Hz Interrupt Enabled Flag
0: Disabled (initial value)
1: Enabled
*Researved bit: Fixed to "1". Write is disabled.
Table 5-2 lists the registers to be changed by TST3
Table 5-2 TST3-Related Registers
Initial value after
system reset
Name
Symbol
Address Read/Write Byte access
TST3="0"
or OPEN
TST3="1"
0H
Interrupt Enable Register 2
Interrupt Enable Register 3
Interrupt Request Register 2
Interrupt Request Register 3
IE2
IE3
3AH
3BH
3EH
3FH
R/W
R/W
R/W
R/W
1H
0DH
1H
Yes
Yes
0CH
IRQ2
IRQ3
0H
0DH
0CH
5-5
APPENDIXES
APPENDIX A PACKAGE DIMENSIONAL DRAWING
MSM64P155-NGS-BK
MSM64P155L-NGS-BK
MSM64P155-XXXGS-BK
MSM64P155L-XXXGS-BK
Figure A-1 100-Pin QFP
Appendix-1
APPENDIX B ELECTRICAL CHARACTERISTICS
(1) For 1.5V Specifications in the microcontroller operation mode
Product Name: MSM64P155
•
Absolute Maximum Rating
(VSS=0V)
Parameter
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
Input voltage 1
Symbol
VDD1
Condition
Ta=25°C
Rating
–0.3~+2.0
Unit
V
VDD2
Ta=25°C
–0.3~+4.0
V
VDD3
Ta=25°C
–0.3~+5.5
V
VIN1
VDD1 system input, Ta=25°C
VDD1 system output, Ta=25°C
VDD2 system output, Ta=25°C
VDD3 system output, Ta=25°C
—
–0.3~VDD1+0.3
–0.3~VDD1+0.3
–0.3~VDD2+0.3
–0.3~VDD3+0.3
–55~+125
V
Output voltage 1
VOUT1
VOUT2
VOUT3
TSTG
V
Output voltage 2
V
Output voltage 3
V
Storage temperature
°C
•
Recommended Operating Conditions
(VSS=0V)
Parameter
Symbol
TOPE
Condition
Range
0~65
Unit
°C
Operating temperature
Operating voltage
Crystal oscillator
—
—
VDD1
1.35~1.7
V
fXT
—
—
30~35
kHz
frequency
RC OSC external resistance
ROS
1M±10%
W
Appendix-2
•
DC Characteristics
(Unless otherwise specified, VSS=0V, VDD1=1.5V, Ta=0~65˚C).
(1/5)
Measure-
Min. Typ. Max. Unit
ment
Parameter
Symbol
Condition
circuit
VDD2 voltage
VDD2
VDD3
Ca, C12=1µF Cb=0.1µF
Ca, C12=1µF Cb=0.1µF
Within 5 seconds from the
2.8 3.0 3.2
4.3 4.5 4.7
V
V
VDD3 voltage
XTOSC oscillation
beginning voltage
XTOSC oscillation
maintaining voltage
XTOSC external
capacity
VSTA
VHOLD
CG
1.45
1.35
10
—
—
—
—
—
30
20
V
V
beginning of oscillations after reset
—
—
1
pF
pF
XTOSC internal
capacity
CD
—
10
15
15
40
CROSC oscillation frequency
fCR
ROS=1MW
75 kHz
Note: "XTOSC" indicates crystal oscillation circuits at 32.768 kHz.
"CROSC" indicates RC oscillation circuits at 32 kHz.
Appendix-3
•
DC Characteristics (32.768 kHz Crystal Oscillation)
(Unless otherwise specified, VSS=0V, VDD1=1.5V, Ta=0~65˚C).
(2/5)
Measure-
Parameter
Symbol
Condition
Typ. Max. Unit
Min.
ment
circuit
Consumption current 1
Consumption current 2
IDD1
IDD2
CPU is in the HALT mode
—
—
2
10 µA
1
µA
CPU is in the operating mode
75 100
•
DC Characteristics (RC Oscillation)
(Unless otherwise specified, VSS=0V, VDD1=1.5V, Ta=0~65˚C).
(3/5)
Measure-
Typ. Max. Unit
Min.
ment
Parameter
Symbol
Condition
circuit
Consumption current 1
Consumption current 2
IDD1
IDD2
CPU is in the HALT mode
—
—
3
20 µA
1
µA
CPU is in the operating mode
100 200
Appendix-4
•
DC Characteristics
(Unless otherwise specified, VSS=0V, VDD1=1.5V, VDD2=3.0V, VDD3=4.5V, Ta=0~65˚C).
(4/5)
Measure-
ment
Parameter
Symbol
IOH1
Condition
VOH1=VDD1-0.5V
VOL1=+0.5V
Min. Typ. Max. Unit
–2.0 –0.6 –0.1 mA
0.1 0.6 2.0 mA
circuit
Output current 1
(P4.0~P4.3)
(MD0, MD0)
(MD1, MD1)
IOL1
IOH2
VOH2=VDD3-0.2V (VDD3 level)
VOMH2=VDD2+0.2V (VDD2 level)
—
4
—
—
—
—
—
—
–4 µA
µA
–4 µA
µA
–4 µA
µA
IOMH2
—
Output current 2
(SEG0~SEG59)
(COM1~COM4)
IOMH2S VOMH2S=VDD2-0.2V(VDD2 level)
—
4
2
IOML2
IOML2S
IOL2
VOML2=VDD1+0.2V (VDD1 level)
VOML2S=VDD1-0.2V(VDD1 level)
—
—
4
VOL2=+0.2V
(VSS level)
—
Output current 3
(P6.0~P6.3)
IOH3
VOH3=VDD1–0.5V
VOL3=+0.5V
VOH=VDD1
VOL=VSS
–5.0 –2.1 –0.3 mA
0.1 0.7 2.0 mA
IOL3
(P7.0~P7.3)
Output leak
(P6.0~P6.3)
(P7.0~P7.3)
IOOH
IOOL
—
—
—
0.3 µA
µA
–0.3
—
Appendix-5
•
DC Characteristics
(Unless otherwise specified, VSS=0V, VDD1=1.5V, VDD2=3.0V, VDD3=4.5V, Ta=0~65˚C)
(5/5)
Measure-
Parameter
Symbol
IIH1
Condition
Min. Typ. Max. Unit
ment
circuit
VIH=VDD1 (for pull-down)
1
0
20 100 µA
Input current 1
(P2.0~P2.3)
(P3.0~P3.1)
(P6.0~P6.3)
(P7.0~P7.3)
IIH1Z
IIL1
VIH1=VDD1 (for high impedance)
—
—
1
0
µA
µA
3
VIL1=VSS
–1
Input current 2
(TST1, TST2)
Input current 3
(TST3)
IIH2
IIL2
IIH3
IIL3
IIH4
IIL4
VIH2=VDD1
VIL3=VSS
VIH3=VDD1
VIL2=VSS
VIH4=VDD1
VIL4=VSS
50 200 800 µA
–1
0.3
–1
2
—
1
0
5
µA
µA
µA
µA
µA
—
8
0
Input current 4
(RESET)
30
0
–1
—
Input voltage 1
(P2.0~P2.3)
(P3.0~P3.1)
(P6.0~P6.3)
(P7.0~P7.3)
(TST1, TST2, TST3)
(RESET)
VIH1
VIL1
—
—
1.2
0
—
—
1.5
0.3
V
V
4
Appendix-6
Measurement Circuit 1 (1)
OSC1
Crystal
C12
OSC0
C1
CG
VSS
C2
VSS VDD1 VDD2
VDD3
Cb
Ca, C12
Cb
Crystal
CG
: 1 mF
: 0.1 mF
: 32.768 kHz
: 15 pF
Ca
A
V
V
Measurement Circuit 1 (2)
OSC1
ROS
C12
OSC0
C1
C2
VSS VDD1 VDD2
VDD3
Cb
Ca
: 20 mF
Cb, C12
ROS
: 0.1 mF ~ 0.2 mF
: 1MW
Ca
A
V
V
Appendix-7
Measurement Circuit 2
(Note 2)
A
Input pins
Output pin
VIH
(Note 1)
VIL
VSS VDD1 VDD2 VDD3
Measurement Circuit 3
(Note 3)
Output pin
A
Input pins
VSS VDD1 VDD2 VDD3
Appendix-8
Measurement Circuit 4
Waveform
monitoring
Input pins
Output pin
VIH
(Note 3)
VIL
VSS VDD1 VDD2 VDD3
Note 1 Input logic for specified mode
Note 2 Repeated on specified output pin
Note 3 Repeated on specified input pin
Appendix-9
(2) For 3.0V Specifications
Product Name: MSM64P155L
•
Absolute Maximum Ratings
(VSS=0V)
Parameter
Symbol
VDD1
Condition
Ta=25°C
Rating
–0.3~+2.0
Unit
V
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
Input voltage 1
VDD2
Ta=25°C
–0.3~+4.0
V
VDD3
Ta=25°C
–0.3~+5.5
V
VIN1
VDD2 system input, Ta=25°C
VDD2 system output, Ta=25°C
VDD3 system output, Ta=25°C
—
–0.3~VDD2+0.3
–0.3~VDD2+0.3
–0.3~VDD3+0.3
–55~+125
V
Output voltage 1
VOUT1
VOUT2
TSTG
V
Output voltage 2
V
Storage temperature
°C
•
Recommended Operating Conditions
(VSS=0V)
Parameter
Symbol
Condition
Range
Unit
°C
Operating temperature
Operating voltage
Crystal oscillator
—
—
TOPE
VDD2
0~65
V
2.7~3.5
—
—
30~66
fXT
kHz
frequency
RC OSC external resistance
ROS
W
1M±10%
Appendix-10
•
DC Characteristics
(Unless otherwise specified, VSS=0V, VDD2=3.0V, Ta=0~65˚C).
(1/5)
Measure-
ment
Parameter
Symbol
Condition
Min. Typ. Max. Unit
circuit
VDD1 voltage
VDD1
VDD3
Ca=1µF Cb, C12=0.1µF
Ca=1µF Cb, C12=0.1µF
Within 5 seconds from the
1.3 1.5 1.7
4.3 4.5 4.7
V
V
VDD3 voltage
XTOSC oscillation
beginning voltage
XTOSC oscillation
maintaining voltage
XTOSC external
capacitance
VSTA
VHOLD
CG
2.7
2.7
10
—
—
—
—
—
30
V
V
beginning of oscillations after reset
—
—
1
pF
pF
XTOSC internal
CD
—
10
15
15 20
capacitance
CROSC oscilaltion frequency
fCR
ROS=1MW
40 75 kHz
Note: "XTOSC" indicates crystal oscillation circuits at 32.768 kHz.
"CROSC" indicates RC oscillation circuits at 32 kHz.
Appendix-11
•
DC Characteristics (32.768 kHz Crystal Oscillation)
(Unless otherwise specified, VSS=0V, VDD2=3.0V, Ta=0~65˚C).
(2/5)
Measure-
ment
Parameter
Symbol
Condition
Unit
Min. Typ. Max.
circuit
Consumption current 1
Consumption current 2
IDD1
IDD2
CPU is in the HALT mode
—
—
1
5
µA
µA
1
CPU is in the operating mode
35 50
•
DC Characteristics (RC Oscillation)
(Unless otherwise specified, VSS=0V, VDD2=3.0V, Ta=0~65˚C).
(3/5)
Measure-
ment
Parameter
Symbol
Condition
Unit
Min. Typ. Max.
circuit
Consumption current 1
Consumption current 2
IDD1
IDD2
CPU is in the HALT mode
—
—
3
15 µA
1
µA
CPU is in the operating mode
50 100
Appendix-12
•
DC Characteristics
(Unless otherwise specified, VSS=0V, VDD1=1.5V, VDD2=3.0V, VDD3=4.5V, Ta=0~65˚C).
(4/5)
Measure-
Parameter
Symbol
IOH1
Condition
VOH1=VDD2–0.5V
VOL1=+0.5V
Min. Typ. Max. Unit
ment
circuit
Output current 1
(P4.0~P4.3)
(MD0, MD0)
(MD1, MD1)
–6 –1.8 –0.7 mA
IOL1
0.7 1.8
6
mA
IOH2
IOMH2
IOMH2S
IOML2
VOH2=VDD3–0.2V (VDD3 level)
VOMH2=VDD2+0.2V (VDD2 level)
VOMH2S=VDD2–0.2V(VDD2 level)
—
4
—
—
—
–4 µA
µA
–4 µA
µA
–4 µA
µA
—
Output current 2
(SEG0~SEG59)
(COM1~COM4)
—
2
VOML2=VDD1+0.2V (VDD1 level)
—
—
—
—
4
—
IOML2S VOML2S=VDD1–0.2V(VDD1 level)
IOL2
IOH3
VOL2=+0.2V
(VSS level)
4
—
Output current 3
(P6.0~P6.3)
VOH3=VDD2–0.5V
–1.8 –6 –2 mA
0.7 1.6 6.0 mA
IOL3
VOL3=+0.5V
VOH=VDD2
(P7.0~P7.3)
Output leak
(P6.0~P6.3)
(P7.0~P7.3)
IOOH
—
—
—
0.3 µA
µA
IOOL
VOL=VSS
–0.3
—
Appendix-13
•
DC Characteristics
(Unless otherwise specified, VSS=0V, VDD1=1.5V, VDD2=3.0V, VDD3=4.5V, Ta=0~65˚C).
(5/5)
Measure-
Min. Typ. Max.
Parameter
Symbol
Condition
Unit
ment
circuit
IIH1
VIH1=VDD2 (for pull-down) 50 100 300 µA
Input current 1
(P2.0~P2.3), (P3.0~P3.1)
(P6.0~P6.3), (P7.0~P7.3)
Input current 2
(TST1, TST2)
IIH1Z
VIH1=VDD2 (for high impedance)
0
—
—
1
µA
IIL1
IIH2
IIL2
IIH3
IIL3
IIH4
IIL4
VIL1=VSS
VIH2=VDD2
VIL2=VSS
VIH3=VDD2
VIL3=VSS
VIH4=VDD2
VIL4=VSS
–1
0
6
µA
mA
µA
µA
µA
0.4 1.5
–1
0.5
–1
20
–1
—
3
0
3
Input current 3
(TST3)
10
0
—
Input current 4
(RESET)
80 300 µA
—
0
µA
Input voltage 1
(P2.0~P2.3)
(P3.0~P3.1)
(P6.0~P6.3)
(P7.0~P7.3)
(TST1, TST2, TST3)
(RESET)
VIH1
VIL1
—
—
2.4
0
—
3.0
V
4
—
0.6
V
Appendix-14
Measurement Circuit 1 (1)
OSC1
Crystal
C12
OSC0
C1
CG
VSS
C2
VSS VDD2 VDD1
VDD3
Cb
Ca
: 1 mF
Cb, C12
Crystal
CG
: 0.1 mF
: 32.768 kHz
: 15 pF
Ca
A
V
V
Measurement Circuit 1 (2)
OSC1
ROS
C12
OSC0
C1
C2
VSS VDD2 VDD1
VDD3
Cb
Ca
Cb, C12
ROS
: 20 mF
: 0.1 mF
: 1MW
Ca
A
V
V
Appendix-15
Measurement Circuit 2
(Note 2)
A
Input pins
Output pin
VIH
(Note 1)
VIL
VSS VDD1 VDD2 VDD3
Measurement Circuit 3
(Note 3)
Output pin
A
Input pins
VSS VDD1 VDD2 VDD3
Appendix-16
Measurement Circuit 4
Waveform
monitoring
Input pins
Output pin
VIH
(Note 3)
VIL
VSS VDD1 VDD2 VDD3
Note 1 Input logic for specified mode
Note 2 Repeated on specified output pin
Note 3 Repeated on specified input pin
Appendix-17
(3) PROM Operations (Common Specifications for 1.5V and 3.0V)
Absolute Maximum Ratings
•
(VSS=0V)
Unit
V
Parameter
PROM power source
voltage
Symbol
Condition
VCC=VDD1=VDD2
Ta=25°C
Rating
VCC
–0.3~+6.7
Program voltage
PROM input voltage
VPP
VI
Ta=25°C
–0.3~+14.0
V
V
VCC system input
Ta=25°C
–0.3~VCC+0.3
PROM output voltage
Storage temperature
VO
VCC system output
Ta=25°C
–0.3~VCC+0.3
–55~+125
V
TSTG
—
°C
•
Recommended Operating Conditions
(VSS=0V)
Parameter
Symbol
Condition
Range
Unit
Operating temperature
VCC power supply
voltage
TOPEP
—
0~65
°C
VCC
VPP
VCC=VDD1=VDD2
4.75~5.25
V
VPP power supply
voltage
In read
4.75~5.25
V
In write
VCC=VDD1=VDD2
—
12.0~13.0
4~VCC
0~1
V
V
V
VIH
VIL
Input voltage
Appendix-18
<Read Operation>
•
DC Characteristics
(Unless otherwise specified, VDD1=VDD2=5V±5%, Ta=25˚C±5˚C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
VCC=VDD1=VDD2
CE=VIH
VCC supply voltage (Standby)
VCC supply voltage (Operation)
Input voltage
ICC1
—
—
35
mA
VCC=VDD1=VDD2
CE=VIL
VCC=VDD1=VDD2
—
ICC2
—
—
100
mA
VIH
VIL
4
0
—
—
VCC
1
V
V
VCC=VDD1=VDD2
VOH=VCC-0.5V
VOL=0.5V
IOH
IOL
–2
–0.7
0.7
–0.2
2
mA
mA
Output current
0.2
•
AC Characteristics
(Unless otherwise specified, VCC=5V±5%, VPP=VCC, Ta=0˚C~70˚C)
Parameter
Symbol
tACC
tCE
Condition
OE=CE=VIL
Min. Typ. Max. Unit
Address access time
CE access time
—
—
—
0
—
—
—
—
120
120
50
ns
ns
ns
ns
OE=VIL
CE=VIL
CE=VIL
OE access time
tOE
Output disable time
tDF
40
Measurement Conditions:
Input pulse level .................... 0.45V~4.55V
During rising/falling input....... 5 ns
Threshold level ...................... input 0.8V, 2V/output 0.8V, 2V
Appendix-19
•
Timing Diagram
Address input
CE
tCE
OE
tDF
tOE
tACC
Data output
Appendix-20
<Write Operation>
•
DC Characteristics
(Unlessotherwisespecified,VSS=0V,VDD1=VDD2=5V±5%,VPP=12.5V±0.5V,Ta=25˚C±5˚C)
Parameter
Symbol
IPP
Condition
Min.
—
—
4
Typ.
—
Max.
50
Unit
mA
mA
V
VPP power supply voltage
VCC power supply current
CE=VIL
100
VCC
1
ICC
VCC=VDD1=VDD2
VCC=VDD1–VDD2
—
—
VIH
—
Input voltage
VIL
0
—
V
VCC=VDD1=VDD2
VOH=VCC-0.5V
VOL=0.5V
–0.2
2
IOH
IOL
–2
–0.7
0.7
mA
mA
Output current
0.2
•
AC Characteristics
(Unlessotherwisespecified,VSS=0V,VDD1=VDD2=5V±5%,VPP=12.5V±0.5V,Ta=25˚C±5˚C)
Parameter
Symbol
tAS
Condition
Min. Typ. Max. Unit
Address setup time
OE setup time
Data setup time
—
2
2
2
0
2
0
2
—
—
—
—
—
—
—
—
—
µs
µs
µs
µs
µs
ns
µs
tOES
tDS
—
—
—
Address hold time
tAH
—
—
—
Data hold time
tDH
—
OE output floating delay time
VPP power source setup time
Initial program pulse width
tDFP
tVS
—
130
—
—
tPW
VDD1=VDD2
6V±0.25V
VDD1=VDD2
6V±0.25V
—
0.95 1.0 1.05 ms
Additional program pulse width
tOPW
tOE
2.85
—
—
—
78.75 ms
150 ns
OE output effective delay time
Measurement Conditions:
Input pulse level .................... 0.45V~4.55V
During rising/falling input....... less than 20 ns
Threshold level ...................... input 0.8V, 2V/output 0.8V, 2V
Appendix-21
•
Program Timing Diagram
Address input
Address N
tAH
tAS
Data input/output
VPP
Data Input
Data Output
tDFP
tDH
tOE
tDS
tVS
CE
OE
tOES
tPW
tOPW
Appendix-22
MSM64P155
User's Manual
First Edition:
March 1996
© 1996 Oki Electric Industry Co., Ltd.
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