MSM6636JS_技术文档

FEUL6636B-05

1

MSM6636/6636B

User’s Manual

SAE-J1850 Communication Protocol Conformed

Transmission Controller for

Automotive LAN

Oki Electric Industry Co., Ltd.

5th EDITION

ISSUE DATE: August 2001

NOTICE

1. The information contained herein can change without notice owing to product and/or technical improvements.

Before using the product, please make sure that the information being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an explanation for

the standard action and performance of the product. When planning to use the product, please ensure that the

external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the specified

operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting

from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or

electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or

operation outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us

in connection with the use of the product and/or the information and drawings contained herein. No responsibility is

assumed by us for any infringement of a third party’s right which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial

applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics,

etc.). These products are not authorized for use in any system or application that requires special or enhanced quality

and reliability characteristics nor in any system or application where the failure of such system or application may

result in the loss or damage of property, or death or injury to humans.

Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace

equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular countries.

The purchaser assumes the responsibility of determining the legality of export of these products and will take

appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

MSM6636/6636B User’s Manual

Contents

1. OVERVIEW

1-1

1.1 Overview..................................................................................................................................................... 1-1

1.2 Features....................................................................................................................................................... 1-1

1.3 Pin Configuration........................................................................................................................................ 1-2

1.4 Pin Description ........................................................................................................................................... 1-3

1.5 Block Diagram............................................................................................................................................ 1-4

2. COMMUNICATION FORMATS

2-1

2.1 Frame Format.............................................................................................................................................. 2-1

2.2 PWM Bit Format ........................................................................................................................................ 2-4

3. INTERNAL REGISTER DETAILS

3-1

3.1 Transmit Register........................................................................................................................................ 3-1

3.2 Response Register....................................................................................................................................... 3-2

3.3 Transmit Status Register............................................................................................................................. 3-2

3.4 Receive Register ......................................................................................................................................... 3-3

3.5 Receive Data Length Register..................................................................................................................... 3-5

3.6 Initialization/Read Completion Indication Register.................................................................................... 3-5

3.7 Interrupt Request Flag................................................................................................................................. 3-5

3.8 Interrupt Enable Flag (IE)........................................................................................................................... 3-7

3.9 Sleep Command Register............................................................................................................................ 3-7

3.10 Break Command Register........................................................................................................................... 3-8

3.11 Mode Setting Register................................................................................................................................. 3-9

3.12 Physical Address Register......................................................................................................................... 3-10

3.13 Functional Address Register..................................................................................................................... 3-10

3.14 NAK Register ........................................................................................................................................... 3-11

4. CPU INTERFACES

4-1

4.1 MSM6636................................................................................................................................................... 4-1

4.1.1 Clock Synchronous Serial Interface...................................................................................................... 4-2

4.1.2 UART Interface (Start-Stop Synchronization System) ......................................................................... 4-5

4.2 MSM6636B ................................................................................................................................................ 4-8

4.2.1 Parallel Interface ................................................................................................................................... 4-8

5. FUNCTION DETAILS

5-1

5.1 Arbitration Function ................................................................................................................................... 5-1

5.2 Address Filter Function............................................................................................................................... 5-1

5.3 Automatic Retransmission Function........................................................................................................... 5-2

5.4 CPU Interrupt Function............................................................................................................................... 5-3

5.5 Receive Message Length Error Detection Function ................................................................................... 5-3

5.6 Local-Station Bus Driver Abnormal Detection Function............................................................................ 5-3

5.7 Communication Check Function between Specific Nodes ........................................................................ 5-3

5.8 Communication Check Function between Multiple Nodes ........................................................................ 5-4

5.9 Break Function............................................................................................................................................ 5-4

5.10 Fault Tolerant Function............................................................................................................................... 5-5

Contents – 1

MSM6636/6636B User’s Manual

Contents

6. APPLICATION EXAMPLE

6-1

6.1 Host CPU and J1850 Line Connection Example ........................................................................................ 6-1

6.2 Initialization Routine Example .................................................................................................................. 6-3

7. ELECTRICAL CHARACTERISTICS

7-1

7.1 Absolute Maximum Ratings ....................................................................................................................... 7-1

7.2 Operation Range ......................................................................................................................................... 7-3

7.3 DC Characteristics ...................................................................................................................................... 7-3

7.4 AC Characteristics ..................................................................................................................................... 7-5

7.4.1 PWM Bit Timing................................................................................................................................... 7-5

7.4.2 CPU Interface Timing........................................................................................................................... 7-6

7.4.3 Wakeup Input Signal........................................................................................................................... 7-11

7.4.4 Fault Tolerant Function Operation Conditions.................................................................................... 7-12

7.4.5 Reset Input Pulse Width...................................................................................................................... 7-13

8. BUS MONITOR FUNCTION

8-1

9-1

9. PACKAGE OUTLINES AND DIMENSIONS

Contents – 2

Chapter 1

OVERVIEW

MSM6636/6636B User’s Manual

Overview

1. OVERVIEW

1.1 Overview

The MSM6636/6636B are transmission controllers for automotive LAN that conform to data communication

protocol SAE-J1850. These LSI devices can realize a data bus topology bus LAN system that employs the PWM

bit encoding method (41.6 kbps). In addition to a protocol control circuit, the MSM6636/6636B have an

oscillation circuit, host CPU interface*, a transmit/receive buffer, and a bus receiver circuit, thereby decreasing the

load on the host CPU.

*

MSM6636: The host CPU is accessed through clock synchronous serial/UART.

MSM6636B: The host CPU is accessed through parallel interface.

1.2 Features

•

Conforms to SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued August 12,

1991)

•

CSMA/CD (carrier-sense multiple access with collision detection)

Internal transmit buffer (1 frame) and receive buffer (2 frames)

Bit encoding: PWM (pulse width modulation)

Transmission speed: 41.6 kbps

Multiaddress setting: 1 type of physical addressing and 15 types of functional addressing

Address filter function by multiaddressing (broadcasting possible)

Automatic retransmission when lost in contention or in the case of non-ACK

Supports 3 types of in-frame responses

1) Single-byte response from a single recipient

2) Multibyte response from a single recipient (with CRC code)

3) Single-byte response from multiple recipients (ID response as ACK)

Error detection by cyclic redundancy check (CRC)

Various communication error detections

Dual-wire bus abnormality detection by internal bus receiver and fault tolerant function

Host CPU interface

•

(1) MSM6636

Host CPU interface is accessed through serial interface with LSB first. Serial 4 modes supported:

① Clock synchronous serial (no parity)

1) Normal mode: 8-bit data

2) MPC mode:

8-bit data + MPC bit (address/data select bit: 1 indicates address. 0 indicates data)

① UART (parity yes/no selectable)

1) Normal mode: 1 start bit + 8-bit data + (parity) + 1 stop bit

2) MPC mode:

1 start bit + 8-bit data + MPC bit + (parity) + 1 stop bit

(2) MSM6636B

Host CPU interface is accessed through parallel interface.

•

Sleep function

Low power mode with oscillator stopped (I_DSMax < 50 µA)

SLEEP/WAKE-UP control from host CPU; WAKE-UP via LAN bus

Package:

(1) MSM6636

18-pin plastic DIP (DIP18-P-300-2.54)

18-pin plastic QFJ (QFJ18-P-R290-1.27)

(Product name: MSM6636RS)

(Product name: MSM6636JS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6636GS-K)

(2) MSM6636B

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6636BGS-K)

30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: MSM6636BGS-AK)

1 – 1

MSM6636/6636B User’s Manual

Overview

1.3 Pin Configuration

(1) MSM6636

18-Pin Plastic DIP

18-Pin Plastic QFJ

24-Pin Plastic SOP

AV_DD

BO–

BI–

BI+

BO+

NC

AGND

1

2

3

4

5

6

7

8

9

24 DV_DD

1

2

3

4

5

6

7

8

9

AV_DD

BO–

BI–

18 DV_DD

23 RES

22 INT

2

1 18

17

RES

21 TXD

20 RXD

19 NC

18 NC

16

INT

3

4

5

6

7

16

15

14

13

12

BI–

INT

15

BI+

TXD

BI+

TXD

14

BO+

AGND

U-C

RXD

BO+

AGND

U-C

RXD

NC

SCLK/PAE

17

16

SCLK

13

SCLK

/PAE

U-C 10

M-N 11

DGND12

15 A-D

12

A-D

14 OSC0

13 OSC1

11

M-N

OSC0

8

9 10 11

10

DGND

OSC1

NC: No Connection

(2) MSM6636B

24-Pin Plastic SOP

30-Pin Plastic SSOP

₂₄DV_DD

₂₃AD7

WR

1

2

₃₀DV_DD

₂₉AD7

₂₈NC

₂₇AD6

₂₆AD5

₂₅AD4

₂₄AD3

₂₃NC

WR

1

2

RD

ALE

INT

₂₂AD6

₂₁AD5

₂₀AD4

₁₉AD3

₁₈AD2

₁₇AD1

₁₆AD0

₁₅CS

3

NC

ALE

INT

RES

3

4

RES

AV_DD

BO–

BI–

5

6

7

AV_DD

NC

7

8

BI+

BO+

AGND ₁₁

DGND₁₂

9

BO–

BI–

BI+

BO+

NC

₂₂AD2

₂₁AD1

₂₀AD0

₁₉CS

9

10

11

12

13

₁₄OSC0

₁₃OSC1

₁₈NC

AGND ₁₄

DGND₁₅

₁₇OSC0

₁₆OSC1

NC: No Connection

Refer to Chapter 9 for package dimension information.

1 – 2

MSM6636/6636B User’s Manual

Overview

1.4 Pin Description

(1) MSM6636

Pin No

DIP/QFJ

Pin Name

I/O

Function

SOP

1

AV_DD

BO–

BI–

1

2

—

O

I

Analog power supply pin

LAN BUS output–

LAN BUS input–

2

3

BI+

4

I

LAN BUS input+

BO+

AGND

U-C

5

O

—

I

LAN BUS output+

Analog ground pin

6

9

7

10

11

12

13

14

UART (:0)/clock synchronous serial (:1) select pin

MPC mode (:0)/normal mode (:1) select pin

Digital ground pin

M-N

8

I

DGND

OSC1

OSC0

9

—

O

I

10

11

Crystal (or ceramic resonator) oscillation output

Crystal (or ceramic resonator) oscillation input

0: data communication

1: address communication

A-D

12

15

I

SCLK/PAE

RXD

13

14

15

16

17

18

16

20

21

22

23

24

I

Serial clock input/parity select pin

Serial data input pin

TXD

O

I

Serial data output pin

Interrupt output pin

INT

RES

Reset input pin

DV_DD

—

Digital power supply pin

(2) MSM6636B

Pin Name

Pin No

I/O

Function

SOP

1

SSOP

1

WR

RD

I

Data write enable input pin

Data read enable input pin

Address Latch enable input pin

Interrupt output pin

2

ALE

3

4

I

INT

RES

4

5

O

I

5

6

Reset input pin

AV_DD

BO–

BI–

6

7

—

O

I

Analog power supply pin

LAN BUS output–

7

9

8

10

11

12

14

15

16

LAN BUS input–

BI+

9

I

LAN BUS input+

BO+

AGND

DGND

OSC1

OSC0

CS

10

11

12

13

14

15

O

—

O

I

LAN BUS output+

Analog ground pin

Digital ground pin

Crystal (or ceramic resonator) oscillation output

Crystal (or ceramic resonator) oscillation input

Chip select input pin

17

19

I

20 to 22,

24 to 27, 29

AD0-7

DV_DD

16-23

24

I/O

—

Address input/data output pins

Digital power supply pin

30

1 – 3

MSM6636/6636B User’s Manual

Overview

1.5 Block Diagram

(1) MSM6636

LAN

Bus

Buffer Register

LAN Controller

Input

S-P

PWM

Degital

Filter

Bus

Receiver

Receive

Register

Receive

Buffer

Converter Decoder

Address Register

Status Register

CRC

Checker

Address

Filter

CPU

Receive Controller

Transmission Controller

Transmission Register

Response Register

CRC

LAN

Bus

Generator

Output

Crystal

P-S

Converter

PWM

Encoder

Clock

Generator

MSM6636

(2) MSM6636B

LAN

Bus

Buffer Register

LAN Controller

Input

S-P

PWM

Digital

Filter

Bus

Receiver

Receive

Register

Receive

Buffer

Converter Decoder

Address Register

Status Register

CRC

Checker

Address

Filter

CPU

Receive Controller

Transmission Controller

Transmission Register

Response Register

CRC

LAN

Bus

Generator

Output

Crystal

P-S

Converter

PWM

Encoder

Clock

Generator

MSM6636B

1 – 4

Chapter 2

COMMUNICATION FORMATS

MSM6636/6636B User’s Manual

Communication Formats

2. COMMUNICATION FORMATS

2.1 Frame Format

101 bits maximum

SOF (A)

(B)

(C)

(D)

CRC EOD

(E)

EOF IFS

3-byte header

Data

Response

SOF: Start Of Frame

CRC: Cyclic Redundancy Check

EOD: End Of Data

EOF: End Of Frame

IFS: Inter-Frame Separation

Number of Bytes

Contents

(A)

(B)

(C)

(D)

(E)

1

Priority and message type

Physical address or functional address of receiver node

Physical address of transmitter node

Data

1

(*)

In-frame response (IFR)

*

The total sum of byte count of (D) + (E) is 0 to 8.

(A) Bit Configuration of Priority and Message Type

MSB

LSB

0

7

6

5

4

3

2

1

H(P3) P2

P1

P0

K

Y

Z1

Z0

H:

0 = 3-byte header (MSM6636/6636B)

1 = 1-byte header (not applicable) (See Note below)

P2 to P0: Priority setting bits

Determines priority of message. The smaller the priority value, the higher the priority.

P2

P1

P0

Priority

0

1

High

1

0

1

Low

Note:

The 1-byte header mode is not selected even if “1” is set to “H” bit.

The 3-byte header mode is always selected.

In the MSM6636/6636B, the “H” bit is not used for selective control of the number of header bytes. However,

since “0” has priority over “1”, the priority control depends on the bit value in the “H” bit, that is, the “H” bit

can be used as “P3” priority setting bit.

2 – 1

MSM6636/6636B User’s Manual

Communication Formats

Y:

Address type setting bit

0 = Functional address is specified to address field (B) of receiver node.

1 = Physical address is specified to address field (B) of receiver node.

K, Z1, Z0: Sets response type

The response type is set by a combination of K, Z1 and Z0 bits.

Message type and response type are determined by the lower 4-bits of the header byte (A), including the Y bit.

Classification is shown below.

The MSM6636/6636B identify each message type and makes an automatic response.

ZZ

Addressing

IFR Type

Message Type

KY10

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Functional

Physical

2

1

2

3

1

3

0

3

0

Multiple IDs received from multiple responders

Broadcast ^*1

Multiple IDs received from multiple responders

Data received from selected responders

ID received from selected responders

Data received from selected responders

SAE reserve ^*2

Physical

Data received from selected responders

To multiple responders (command/status)

To multiple responders (request)

Functional

Physical

*1 Broadcast: The same data is transmitted to multiple responders selected by functional addressing. Only the

responder having an ID (physical address) with the highest priority can send an ID as IFR. (IFR is sent only

once, and other responder IFRs are stopped.)

*2 SAE Reserve: The MSM6636/6636B do not respond even if IFR is requested by this header, because the

response type is not defined.

2 – 2

MSM6636/6636B User’s Manual

Communication Formats

[IFR Type 0]

SOF

Header

DATA

CRC EOF

Frame format when an in-frame response is not requested.

[IFR Type 1]

SOF

Header

DATA

CRC EOD ID EOF

Responder sends ID as an in-frame response.

ID is 1 byte only. Therefore, the number of bytes for sending data is a maximum of 7 bytes.

[IFR Type 2]

SOF

Header

DATA

CRC EOD ID1

…

IDn EOF

Multiple responders send ID sequentially as in-frame responses.

IDs are sent in sequence from the responder with the highest priority ID.

[IFR Type 3]

SOF

Header

DATA

CRC EOD IFR DATA CRC EOF

One selected responder returns multi-byte data with CRC as IFR.

(B) Physical address or functional address of receive node

The Y bit at the 1st byte (A) of 3-byte header determines whether an address is physical or functional. The 2nd

type (B) indicates the target address.

(C) Physical address of transmit node

Indicates the physical address (ID) of transmit node.

(D) Data

0 to 8 bytes of arbitrary data to transmit is written. Data can be increased/decreased in byte units. The maximum

number of bytes is 8, including response.

(E) In-frame response (IFR)

Determined by the bit configuration of message type at the 1st byte (A) of header. See the classification table of

IFR types.

2 – 3

MSM6636/6636B User’s Manual

Communication Formats

2.2 PWM Bit Format

♦

Pulse Width Modulation at 41.6 kbps (Typ.)

TP1

TP2

Dominant

Passive

“1”

TP3

Dominant

Passive

“0”

TP4

Dominant

Passive

“SOF”

“EOD”

“EOF”

“IFS”

“BRK”

TP5

Dominant

Passive

TP1

Dominant

Passive

Dominant

Passive

TP1

TP1 = 24

s

µ

TP2 = 7 s

µ

TP6

TP3 = 15

TP4 = 31

TP5 = 48

TP6 = 39

s

µ

s

µ

s

µ

s

µ

Dominant

Passive

2 – 4

Chapter 3

INTERNAL REGISTER DETAILS

MSM6636/6636B User’s Manual

Internal Register Details

3. INTERNAL REGISTER DETAILS

Internal Address

00H-0AH

0BH-12H

13H-14H

15H-1FH

20H

R/W

W

R

Contents

Status at Reset

Undefined

00H

Transmit register

Response register

Transmit status register

Receive register

Receive data length register

Undefined

00H

R

21H

W

Initialization/read completion indication register

Interrupt request flag

Interrupt enable flag

Sleep command register

Break command register

Mode setting register

Physical address register

Functional address register

NAK register

—

00H

22H-24H

25H-27H

28H

29H

2AH

2BH

2CH-3AH

3BH

R/W

W

00H

R/W

Undefined

3.1 Transmit Register

MSB

LSB

0 0

H

P2

P1

P0

K

Y

Z1

Z0

... Communication Type

... Receive Address

♦

Write priority and type of the message.

MSB

LSB

0 1

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

♦

Write physical address or functional address of receive node.

MSB

D7

LSB

D0

0 3

0 A

D6

D5

D4

D3

D2

D1

Transmit Data

8 bytes

D7

D0

♦

Write arbitrary data for transmitting.

Address 02H is empty, which permits the write operation.

The maximum number of bytes of transmit data that can be set depends upon the IFR type.

3 – 1

MSM6636/6636B User’s Manual

Internal Register Details

3.2 Response Register

MSB

LSB

D0

0 B

D7

D6

D5

D4

D3

D2

D1

IFR type 3 Response Data

8 bytes

1 2

D7

D0

♦

Write arbitrary data for transmitting IFR.

(Only applicable for IFR type 3 transmission)

3.3 Transmit Status Register

MSB

LSB

1 3

DL3 DL2 DL1 DL0

... Data Length

—

♦

Write the total number of bytes of 3-byte header and data (excluding CRC).

Data written to this register becomes the transmit start command.

MSB

—

LSB

1 4

RL3 RL2 RL1 RL0

... Response Data Length

—

♦

Write the number of bytes of data that has been written to the response register used for IFR transmission.

Data written to this register becomes the response transmit standby command.

This standby state continues till the response request of IFR type 3 is received and is released after

transmitting the response.

3 – 2

MSM6636/6636B User’s Manual

Internal Register Details

3.4 Receive Register

Receive register configuration

BUS(+)

BUS(–)

Receive

Circuit

Receive Buffer

Receive Register

Internal Bus Line

Message normal receive (RCV)

Response normal receive (RSP)

Read request

One frame of messages is stored in the receive register and one frame of messages in the receive buffer. Transfer

from the receive buffer to the receive register is implemented at the message/response receive time. Transfer to the

receive register is not implemented if communication errors or overrun errors occur when receive operation is in

progress.

Note: If the bus monitor mode is set to prepare a monitor tool, a transfer to the receive register is performed even

when errors described above occur. (See Section 8, “Bus Monitor Function”).

3 – 3

MSM6636/6636B User’s Manual

Internal Register Details

[When receiving header part and data part]

MSB

LSB

Z0

1 5

H

P2

P1

P0

K

Y

Z1

... Communication Type

... Receive Address

♦

Stores priority and type of the receive message.

MSB

LSB

1 6

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

♦

Stores physical address or functional address of receive node.

MSB

LSB

1 7

TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0

... Transmit Address

♦

Stores physical address of transmit node.

MSB

D7

LSB

D0

1 8

1 F

D6

D5

D4

D3

D2

D1

Receive Data

8 bytes

D7

D0

[When receiving response part]

MSB

LSB

D0

1 5

D7

D6

D5

D4

D3

D2

D1

Response

8 bytes

1 C

D0

3 – 4

MSM6636/6636B User’s Manual

Internal Register Details

3.5 Receive Data Length Register

MSB

LSB

2 0

—

RL3 RL2 RL1 RL0

... Receive Data Length

—

♦

Shows the byte length of receive data stored to the receive buffer (excluding CRC).

“—” indicates bits that are not provided. They will always read “0”.

3.6 Initialization/Read Completion Indication Register

MSB

LSB

2 1

—

... Completion Command

♦

Shows the completion of initialization after reset by writing to register 21H.

Shows by writing to register 21H that CPU has read all receive data stored to the receive register. Data to be

written is not specified.

3.7 Interrupt Request Flag

MSB

LSB

IFS

2 2

LEN ABN D-P OVER CRC FORM INV

♦

Flags related to message abnormality etc.

MSB

LSB

2 3

BUSY NOACK NRSP

—

BRK RSP RCV TR

♦

Flags related to message transmit/receive status etc.

MSB

LSB

WAKRWAKD BPG BPV BNG BNV

2 4

PAR*

—

*

♦

In MSM6636B, this bit is “—”.

Flags related to LAN bus line etc.

“1” indicates that a corresponding interrupt occurred. Each bit is cleared by writing “0” to it. All bits are

automatically set to “0” at reset. For details of how to clear, see Section 5.4, “CPU Interrupt Function” (page

5-3).

The bits to which a flag is not allocated will always read “0”.

3 – 5

MSM6636/6636B User’s Manual

Internal Register Details

[INTERRUPT CAUSE DETAILS]

LEN

ABN

Exceeded 12 bytes maximum, frame length of receive message.

LAN bus was in dominant status for more than specified time (48 µsec at 41.6 kbps).

BI(+) and BI(–) both received a signal indicating passive status even though a signal indicating

dominant status was output from BO(+) and BO(–) to both lines of BUS(+) and BUS(–). (Local

bus drive abnormality or LAN bus abnormality detected.)

D-P

If one line is normal, the communication is made by the normal line and the interrupt in D-P flag

does not occur.

Received next message before host CPU completed receive message processing.

(Overrun error)

Error was detected during CRC check.

OVER

CRC

Received abnormal format message:

FORM

(1) Received “SOF” during message receive.

(2) Detected “EOD” or “EOF” at location other than byte boundary.

Received signal in undefined bit format.

Another node started transmission during IFS. Even when IFS flag is set, if the receive frame is

normal, receive operation is executed.

INV

IFS

BUSY

NOACK

Lost in contention for all specified number of retransmissions.

Received no response for all specified number of retransmissions.

Type 3 IFR request message was received, but return data was not in response register (not in

transmission standby status).

NRSP

BRK

RSP

RCV

Received break signal.

Received response normally.

Received message normally.

Message transmission ended normally.

TR

If a response is not sent normally even though a response request was sent, the interrupt in TR

flag does not occur.

PAR*

Receive data parity error was detected during UART communication with CPU.

MSM6636: Wake-up occurred during sleep due to change of RXD terminal state.

MSM6636B: Wake-up occurred during sleep due to change of CS terminal state.

Wake-up occurred during sleep due to change of LAN bus status from passive to dominant.

Short-circuiting to GND detected at LAN bus(+) side.**

WAKR

WAKD

BPG

BPV

Short-circuiting to V_DDdetected at LAN bus(+) side.**

BNG

BNV

Short-circuiting to GND detected at LAN bus(–) side.**

Short-circuiting to V_DDdetected at LAN bus(–) side.**

*

Only applies to the MSM6636.

** For details, see Section 5.10, “Fault Tolerant Functions.”

3 – 6

MSM6636/6636B User’s Manual

Internal Register Details

3.8 Interrupt Enable Flag (IE)

MSB

LSB

IFS

2 5

LEN ABN D-P OVER CRC FORM INV

♦

Flags related to message abnormality etc.

MSB

LSB

2 6

BUSY NOACK NRSP

—

BRK RSP RCV TR

♦

Flags related to message transmit/receive status etc.

MSB

LSB

WAKRWAKD BPG BPV BNG BNV

2 7

PAR*

—

*

♦

In MSM6636B, this bit is “—”.

Flags related to LAN bus line etc.

An IE enables interrupt for each cause when set to “1”.

All bits are automatically set to "0" at reset.

Write is possible even for the bits to which a flag is not allocated, but no interrupt will be generated.

3.9 Sleep Command Register

MSB

LSB

S0

2 8

S7

S6

S5

S4

S3

S2

S1

... Sleep Command

♦

The MSM6636/6636B enter sleep status by writing “AAH” to register 28H. However, if the

MSM6636/6636B are processing a transfer, they will enter sleep status after completing processing and after

detecting IDLE bus status. In sleep status, oscillation stops and the MSM6636/6636B will be in output

passive status. After entering sleep status, the value of register 28H is automatically set to “00H”.

The value is automatically set to “00H” at reset.

Sleep status has a low supply current mode that stops the oscillator circuit.

Do not make the device enter sleep status during message transmission.

♦

Wake-up conditions include:

1) LAN bus status changes from passive to dominant.

2) MSM6636: RXD terminal of CPU interface terminals changes.

MSM6636B: Falling edge of CS terminal

When detecting these conditions 1) and 2), the MSM6636/6636B enable oscillation circuit operation, and at

the same time notify WAKE-UP completion to the CPU by sending an INT output (in the case of WAKE-UP

interrupt enable). Even if an abnormality occurs at one LAN bus (V_DD, short-circuit to GND or OPEN), the

MSM6636/6636B detect the change to dominant and WAKE-UP occurs if the other bus is normal.

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MSM6636/6636B User’s Manual

Internal Register Details

Notes:

1. In the case of wake-up using ceramic oscillator, the CPU interface cannot be used unless the

specified oscillation stabilization time has elapsed. Start access to the MSM6636/6636B

considering the above time in an INT processing routine.

2. When an oscillator is used and the wake-up request has been received through LAN bus, the

interrupt flags except the WAKD interrupt flag may be set while the oscillation is unstable. Be sure

to ignore and clear all these flags after the oscillation has reached a stable point.

3.10 Break Command Register

MSB

LSB

B0

2 9

B7

B6

B5

B4

B3

B2

B1

... BRK Transmit Command

♦

BRK is transmitted by writing “55H” to register 29H. However, if the LAN bus is in communication, a BRK

transmission starts when the end of a PWM bit format is detected in the frame during communication.

A LAN bus can be set to idle status before the completing of a frame during communication by a BRK

transmission.

The value of register 29H is automatically set to “00H” after a BRK transmission and at reset.

For details, see Section 5.9, “Break Function” (page 5-4).

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MSM6636/6636B User’s Manual

Internal Register Details

3.11 Mode Setting Register

MSB

LSB

N0

2 A

D2

D1

D0

PB0 NB0 NAK N1

... Mode Setting Register

♦

Setting division ratio of source oscillation (D2 to D0)

The internal selectable frequency divider will realize J1850 specified transmission speed from various source

oscillation such as CPU clock out or other oscillator.

Set the division ratio according to the source oscillation for use by referring to the table below.

D2, D1 and D0 = 1, 1, 1 are used for bus monitor. For details, see Section 8, “Bus Monitor Function.”

Source Oscillation

4 MHz

Division Ratio

D2

0

D1

0

D0

0

1

1/4

1/5

5 MHz

8 MHz

1/8

0

1

0

10 MHz

12 MHz

16 MHz

2 MHz

1/10

1/12

1/16

1/2

0

1

0

1

0

1

0

♦

Selecting NAK return yes/no (NAK)

This bit selects whether NAK register contents should be sent as a response or not when the

MSM6636/6636B is not in response standby status and receives a response request in IFR type 3.

0: Do not return NAK register value

1: Return NAK register value

Setting automatic retransmission function (N1, N0)

(N1) Selecting the function of retransmission in the case of non-ACK

0: Retransmission twice

1: No retransmission

This is a function that automatically retransmits when a response is not returned even though an IFR request

was sent.

(N0) Selecting the function of retransmission in the case of being lost contention.

0: Retransmission twice

1: No retransmission

This is a function that automatically retransmits when lost in contention during simultaneous transmission.

3 – 9

MSM6636/6636B User’s Manual

Internal Register Details

♦

LAN BUS output disable (PB0, NB0)

When an abnormality occurs on LAN BUS, its output (external driving) can be disabled.

(PB0) 0: LAN BUS(+) output is enabled. However, when an abnormality is detected on LAN BUS(+), it is

automatically disabled and when it becomes bus idle status, it is automatically enabled.

1: LAN BUS(+) output is disabled regardless of the detection of LAN BUS(+) abnormality. It is

recommended that this setting be made after checking that interrupt request flags BPG and BPV are

set. With PB0 set to “1”, the interrupt request flag BPG is always set during message transmission.

(NB0)0: LAN BUS(–) output is enabled. However, when an abnormality is detected on LAN BUS(–), it is

automatically disabled and when it becomes bus idle status, it is automatically enabled.

1: LAN BUS(–) output is disabled regardless of the detection of LAN BUS(–) abnormality. It is

recommended that this setting be made after checking that interrupt request flags BNG and BNV are

set. With NB0 set to “1”, the interrupt request flag BNV is always set during message transmission.

3.12 Physical Address Register

MSB

LSB

2 B

PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

... Physical Address

♦

Set the physical address (ID) of each node.

3.13 Functional Address Register

MSB

LSB

2 C

FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0

Functional Address

15 bytes

3 A

FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0

♦

In the case of communication by functional addressing, 15 types of address values in the above register are

automatically filtered in sequence.

Even if 15 types are not used for functional addressing, all 15 bytes are filtered. Therefore set the functional

address value in all address areas from the host CPU during initial setting.

(For example, write the same functional address value in unnecessary address areas.)

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MSM6636/6636B User’s Manual

Internal Register Details

3.14 NAK Register

MSB

LSB

3 B

NA7 NA6 NA5 NA4 NA3 NA2 NA1 NA0

... NAK Register

♦

When data with CRC is returned as IFR in IFR type 3, and when data was not set at the response register

before response timing, that is, when data is not in transmission standby status because the write of response

data has not been completed, data of the NAK register is returned with CRC added.

If the NAK return function is used, set the 3rd bit “NAK” of the mode setting register to “1”.

3 – 11

Chapter 4

CPU INTERFACES

MSM6636/6636B User’s Manual

CPU Interfaces

4. CPU INTERFACES

4.1 MSM6636

Access to each internal register can be selected from 4 types of serial interfaces. Data length is fixed to 8 bits (LSB

first). Clock synchronous or UART can be selected and each has 2 types of modes: normal mode, to decide

whether it is address value receive or data value receive according to the A-D pin status, and MPC mode, to decide

address/data by MPC bit following 8 bit data. When UART mode is selected, even parity addition yes/no can be

selected by the SCLK/PAE pin.

Type selection is set by the U-C pin and the M-N pin, and is determined by the sampling result of the status of both

pins immediately after clearing RESET.

If a communication type change is required, be certain to perform RESET processing.

(1) Clock synchronous serial:

Normal mode

MPC mode

: 8-bit data

: 8-bit data + MPC bit

(1: address / 0: data select bit)

(2) UART (start-stop synchronization system)

Normal mode

MPC mode

: 1 start bit + 8-bit data + (parity) + 1 stop bit

: 1 start bit + 8-bit data + MPC bit + (parity) + 1 stop bit

Selection of CPU interface type

UART

L

Clock Synchronous Serial

MPC Mode Normal Mode

Type

Pin Process

U-C Pin

M-N Pin

MPC Mode

L

Normal Mode

H

L

H

4 – 1

MSM6636/6636B User’s Manual

CPU Interfaces

4.1.1 Clock Synchronous Serial Interface

♦

Normal Mode

[PIN CONNECTION]

CPU

MSM6636

SCLK/PAE

A-D

SCLK

Pxx

SOUT

SIN

RXD

TXD

V_DD

U-C

M-N

INT

A-D pin input selects whether serial bus data is address or data information.

(For control purposes, connect CPU general purpose port (Pxx) output to A-D pin.)

Supply serial clock for both transmit and receive to CPU.

(CPU: master / MSM6636: slave communication)

[WRITE PROCEDURE]

Send the address of the write target register and communication type first, then send the write data. Since

address values are automatically incremented, it may be quicker to write to the registers that have consecutive

addresses.

1. Set “1” to the A-D pin to send the write destination address and the communication type.

2.

Synchronize 8 bits of the register write code, M1, M0 = “0, 1”, and the write destination address values

“A5 to A0”, to SCLK with LSB first, then send it to RXD input.

3. The data input to RXD is sampled at the rising edge of SCLK.

4. Set “0” to the A-D pin to send write data.

5. Synchronize 8 bits of write data to the SCLK clock with LSB first, then send it to RXD input.

6. Auto increment of the write destination address values occurs after each data write. (This makes

continuous data writing quicker, by eliminating some address selections.)

4 – 2

MSM6636/6636B User’s Manual

CPU Interfaces

[READ PROCEDURE]

Send the address of the read target register and the communication type first, then receive the read data. Since

address values are automatically incremented, it is speedy to read data of the registers that have consecutive

addresses.

1. Set “1” to the A-D pin to send the read destination address and the communication type.

2. Synchronize 8 bits of the register read code, M1, M0 = “1, 0”, and the read destination address values “A5

to A0” to SCLK with LSB first, then send it to RXD input.

3. Data input to RXD is sampled at the rising edge of SCLK.

4. 8 bits of read data is sent from TXD output, synchronizing to SCLK with LSB first. Sample the read data

at the rise of SCLK at the CPU side. (In MSM6636, data transmit and receive are simultaneous, so in the

case of continuous read, set the RXD pin to “H” or “ L”.)

5. Automatic increment of read destination address values operate every time one data reading ends. (This

makes continuous data reading possible.)

[COMMUNICATION TYPE AND COMMUNICATION ADDRESS]

7

6

5

4

3

2

1

0

M1

M0

A5

A4

A3

A2

A1

A0

High-order 2 bits (communication type)

01: WR Register

Low-order 6 bits (communication address)

Write destination address

10: RD Register

Read destination address

SCLK

RXD

(3)

D2

(3)

D3

D0

(2)

D1

(2)

D4

D5

D6

D7

(2)

D0

D1

D2

D3

TXD

A-D

(1)

Notes: (1) In the MSM6636, data is actually sampled at the A-D pin at the rise of the final SCLK of 1 frame to

determine whether data is address information or data itself. Set up the A-D pin before the final SCLK

input.

(2) In the MSM6636, “D0” is output to the TXD pin when setting transmit data to the transmit register is

completed. “D1” and later data are output synchronizing to the rise of SCLK. For details, see Section 7.4,

“AC Characteristics”.

(3) In the MSM6636, RXD data is sampled at the rise of SCLK.

4 – 3

MSM6636/6636B User’s Manual

CPU Interfaces

♦

MPC Mode

[PIN CONNECTION]

CPU

MSM6636

SCLK/PAE

SCLK

SOUT

SIN

RXD

TXD

V_DD

U-C

A-D

M-N

INT

In MPC mode, an MPC bit is added after the MSB bit (D7) of serial data, indicating that this 8 bit data is address

information if MPC = “1”, and that it is data itself if MPC = “0”. Therefore, unlike normal mode, A-D pin

control is unnecessary. (Connect the A-D pin to V_DDor GND.)

Except for adding an MPC bit to the serial data, everything, including timing, is the same as in the normal

mode.

SCLK

D0

D1

D2

D3

D4

D5

D6

D7

MPC

RXD

TXD

MPC: 1 = address

0 = data

4 – 4

MSM6636/6636B User’s Manual

CPU Interfaces

4.1.2 UART Interface (Start-Stop Synchronization System)

Normal Mode

♦

[PIN CONNECTION]

CPU

MSM6636

SCLK/PAE

V_DD

Parity Select

Pxx

A-D

U-C

SOUT

SIN

RXD

TXD

V_DD

M-N

INT

A-D pin input selects whether serial bus data is address or data information. (For control purposes, connect the

A-D pin to the general purpose port (Pxx) output, etc. of the CPU.) In UART, transmit/receive is controlled by

a shift clock with a 1/64 source oscillation frequency. If UART is used, set the baud rate at the CPU side.

[Example] If the source oscillation is 4 MHz, the transmission speed is 4 MHz/64 = 62.5 kbps.

SCLK/PAE pin = “H” selects parity yes, “L” selects parity no. This is determined by the pin status immediately

after RESET. When changing a setting, be certain to reset, since setting cannot be changed during

communication. (Parity is even parity.)

[WRITE PROCEDURE]

Send the address of the write target register and the communication type first, then send the write data. Since

address values are automatically incremented, it may be quicker to write data to registers that have consecutive

addresses.

An example of a parity yes condition follows.

1. Set “1” to the A-D pin to send the write destination address and the communication type.

2. Send start bit “0” and 8 bits of register write code M1, M0 = “0, 1”, and write destination address values

“A5 to A0” to RXD input with LSB first. When sending, add even parity (when parity yes is selected) and

stop bit “1” after the MSB bit.

3. After detecting the edge of start bit “0”, the MSM6636 generates a shift clock synchronizing data and

samples data in the sequence of input to RXD.

4. Set “0” to the A-D pin to send write data.

5. Send the start bit, 8 bits of write data (LSB first), the parity bit and the stop bit to RXD input in this order.

6. Auto increment of write destination address values occurs after each data write. (This makes continuous

data writing quicker by eliminating some address selections.)

4 – 5

MSM6636/6636B User’s Manual

CPU Interfaces

[READ PROCEDURE]

Send the address of the read target register and the read communication type set value “10”. The MSM6636

automatically sends the specified read target data after a specified time.^*1The address auto-increment function

does not operate when reading in UART mode. When reading from the MSM6636, address setting is required

for each data item.

1. Set “1” to the A-D pin to send the read destination address and the communication type.

2. Send start bit “0” and 8 bits of register read code M1, M0 = “1, 0”, and read destination responder address

values “A5 to A0” to RXD input with LSB first. When sending, add even parity (when parity yes is

selected) and stop bit “1” after the MSB bit.

3. After detecting the edge of start bit “0”, the MSM6636 generates a shift clock synchronizing data and

samples data in the sequence of input to RXD.

4. Read target data is sent from TXD output in the sequence of start bit, 8 bits of read data (LSB first), parity

bit and stop bit, after a specified time.^*1Receive in UART at the CPU side with the same baud rate.

*1: The interval time from when the read request in UART came from the CPU to when data transmit starts

takes 56 clocks of source oscillation.

[COMMUNICATION TYPE AND COMMUNICATION ADDRESS]

7

6

5

4

3

2

1

0

M1

M0

A5

A4

A3

A2

A1

A0

High-order 2 bits (communication type)

01: WR Register

Low-order 6 bits (communication address)

Write destination address

10: RD Register

Read destination address

A-D

D0

D1

D2

D5

D6

D7

P

RXD

(TXD)

START

STOP

P: Even parity

4 – 6

MSM6636/6636B User’s Manual

CPU Interfaces

♦

MPC Mode

[PIN CONNECTION]

CPU

MSM6636

SCLK/PAE

V_DD

Parity Select

U-C

SOUT

RXD

TXD

SIN

A-D

M-N

INT

In MPC mode, an MPC bit is added between the MSB bit (D7) of serial data and the parity bit (P), indicating

that this 8 bit data is address information if MPC = “1”, and that it is data itself if MPC = “0”. Therefore, unlike

normal mode, A-D pin control is unnecessary. (Connect the A-D pin to GND.)

Except for an MPC bit that is added to serial data, everything, including timing, is the same as in normal mode.

In UART, transmit/receive is controlled by the shift clock with a 1/64 source oscillation frequency. If UART is

used, set the baud rate at the CPU side.

SCLK/PAE pin: “H” selects parity yes, “L” selects parity no.

D0

D1

D2

D5

D6

D7

MPC

P

RXD

(TXD)

START

STOP

P: Even parity

MPC: 1 = address

0 = data

Note:

If an abnormality occurs at the host CPU serial interface part (missing bit, synchronization shift, etc.),

reset the MSM6636 from the CPU to initialize the interface circuit, then start communication again.

Even if the MSM6636 is reset, an internal register like a physical address is not initialized, therefore

resetting is unnecessary. (See Status at Reset in “Internal Register Details” (page 3-1).)

Normal/abnormal of the host CPU interface part can be evaluated by sending an RD request for the

physical address value and checking whether the set physical address value can be correctly read.

4 – 7

MSM6636/6636B User’s Manual

CPU Interfaces

4.2 MSM6636B

The internal registers can be accessed through parallel interface. This facilitates interfacing with a microcontroller

that has an address multiplex type bus port.

4.2.1 Parallel Interface

The internal registers can be accessed through parallel interface by applying a “L” level to the CS pin. After a

“L” level is applied to the CS pin, be sure to make address settings before reading or writing data. Parallel

interface allows the internal registers to be accessed asynchronously with the internal clock.

While accessing through the parallel interface, avoid device operation where a “L” level is applied to the WR

and RD pins simultaneously or the case that both of them are at a “L” level at the same time.

Applying a “H” level to the CS pin disables access though parallel interface. In this case, pins WR, RD, ALE,

and AD0 to AD7 will be set to high impedance input.

[PIN CONNECTION]

Host CPU

AD0-AD7

MSM6636B

AD0-AD7

8

ALE

RD

ALE

RD

WR

Pxx

INT

CS

RES

INT

J1850 Bus

4 – 8

MSM6636/6636B User’s Manual

CPU Interfaces

[WRITE PROCEDURE 1]

1. Apply a “L” level to the CS pin to enable parallel interface.

2. Apply a “H” level to the ALE pin.

3. Set address values to the AD0 to AD7 pins.

4. Apply a “L” level to the ALE pin. (Set up the addresses at the fall of ALE.)

5. Apply a “L” level to the WR pin.

6. Input date to the AD0 to AD7 pins.

7. Apply a “H” level to the WR pin to write data. (Data writing ends at the rise of WR.)

8. Apply a “H” level to the CS pin to terminate the use of parallel interface.

CS

AD0-7

Address

Data

ALE

WR

Figure 4.1 Write Timing

[READ PROCEDURE 1]

1. Apply a “L” level to the CS pin to enable parallel interface.

2. Apply a “H” level to the ALE pin.

3. Set address values to the AD0 to AD7 pins.

4. Apply a “L” level to the ALE pin. (Set up the addresses at the fall of ALE.)

5. Apply a “L” level to the RD pin to read data. (Data reading starts at the fall of RD.)

6. Apply a “H” level to the RD pin to end reading. (Data reading ends at the rise of RD.)

7. Apply a “H” level to the CS pin to terminate the use of parallel interface.

CS

AD0-7

Address

Data

ALE

RD

Figure 4.2 Read Timing

4 – 9

MSM6636/6636B User’s Manual

CPU Interfaces

[WRITE PROCEDURE 2]

Once address values have been set, they will be automatically incremented after each data write.

It is therefore quicker to write to the registers consecutively.

1. Apply a “L” level to the CS pin to enable parallel interface.

2. Apply a “H” level to the ALE pin.

3. Set address values to the AD0 to AD7 pins.

4. Apply a “L” level to the ALE pin. (Set up the addresses at the fall of ALE.)

5. Apply a “L” level to the WR pin.

6. Input data though the AD0 to AD7 pins.

7. Apply a “H” level to the WR pin to write data. (Data writing ends at the rise of WR.)

8. To write data to the areas with consecutive addresses, repeat steps 5 to 7.

9. Apply a “H” level to the CS pin to terminate the use of parallel interface.

CS

AD0-7

Address

Data

ALE

WR

Repeat

Figure 4.3 Write Timing

[READ PROCEDURE 2]

Once address values have been set, they will be automatically incremented after each data write.

It is therefore quicker to write to the registers consecutively.

1. Apply a “L” level to the CS pin to enable parallel interface.

2. Apply a “H” level to the ALE pin.

3. Set address values to the AD0 to AD7 pins.

4. Apply a “L” level to the ALE pin. (Set up the addresses at the fall of ALE.)

5. Apply a “L” level to the RD pin to read data. (Data reading starts at the fall of RD.)

6. Apply a “H” level to the RD pin to end reading. (Data reading ends at the rise of RD.)

7. To read data from the areas with consecutive addresses, repeat steps 5 to 6.

8. Apply a “H” level to the CS pin to terminate the use of the parallel interface.

CS

AD0-7

Address

Data

ALE

RD

Repeat

Figure 4.4 Read Timing

4 – 10

Chapter 5

FUNCTION DETAILS

MSM6636/6636B User’s Manual

Function Details

5. FUNCTION DETAILS

5.1 Arbitration Function

Multiple nodes are connected to the LAN bus, so if multiple nodes start to transmit at the same time, the

MSM6636/6636B perform nondestructive collision detection, and control priority using the arbitration function.

Only the node transmitting a message that has the highest priority can complete a transmission. Priority is set so

that the node outputting in dominant status is higher than the node outputting in passive status. The

MSM6636/6636B constantly monitor the LAN bus status, even during transmission, comparing the output data of

local nodes and the LAN bus status. If a local node is in passive status output, but the dominant status is detected on

the LAN bus, the MSM6636/6636B judge this as a collision, and immediately stop output.

This is how bus arbitration is performed.

Arbitration Loss

Transmit Node A

Transmit Node B

Arbitration Loss

Transmit Node C

LAN Bus

Dominant status output

Node B gains priority.

SOF

0

1

0

5.2 Address Filter Function

The MSM6636/6636B have physical addresses that are unique to each node, and functional addresses that are set

for each functional block. Based on these address values, the address filter function automatically judges whether

data on the LAN bus becomes the receive target.

Set the physical address value to each node and set the functional address value for each functional block (15 types

can be set) from the host CPU side.

The MSM6636/6636B select either a physical address or functional address by the physical address/functional

address decision bit (Y) in a receive message, and execute collating with each address value of the internal register.

If the same address is detected, the MSM6636/6636B judge this as a message to their own node, and enter receive

operation. Otherwise the MSM6636/6636B do not receive the message in that frame.

SOF (A)

(B)

(C) DATA

… …

EOF

Selects address type by Y bit of 3-byte header (A)

0: functional address 1: physical address

Address Filter

Executes collating between listener address value of (B)

and address value set to internal register.

Physical Address

Functional Address

5 – 1

MSM6636/6636B User’s Manual

Function Details

< Physical Address >

< Functional Address >

8-bit × 1

8-bit × 15

Address Setting Register

2BH to 3AH

2BH

PID #01

2CH

↓

FID #01

↓

3AH

FID #15

Note: The values of functional address registers (2CH to 3AH) are undefined at reset. Filtering is executed to the

entire #1 to #15 area, therefore be certain to set address values to the entire area, even if not all the 15 types

are used. In this case, set the same functional address values or invalid address values to areas not used.

5.3 Automatic Retransmission Function

When a message cannot be transmitted because of being lost in contention (when BUSY flag is set) or

communication errors (when ABN, D-P, FORM, or INV flag is set), and when a response is not normally returned

even if an in-frame response request is sent (when OVER, CRC, INV, FORM, ABN, or LEN flag is set), automatic

retransmission is possible.

Automatic retransmission can be set for contention loss time and for non-ACK time independently by setting the

“N1, N0” bits of the mode setting register.

For example, if transmission was not possible when “retransmission twice” was selected, this means that the

transmit operations were repeated a total of 3 times. When “no retransmission” was selected, if transmission was

not possible in the first transmission attempt, it notifies the CPU that transmission was not possible.

2AH

D2

D1

D0

—

NAK N1

N0

When lost in contention

0

Retransmission twice

No retransmission

1

In the case of non-ACK in IFR

0

1

Retransmission twice

No retransmission

5 – 2

MSM6636/6636B User’s Manual

Function Details

5.4 CPU Interrupt Function

When transmit/receive is completed, or when various errors occur, an interrupt can be requested to the host CPU

by INT output (low active). Also interrupt enable/disable can be set for each interrupt cause.

The host CPU can clear an interrupt request (INT output = “H”) by writing “0” to the corresponding bit of an

interrupt request flag in an interrupt process routine.

However, the flag is not set by writing “1” in the interrupt request flag, but the previous state is held. Therefore,

other interrupts can be received during clearing operation by writing “0” to only the corresponding bits of the

causes to be cleared and “1” to other bits.

An interrupt request is cleared when all bits set to interrupt enable status are cleared. (See below.)

INT

Interrupt cause

A generated

Interrupt cause

A generated

Interrupt cause

A cleared

Interrupt cause

A cleared

Interrupt cause

B generated

Interrupt cause

B cleared

5.5 Receive Message Length Error Detection Function

When a message length exceeds 12 bytes, only the transmission and reception nodes of the message set an interrupt

request flag LEN. And then a reception message or reception response is not stored in reception register. The

message transmission or response transmission continues even if this flag is set.

5.6 Local-Station Bus Driver Abnormal Detection Function

If a passive status is received although a dominant status was output on LAN bus, an interrupt request flag D-P is

set and this function notifies that the local-station bus driver is abnormal. In addition, the message transmission or

response transmission is discontinued at once.

5.7 Communication Check Function between Specific Nodes

This function checks whether communication between specific nodes was normal or not by sending the response

type (K, Y, Z1, Z0) = (0, 1, 0, 0) (physical address & IFR type 1) messages.

The specific node that normally received the message of the abovementioned response type sends back the

physical address (ID) of the local-station as an in-frame response. The node that sent the message does not store

this returned response in a reception register, and an interrupt request flag TR is set only when the value of a sent

remote reception address was coincident with that of a received response. At this time, an interrupt request flag

RSP is not set. Therefore, whether the communication is normal or not can be judged by checking only the TR flag,

which helps reduce the software load. Also, the setting of a read completion command (address 21H ) is not

required, because the response received at this time is not stored in the reception register.

5 – 3

MSM6636/6636B User’s Manual

Function Details

5.8 Communication Check Function between Multiple Nodes

This function checks whether communication between multiple nodes with their respective functional addresses

was normally made or not by sending messages with response type (K, Y, Z1, Z0) = (0, 0, 0, 0) or (0, 0, 1, 0)

(physical address & IFR type 2). How it is done is described below.

The multiple responders that normally received the message of the abovementioned response type send back ID

sequentially as in-frame responses, in which case the IDs are sent back in sequence from the responder with the

highest priority ID.

The returned IDs are then stored in the reception register in sequence from address 15H of the register. When all

the IDs have been stored, the interrupt request flags TR and RSP are set. The length of the received data is stored

in the reception data length register (address 20H). Therefore, by reading the reception data of the received data

length from the reception register and checking the IDs returned, the user can check whether the communication

between multiple nodes was normally made.

5.9 Break Function

The break function forcibly sets all nodes connected to LAN line to “receive enable state.”

By this function, the break transmission node can quickly carry out the message transmission operation by a break

transmission even during a bus busy state.

The break transmission is executed by writing “55H” to the break command register (29H).

Data on bus

Node (A)

BRK

EOD EOF IFS

Transmission stop

SOF

Node (B)

Timing in Node (A) Break Transmission during Node (B) Transmission

The following shows how the MSM6636/6636B operate when a break signal is received.

State at Break Reception

Operation

•

Stops transmission operation (judges the contention loss generated

during communication).

•

The break interrupt flag is set.

Even though an auto-retransmission mode is set, the frame that

stopped the transmission by the break reception is canceled.

During transmission operation

Therefore, the retransmission operation is not carried out.

•

Retransmission standby is canceled. Therefore, the retransmission

During transmission standby such

as bus busy (in setting the auto-

retransmission mode)

operation is not carried out, after break.

•

The break interrupt flag is set.

Stops the reception operation.

The message on response during reception is not stored in a reception

During reception operation

During transmission standby

register.

•

The break interrupt flag is set.

5 – 4

MSM6636/6636B User’s Manual

Function Details

5.10 Fault Tolerant Function

The following shows a detection flow in the case that BUS(+) and BUS(–) are short-circuited to V_DDand GND.

BUS(–)’s short circuit to GND

BUS(+)

48 µs

BUS(–)

INT

BUS(–)’s short

circuit to GND

• Bus input is

switched to

INV, ABN,

Clear processing

of INV, ABN,

Clear processing

of BNG flag

and BNG flags

are set.

and BNG flags

• BNG flag is set.

• Bus input is left

switched to

BUS(–) returns to normal status.

• Bus input is switched to the

differential input of BUS(+)

and BUS(–).

• Bus input is

switched to

BUS(+) only.

BUS(–) only.

BUS(+) only.

At a bus idle status, when BUS(–) is short-circuited to GND, because a bus that changes its status is preferentially

recognized as a normal bus, it is first judged that BUS(+) is short-circuited to GND and only BUS(–) is switched as

the reception input. If the BUS(–) is short-circuited to GND for more than 48 µsec (in transmission speed 41.6

kbps setting), the dominant time error of the bus is detected and interrupt request flags ABN and INV are set. As

soon as these flags are set, it is rejudged that BUS(–) is short-circuited to GND, an interrupt request flag BNG is set,

and only BUS(+) input is switched as the reception input. Through the abovementioned flow, BUS(–)’s short

circuit to GND is detected and LAN bus input is switched so that normal communication can be carried out. Then,

three interrupt request flags (INV, ABN, and BNG) are set. When these flags are cleared, the operation after that is

just to set BNG flag. Next, when BUS(–) returns to the normal status, the inputs of both BUS(+) and BUS(–) are

switched as reception inputs and the reception status of a normal LAN bus is given as before. If BNG flag is then

cleared, all interrupt requests on LAN bus are cleared. When the disable setting bit (NB0) of LAN BUS output is

“0”, the LAN BUS(–) output is disabled when BNG flag is set and the LAN BUS(–) output is enabled when

BUS(–) returns to the normal status.

5 – 5

MSM6636/6636B User’s Manual

Function Details

BUS(–)’s short circuit to V_DD

BUS(+)

BUS(–)

INT

BNV flag is set.

Clear processing of BNV flag

BNV flag is set.

Bus input is switched to BUS(+) only.

BUS(–)’s short circuit to V_DD

At a bus idle status, when BUS(–) is short-circuited to V_DD, the abnormality of LAN bus is not detected until

messages are output on LAN bus (until the status of LAN bus is changed) because of no change at the status of

LAN bus. When the messages are output on LAN bus, the interrupt request flag BNV is set from judging that

BUS(–) is short-circuited after a fixed time. Then the BUS(+) input only is switched to the reception input. At the

bus idle status, if BNV flag is cleared, the abnormality of LAN bus is not detected until messages are again output

on LAN bus. When the disable setting bit (NB0) of the LAN BUS output is “0”, the output drive of the LAN

BUS(–) output is disabled when BNV flag is set. After a short circuit is detected, when a frame of communication

finishes, the status of LAN bus returns to the bus idle status and the BUS(–) output again returns to an output

enable status. Therefore, when the status of the short circuit continues, note that the transistors mounted externally

are driven during the top SOF signal dominant period per one communication frame. In addition, the

abovementioned automatic return function is not operated and the output drive can be completely stopped by

setting the disable setting bit (NB0) of the LAN bus output to “1”.

Note: When BUS(–) (passive state) is short-circuited, the overcurrent flows in the external bus drivers only

during the SOF dominant period.

5 – 6

MSM6636/6636B User’s Manual

Function Details

BUS(+)’s short circuit to GND

BUS(+)

BUS(–)

INT

BPG flag is set.

Bus input is switched to BUS(–) only.

BUS(+)’s short circuit to GND

Bus input is switched to BUS(–) only.

Clear processing of BPG flag

At bus idle status, when BUS(+) is short-circuited to GND, it is also detected and processed by the same way as the

case of the BUS(–)’s short circuit to V_DDas stated above.

BUS(+)’s short circuit to V_DD

48

s

µ

BUS(+)

BUS(–)

INT

BUS(+)’s short

circuit to V_DD

INV, ABN,

and BPV flags

are set.

Clear processing

of INV, BPV,

Clear processing

of BPV flag

Bus input is

and ABN flags

•

switched to

Bus input is

switched to

BUS(–) only.

BPV flag is set.

Bus input is

switched to

•

BUS(+) is normally

recovered.

BUS(+) only.

Bus input is switched to the

•

BUS(–) only.

differential input of BUS(+)

and BUS(–).

At the bus idle status, when BUS(+) is short-circuited to V_DD, the input of LAN bus is switched to communicate

normally by detecting the BUS(+)’s short circuit to V_DDthrough the same flow as the case of the BUS(–)’s short

circuit to GND as stated above.

When BUS(+) returns to the normal status, the inputs of both BUS(+) and BUS(–) are switched as reception inputs

and the reception status of a normal LAN bus is given as before. If BPV flag is then cleared, all interrupt requests

on LAN bus are cleared.

5 – 7

Chapter 6

APPLICATION EXAMPLE

MSM6636/6636B User’s Manual

Application Example

6. APPLICATION EXAMPLE

6.1 Host CPU and J1850 Line Connection Example

1) Example of connection of host CPU and J1850 line with the MSM6636 is shown below.

Unit A

Host CPU

MSM6636

DV_DDAV_DD

BO(+)

R_S

SOUT

RXD

TXD

INT

R_B

R_R

R_B

SIN

INT

CLKOUT

OSC0

BI(+)

(*1)

C

OPEN OSC1

SCLK/PAE

BI(–)

U-C

ZD

M-N

BO(–)

A-D

ZD

R_S

RES

RES DGND AGND

Unit B

R_P

R_D

Bus+

Bus–

The above connection example is when “UART, MPC and 'parity no' mode” is used as the host CPU interface, and

when “CLKOUT output of the host CPU” is used as the clock for the MSM6636.

An optimum system can be constructed by selecting an optimum host CPU (number of ports, A/D converter

yes/no) for the control target and combining it with the MSM6636.

*1 Insert a capacitor between the power supply and GND as a countermeasure for noise.

It is recommended that a small-capacitance bypass capacitor and a large-capacitance filter capacitor be

connected in parallel. Typical capacitors are as follows:

0.01 to 0.22 µF: Ceramic capacitor

10 to 100 µF:

Tantalum capacitor

6 – 1

MSM6636/6636B User’s Manual

Application Example

2) Example of connection of host CPU and LAN bus with the MSM6636B is shown below.

Unit A

Host CPU

MSM6636B

DV_DDAV_DD

R_S

AD0-7

ALE

RD

8

R_B

R_R

R_B

ALE

BO(+)

BI(+)

RD

WR

C

(*1)

Pxx

CS

INT

BI(–)

INT

CLKOUT

OSC0

ZD

BO(–)

OPEN

OSC1

ZD

R_S

DGND AGND

RES

Unit B

R_P

R_D

Bus+ Bus–

The adove connection example is when “parallel interface” is used as the host CPU intreface, and when

“CLKOUT output of the host CPU” is used as the clock for the MSM6636B.

An optimum system can be constructed by selecting an optimum host CPU (number of ports, A/D converter

yes/no) for the control target and combining it with the MSM6636B.

*1 Insert a capacitor between the power supply and GND as a countermeasure for noise.

It is recommended that a small-capacitance bypass capacitor and a large-capacitance filter capacitor be

connected in parallel. Typical capacitors are as follows:

0.01 to 0.22 µF: Ceramic capacitor

10 to 100 µF:

Tantalum capacitor

6 – 2

MSM6636/6636B User’s Manual

Application Example

6.2 Initialization Routine Example

POWER ON

Reset MSM6636/6636B

Set the RES pin to a low level to reset the device.

Set division ratio of source oscillation (D2 to D0).

Select NAK return yes/no (NAK).

Set automatic retransmission function (N1, N0).

Set mode.

Write to address 2AH.

This setting is kept until the device is powered down and is not reset

by the RES pin input.

Set a physical address (ID). Write an inherent address on the network.

This setting is not reset by the RES pin input.

Set physical address.

Write to address 2BH.

Set the function address register. Up to 15 types of address values can be used.

Even if 15 types are not used for functional addressing, all 15 bytes are filtered.

Therefore set the functional address value in all address areas from the host CPU

during initial setting.

Set functional address.

Write to addresses

2CH-3AH.

(For example, write the same functional address value in unnecessary address areas.)

Set interrupt

enable flag.

Write to addresses

25H-27H.

Set an interrupt enable flag. (See Section 3.8, Interrupt Enable Flag IE.)

At reset, all the flags are disabled for interrupt.

Set initialization

completion command.

Write to address

21H.

After reset, be sure to set an initialization command. The message reception

response reception are enabled by writing in address 21H.

The data to be written is not specified.

Initialization

completed

6 – 3

Chapter 7

ELECTRICAL CHARACTERISTICS

MSM6636/6636B User’s Manual

Electrical Characteristics

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

DGND = AGND = 0 V

Parameter

Power Supply Voltage

Input Voltage

Symbol

Condition

—

Rated Value

–0.3 to +7.0

–0.3 to DV_DD+ 0.3

850

Unit

V

DV_DD, AV_DD

V_I

AV_DD= DV_DD

Ta = 25°C

—

V

Output Voltage

V_O

V

*1

P_D(DIP)

mW

°C

*2

P_D(QFJ)

940

*3

Power Dissipation

P_D(SOP)

910

*4

P_D(SOP)

780

*5

P_D(SSOP)

970

Storage Temperature

T_STG

–55 to +150

*1 Indicates 18-pin DIP package power dissipation for MSM6636.

*2 Indicates 18-pin QFJ package power dissipation for MSM6636.

*3 Indicates 24-pin SOP package power dissipation for MSM6636.

*4 Indicates 24-pin SOP package power dissipation for MSM6636B.

*5 Indicates 30-pin SSOP package power dissipation for MSM6636B.

Power Dissipation Curve

18-pin DIP package for MSM6636

18-pin QFJ package for MSM6636

1000

940

1000

850

500

–40 25

125 150

–40 25

125 150

Ambient temperature Ta (°C)

24-pin SOP package for MSM6636

1000

910

500

–40 25

125 150

Ambient temperature Ta (°C)

7 – 1

MSM6636/6636B User’s Manual

Electrical Characteristics

30-pin SSOP package for MSM6636B

24-pin SOP package for MSM6636B

1000

970

1000

780

500

–40 25

125 150

–40 25

125 150

Ambient temperature Ta (°C)

7 – 2

MSM6636/6636B User’s Manual

Electrical Characteristics

7.2 Operation Range

DGND = AGND = 0 V

Parameter

Symbol

DV_DD, AV_DD

f_OSC

Condition

AV_DD= DV_DD

Rated Value

4.5 to 5.5

Unit

V

Power Supply Voltage

Operating Frequency

Operating Temperature

DV_DD= AV_DD= 5 V ±10%

—

2 to 16

MHz

°C

Ta

–40 to +125 *

*

–40 to +85°C for MSM6636B

7.3 DC Characteristics

1) MSM6636

DV_DD= AV_DD= 5 V ±10%, DGND = AGND = 0 V, Ta = –40 to +125°C

Parameter

Symbol

V_IH1

V_IL1

V_IH2

V_IL2

V_H

Condition

—

Application

Min.

Typ.

—

Max.

DV_DD+ 0.3

DV_DD× 0.2

DV_DD+ 1.0

DGND + 2.0

400

Unit

V

H Level Input Voltage

L Level Input Voltage

H Level Input Voltage

L Level Input Voltage

Receiver Hysteresis Width

H Level Input Current

L Level Input Current

H Level Input Current

L Level Input Current

H Level Input Current

L Level Input Current

H Level Output Voltage

L Level Output Voltage

H Level Output Voltage

L Level Output Voltage

GND Offset Voltage

Supply Current 1

A

DV_DD× 0.8

—

DGND – 0.3

V

—

F

DV_DD– 2.0

V

—

F

DGND – 1.0

V

—

F

100

mV

µA

V

I_IH1

V_I= V_DD

V_I= 0 V

V_I= V_DD

V_I= 0 V

V_I= V_DD

V_I= 0 V

B

—

+1

I_IL1

B

—

–1

I_IH2

C

—

+1

I_IL2

C

—

–100

I_IH3

BI(+)

BI(–)

D

—

+100

I_IL3

—

–100

V_OH1

V_OL1

V_OH2

V_OL2

V_OFF

I_DS

I_O= –400 µA

I_O= +3.2 mA

I_O= –4.0 mA

I_O= +4.0 mA

—

DV_DD– 0.4

—

D

—

DGND + 0.4

—

V

E

DV_DD– 0.4

V

E

—

DGND + 0.4

±1

V

—

V

During sleep

f = 16 MHz,

no load

50

µA

Supply Current 2

I_DD

—

10

mA

A: RES, SCLK/PAE, RXD, U-C, M-N, A-D, OSC0

B: SCLK/PAE, RXD, U-C, M-N, A-D

C: RES

D: TXD, INT

E: BO–, BO+

F: BI–, BI+

7 – 3

MSM6636/6636B User’s Manual

Electrical Characteristics

2) MSM6636B

DV_DD= AV_DD= 5 V ±10%, DGND = AGND = 0 V, Ta = –40 to +85°C

Parameter

Symbol

V_IH1

V_IL1

V_IH2

V_IL2

V_IH3

V_IL3

V_H

Condition

—

Application

Min.

Typ.

—

*1

Max.

DV_DD+ 0.3

DV_DD× 0.2

DV_DD+ 1.0

DGND × 0.3

DV_DD+ 0.3

+0.8

Unit

V

H Level Input Voltage

L Level Input Voltage

H Level Input Voltage

L Level Input Voltage

H Level Input Voltage

L Level Input Voltage

Receiver Hysteresis Width

H Level Input Current

L Level Input Current

H Level Input Current

L Level Input Current

H Level Input Current

L Level Input Current

H Level Output Voltage

L Level Output Voltage

H Level Output Voltage

L Level Output Voltage

GND Offset Voltage

Current Supply 1

A

DV_DD× 0.8

—

DGND – 0.3

V

—

E

DV_DD× 0.7

V

—

E

DGND – 1.0

V

—

B

2.4

V

—

B

–0.3

V

—

E

100

400

mV

µA

V

I_IH1

V_I= V_DD

V_I= 0 V

V_I= V_DD

V_I= 0 V

V_I= V_DD

V_I= 0 V

B

—

+1

I_IL1

B

—

–1

I_IH2

RES

BI(+)

BI(–)

—

+1

I_IL2

—

–100

I_IH3

—

+100

I_IL3

—

–100

V_OH1

V_OL1

V_OH2

V_OL2

V_OFF

I_DS

I_O= –400 µA C, AD0-7

I_O= +3.2 mA C, AD0-7

DV_DD– 0.4

—

DGND + 0.4

—

V

I_O= –4.0 mA

I_O= +4.0 mA

—

D

DV_DD– 0.4

V

—

DGND + 0.4

±1

V

—

V

During sleep

f = 16 MHz,

no load

50

µA

Current Supply 2

I_DD

—

*2

10

mA

A: RES, CS, OSC0

B: ALE, WR, RD, AD0-7

C: INT

D: BO–, BO+

E: BI–, BI+

*1 Typ. = 0.2 µA when V_DD= 5 V, f = 16 MHz, Ta = 25°C

*2 The variations in supply current at different frequencies at V_DD= 5 V, Ta = 25°C are shown below.

DYNAMIC SUPPLY CURRENT VS. FREQUENCY (Typ.)

4

Ta = 25°C

_DD= 5 V

3

2

1

0

V

0

2

4

6

8

10

12

14

16

18

f

[MHz]

7 – 4

MSM6636/6636B User’s Manual

Electrical Characteristics

7.4 AC Characteristics

7.4.1 PWM Bit Timing

DV_DD= AV_DD= 5 V ±10%, Ta = –40 to +125°C*, Set at 41.6 kbps

Transmit

Typ.

Receive

Min.

Parameter

Symbol

Unit

Min.

23.64

6.90

Max.

24.36

7.11

15.23

31.47

48.72

39.59

48.72

—

Max.

28.00

12.00

20.00

36.00

52.00

44.00

51.00

76.00

—

Bit Length

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

TP10

24.00

7.00

21.00

5.00

µs

“1” Dominant Width

“0” Dominant Width

“SOF” Dominant Width

“SOF, BRK” Length

“BRK” Dominant Width

“EOD” + Bit Length

“EOF” + Bit Length

“EOF + IFS” + Bit Length

“0” Passive Width

14.87

30.54

47.28

38.42

47.28

70.92

94.56

8.86

15.00

31.00

48.00

39.00

48.00

72.00

96.00

9.00

13.00

29.00

45.00

37.00

43.00

69.00

86.00

4.00

—

9.14

15.00

*

–40 to +85°C for the MSM6636B

The sending timing in the above table does not include the delay of the bus drivers.

Dominant

“1”

Passive

TP2

Dominant

“0”

Passive

TP3

TP1

TP10

Dominant

“SOF”

Passive

TP4

TP5

Dominant

“EOD”

Passive

LAST BIT

EOD

TP8

TP7

Dominant

Passive

“EOF”

“IFS”

EOF

TP9

IFS

Dominant

Passive

“BRK”

TP6

TP5

7 – 5

MSM6636/6636B User’s Manual

Electrical Characteristics

7.4.2 CPU Interface Timing

1) MSM6636

Serial Interface Timing between CPUs

Clock synchronous serial

•

DV_DD= AV_DD= 5 V ±10%, Ta = –40 to +125°C

Parameter

Symbol

tφ

Min.

62

Typ.

—

Max.

Unit

ns

OSC0 (source oscillation) Pulse Cycle

Period of SCLK Low

500

t_CKLW

t_CKHW

t_SRS

t_SRH

t_STD

8tφ

4tφ

0

—

Period of SCLK High

—

Setup Time, RXD High/Low to SCLK High

Hold Time, SCLK High to RXD High/Low

Output Delay Time, SCLK High to TXD High/Low

Setup Time, A-D High/Low to SCLK High

Hold Time, SCLK High to A-D High/Low

—

6tφ + 100

—

t_AS

—

t_AH

8tφ

—

Time Interval between SCLK Frames ^*1

Time Interval between SCLK Frames ^*2

t_INT1

t_INT2

8tφ

—

ns

16tφ

φ

t

OSC0

SCLK

t_CKLW

t_CKHW

t_SRSt_SRH

RXD

TXD

t_STD

t_ASt_AH

A-D

SCLK

t_{INT1, 2}

Final SCLK Rise of 1 Frame

*1 Between “Communication type (WR) and address setting” frame and “WR data” frame.

Between one “WR data” frame and the next “WR data” frame during continuous WR.

*2 Between “Communication type (RD) and address setting” frame and “RD data” frame.

Between one “RD data” frame and the next “RD data” frame during continuous RD.

7 – 6

MSM6636/6636B User’s Manual

Electrical Characteristics

•

UART

DV_DD= AV_DD= 5 V ±10%, Ta = –40 to +125°C

Parameter

Symbol

t_UAS

Min.

0

Typ.

—

Max.

Unit

ns

Setup Time, A-D High/Low to STOP bit High

Hold Time, STOP bit Low to A-D High/Low

Output Delay Time, START bit Low toTXD High

Time Interval between Write Frames ^*3

—

t_UAH

0

—

50tφ + 100

—

ns

t_UTD

48tφ

0

—

ns

t_INT3

—

ns

Time Interval between Read Frames ^*4

t_INT4

10tφ

—

ns

tφ

OSC0

t_UAS

t_UAH

A-D

STOP

RXD

TXD

START

t_UTD

t_INT3

t_INT4

START

STOP bit Termination

*3 Between “Communication type (WR) and address setting” frame and “WR data” frame.

Between one “WR data” frame and the next “WR data” frame during continuous WR.

*4 Between “Communication type (RD) and address setting” frame and “RD data” frame.

7 – 7

MSM6636/6636B User’s Manual

Electrical Characteristics

2) MSM6636B

Parallel Interface Timing between CPUs

DV_DD= AV_DD= 5 V ±10%, Ta = –40 to +85°C

Parameter

Symbol

t_AW

Condition

Min.

65

5

Max.

—

70

50

—

Unit

ALE Pulse Width

Address Setup Time

Address Hold Time

t_AS

t_AH

CS Setup Time

RD Setup Time

t_CSS

t_RDS

t_RDCY

t_RD

50

20

160

—

Continuous Read Cycle Time

RD Output Effective Delay Time

RD Output Floating Delay Time

RD Pulse Width

RD Hold Time during Read

WR Setup Time

t_RDH

t_RDW

t_RCSH

t_WRS

t_WRCY

t_WRW

t_DS

—

C_L= 50 pF

ns

75

0

100

160

75

100

40

50

Continuous Write Cycle Time

WR Pulse Width

Data Setup Time

Data Hold Time

t_DH

CS Hold Time during Write

t_WCSH

7 – 8

MSM6636/6636B User’s Manual

Electrical Characteristics

•

Parallel interface timing

t_AW

ALE

t_RDS

t_AS

t_AH

AD0-7

Address

Data Output

t_RDH

t_RD

CS

t_CSS

t_RDW

t_RCSH

RD

Read Timing

ALE

t_WRS

AD0-7

Address

Data Input

t_DS

t_DH

CS

t_WRW

t_WCSH

WR

Write Timing

7 – 9

MSM6636/6636B User’s Manual

Electrical Characteristics

•

Timing when address auto-increment function is used

ALE

t_RDS

AD0-7

Address

Data Output

CS

RD

t_RD

t_RDH

t_RDCY

t_RDW

Read Timing

ALE

t_WRS

AD0-7

Address

Data Input

t_DS

t_DH

CS

t_WRCY

t_WRW

WR

Write Timing

7 – 10

MSM6636/6636B User’s Manual

Electrical Characteristics

7.4.3 Wakeup Input Signal

DV_DD= AV_DD= 5 V ±10%, Ta = –40 to +125°C *

Parameter

Symbol

t_WD

Min.

7

Typ.

—

Max.

—

Unit

µs

LAN Bus Passive → Dominant Change Pulse Width

RXD Terminal Input Pulse Width (for MSM6636)

CS Terminal Input Pulse Width (for MSM6636B)

Bus Receiver Stable Time ^*5

t_WR

300

400

1

—

ns

t_WR

—

ns

t_RS

—

µs

*

–40 to +85°C for MSM6636B

t_WD

BI+

BI–

RXD

t_WR

CS

t_WR

Note: The above timing waveforms show the wakeup input signals from each sleep status.

*5

The stable time of the bus receiver is from just after wakeup to the restart of message transmission

and reception. However, the clock oscillation source should use an external clock. (A clock is

input even in the sleep status.)

7 – 11

MSM6636/6636B User’s Manual

Electrical Characteristics

7.4.4 Fault Tolerant Function Operation Conditions

DV_DD= AV_DD= 5 V ±10%, Ta = –40 to +125°C*, set at 41.6 kbps

Parameter

Symbol

t_PG

Min.

5

Typ.

—

Max.

—

Unit

µs

LAN Bus(+)-to-GND Short Circuit Detection Pulse Width

LAN Bus(+)-to-V_DDShort Circuit Detection Pulse Width

LAN Bus(–)-to-GND Short Circuit Detection Pulse Width

LAN Bus(–)-to-V_DDShort Circuit Detection Pulse Width

–40 to +85°C for MSM6636B

t_PV

48

5

—

µs

t_NG

—

µs

t_NV

—

µs

*

BUS(+)

BUS(–)

t_PG

t_PV

BUS(+)

BUS(–)

t_NV

t_NG

7 – 12

MSM6636/6636B User’s Manual

Electrical Characteristics

7.4.5 Reset Input Pulse Width

DV_DD= AV_DD= 5 V ±10%, Ta = –40 to +125°C*

Parameter

Symbol

t_RES

Min.

0.1

Typ.

—

Max.

—

Unit

µs

Reset Input Pulse Width

*

–40 to +85°C for MSM6636B

RES

t_RES

Note: Make certain that as much time as the oscillation stable time determined by the crystal or ceramic

resonator used and the parasitic capacitance generated by connection will be ensured as the t_REStime

above when power is turned on.

The reset input pulse width given in the table above denotes the minimum pulse width when oscillation

is stable in power-on state.

7 – 13

Chapter 8

BUS MONITOR FUNCTION

MSM6636/6636B User’s Manual

Bus Monitor Function

8. BUS MONITOR FUNCTION

In ordinal operation mode of MSM6636/6636B, the message filtering function is based on physical or functional

address. Therefore the MSM6636/6636B treat only the message that is addressed to it and handle the message as

a communication frame.

However, when the bus monitor mode is set as explained below, all the messages on LAN can be received.

Using the bus monitor mode, monitor equipment to analyze the messages on J1850 network can be easily

designed.

(1) Bus Monitor Setting Method

a) Set the frequency division select code “D2, D1, D0” bits of the Mode Setting Register (2AH) to “1, 1,

1” .

MSB

D2

LSB

N0

D1

D0

PB0 NB0 NAK N1

2A

Frequency division ratio setting (D2 to D0)

♦

b) MSM6636: Apply 4 pulses to M-N

MSM6636B: Apply 4 pulses to ALE pin (when “L” level is input to CS pin)

The following figure shows the bus monitor setting timing of the MSM6636B.

c) Resume the contents of “D2, D1, D0” to proper value that is depending on the applied oscillation

frequency.

MSM6636B bus monitor setting timing

(a)

(b)

(c)

CS

Data

Address

Data

Address

AD0-7

ALE

WR

Set the frequency division select

code to “1, 1, 1”.

Reset the frequency division select

code to the specified code.

8 – 1

MSM6636/6636B User’s Manual

Bus Monitor Function

(2) Bus Monitor Using Method

The received messages should be retrieved by the master CPU from the MSM6636/6636B using the CPU

interface.

When the program uses interrupts, please use the following registers.

IRQ and IE flags are mapped into the following registers.

IRQ (Interrupt Request Flag)

MSB

LSB

BUSY _NOACKNRSP B-MON BRK RSP RCV TR

23

Transmit/receive status of messages

♦

IE (Interrupt Enable Flag)

MSB

LSB

BUSY

NRSP B-MON BRK RSP RCV TR

26

NOACK

Transmit/receive status of messages

♦

Note: When the bus monitor is not used,

the B-MON interrupt request flag is fixed at “0”, and

the B-MON interrupt enable flag is merely a read/write enable flag.

(3) Notes for Using Bus Monitor

♦ Bus Monitor mode operates as usual node. Only the difference is that address filtering function is

disabled to receive all messages. Therefore if the message is addressed to the monitor node, the node

may make response to the message.

♦ To avoid making response as described above and make the node work as monitoring only, choose the

unused address and set the address to the Address Setting Register.

(4) Detailed Explanation for Bus Monitor

When the MSM6636/6636B enter the bus monitor mode, messages are sequentially stored in receive

registers, starting with the 3-byte header of a message that begins with SOF. The difference from the

normal receiving is that data is received together with CRC code. Messages are stored in receive registers

in the order of data, CRC, and response. Therefore, because a message is stored by one byte too much for

CRC code, the last byte is not stored in receive registers (15H to 1CH) if the message is equal to the

maximum frame length. However, the last byte is stored in the 3CH address in that case. Therefore, in

this case, read also the 3CH address, though the address is not used for the normal communication.

In addition, the bytes including CRC are stored in receive data length registers. Therefore, during the bus

monitor mode, check data referencing the above bytes, when reading the received data.

8 – 2

Chapter 9

PACKAGE OUTLINES AND

DIMENSIONS

MSM6636/6636B User’s Manual

Package Outlines and Dimensions

9. PACKAGE OUTLINES AND DIMENSIONS

(Unit: mm)

DIP18-P-300-2.54

Package material

Lead frame material

Epoxy resin

42 alloy

Pin treatment

Package weight (g)

Rev. No./Last Revised

Solder plating (≥5µm)

1.30 TYP.

2/Dec. 11, 1996

5

9 – 1

MSM6636/6636B User’s Manual

Package Outlines and Dimensions

(Unit: mm)

QFJ18-P-R290-1.27

Spherical surface

Package material

Lead frame material

Pin treatment

Package weight (g)

Rev. No./Last Revised

Epoxy resin

42 alloy

Solder plating (≥5µm)

0.50 TYP.

5

3/Nov. 11, 1996

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package

name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

9 – 2

MSM6636/6636B User’s Manual

Package Outlines and Dimensions

(Unit: mm)

SOP24-P-430-1.27-K

Mirror finish

Package material

Epoxy resin

Lead frame material

Pin treatment

Package weight (g)

Rev. No./Last Revised

42 alloy

Solder plating (≥5µm)

0.58 TYP.

5

5/Oct. 13, 1998

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package

name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

9 – 3

MSM6636/6636B User’s Manual

Package Outlines and Dimensions

(Unit: mm)

SSOP30-P-56-0.65-K

Mirror finish

Package material

Lead frame material

Pin treatment

Package weight (g)

Rev. No./Last Revised

Epoxy resin

42 alloy

Solder plating (≥5µm)

0.19 TYP.

5/Dec. 5, 1996

5

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package

name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

9 – 4

MSM6636/6636B

User’s Manual

First Edition:

June 1995

Second Edition: July 1998

Third Edition:

February 2000

Fourth Edition: May 2000

Fifth Edition:

2001 Oki Electric Industry Co., Ltd.

FEUL6636B-05

August 2001


型号：	MSM6636JS
厂家：	OKI ELECTRONIC COMPONETS
描述：	LAN Controller, 1 Channel(s), 0.005078125MBps, CMOS, PQCC18, 0.290 INCH, 1.27 MM PITCH, PLASTIC, QFJ-18 局域网
文件：	总72页 (文件大小：707K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSM6636JS [OKI]

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