MSM6665C-02 [OKI]
Dot Matrix LCD Driver, 16 X 80 Dots, CMOS, 6.09 X 4.97 MM, ALUMINIUM PAD, DIE-117;
| 型号： | MSM6665C-02 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Dot Matrix LCD Driver, 16 X 80 Dots, CMOS, 6.09 X 4.97 MM, ALUMINIUM PAD, DIE-117 时钟 驱动 CD 外围集成电路 |
| 文件： | 总32页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL6665C-04
Issue Date: Dec. 27, 2004
MSM6665C-xx
DOT MATRIX LCD CONTROLLER WITH 17-DOT COMMON DRIVER AND 80-DOT SEGMENT
DRIVER
GENERAL DESCRIPTION
The MSM6665C-xx is a dot-matrix LCD control driver which has functions of displaying
characters, cursor and arbitrators.
The MSM6665C-xx is provided with a 17-dot common driver, 80-dot segment driver, display
RAM and character ROM, and is controlled with the commands from the serial interface.
The character ROM can change the font data by mask option.
The MSM6665C-02 has standard ROM with 256 different character fonts.
TheMSM6665C-xxcandriveavarietyofLCDpanelsbecausethebiasvoltage, whichdetermines
the LCD driving voltage, can be optionally supplied from the external source.
FEATURES
• Serial interface
• Contains a 17-dot common driver and an 80-dot segment driver.
• Contains ROM with character fonts of (5 x 7 dots) x 256.
• A built-in RC oscillator circuit.
• Provided with 80-dot arbitrators.
• Switchable between 1/9 duty (1 line; characters + cursor + arbitrator) and 1/17 duty (2 lines;
characters + cursor, 1 line; arbitrator).
• Character blink operation can be switched between all-characters lighting-on mode and all-
characters lighting-off mode.
• SiG C-MOS process
• Arbitrator blink operation can be switched between 5-dot unit mode and 1-dot unit mode.
• Package options :
128-pin plastic QFP (QFP128-P-1420-0.50-K) (MSM6665C-xxGS-K)
Aluminum pad chip
(MSM6665C-xx)
xx indicates code number.
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MSM6665C-xx
BLOCK DIAGRAM
C1 - C17
17
S1 - S80
80
SEGMENT
DRIVER
COMMON
DRIVER
VDD
VSS
VSS1
VSS2
VSS3
VSS4
VSS5
LATCH
SHIFT REGISTER
CHARACTER
GENERATOR
ROM
F/F
TEST1
TEST2
TEST3
RAM
(512bits)
GATE
(256x5x7dots)
9D/
17D
RST
FREQUENCY
DIVIDER
&
8
OSC1
OSC2
OSC3
OSC
TIMING
SERIAL/PARALLEL INTERFACE
GENERATION
CS
C/D
SHT
SO
SI
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PIN CONFIGURATION (TOP VIEW)
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48 10
S47 11
S46 12
NC 13
1
2
3
4
5
6
7
8
9
102 TEST1
101 OSC3
100 OSC2
99 NC
98 OSC1
97 VDD
96 SO
95 RST
94 9D/17D
93 SHT
92 SI
91 C/D
90 NC
S45 14
S44 15
NC 16
S43 17
S42 18
S41 19
S40 20
S39 21
S38 22
NC 23
89 CS
88 VSS1
87 NC
86 VSS2
85 VSS3
84 VSS4
83 VSS5
82 VSS (GND)
81 C1
80 NC
S37 24
S36 25
NC 26
79 C2
78 C3
77 NC
76 C4
75 C5
74 C6
73 C7
72 C8
S35 27
S34 28
S33 29
S32 30
S31 31
S30 32
S29 33
S28 34
S27 35
S26 36
S25 37
S24 38
71 C9
70 C10
69 C11
68 C12
67 C13
66 C14
65 C15
NC : No connection
128-Pin Plastic QFP
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ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Bias Voltage
Symbol
VDD
Condition
Ta=25°C, VDD–VSS
Ta=25°C, VDD–VSS5
Ta=25°C
Rating
–0.3 to +7
Unit Applicable pin
V
V
V
VDD, VSS
VBI
–0.3 to +10
–0.3 to VDD+0.3
VDD, VSS5
All inputs
Input Voltage
VI
Ta=25°C *1
QFP128-1420
Power Dissipation
PD
1210
mW
Storage Temperature
TSTG
–55 to +150
°C
*1:
The power dissipation depends on the heat sink characteristic of the package.
Set a junction temperature at 150°C or lower.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
VDD
Condition
VDD–VSS
VDD–VSS5
*1
Range
2.5 to 5.5
3 to 8
Unit Applicable pin
V
V
VDD, VSS
VDD, VSS5
OSC1
Bias Voltage
VBI
Operating Frequency
Operating Temperature
fop
65 to 115
–40 to +85
kHz
°C
Top
—
*1:
RC oscillation, external input clock frequency
(Note) Bias voltage list
(VBI=VDD–VSS5
Remarks
)
Symbol
VDD
1/5 bias
VDD
1/4 bias
VDD
Highest voltage
VSS1
VSS2
VSS3
VSS4
VSS5
VDD–1/5VBI
VDD–2/5VBI
VDD–3/5VBI
VDD–4/5VBI
VSS5
VDD–1/4VBI
VDD–2/4VBI
VDD–3/4VBI
VSS5
Lowest voltage
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ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD=2.5 to 3.5V, VBI=3 to 8V, Ta=–40 to +85°C)
Parameter
"H" Input Voltage 1
"L" Input Voltage 1
"H" Input Voltage 2
"L" Input Voltage 2
"H" Input Current 1
"L" Input Current
Symbol
VIH1
VIL1
VIH2
VIL2
IIH1
IIL
Condition
External clock input
External clock input
—
Min. Typ. Max. Unit Applicable pin
0.8VDD
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
0.2VDD
VDD
0.2VDD
1
V
V
V
V
OSC1
OSC1
0.8VDD
0
Input pins except OSC1
Input pins except OSC1
—
—
mA Input pins except TEST
mA Input pins
VI=VDD
—
–1
VI=0V
IIH2
VOH
VOL
IOFF
IOH
"H" Input Current 2
"H" Output Voltage
"L" Output Voltage
OFF Leakage
0.01
VDD–0.5
—
0.4
mA TEST 1 - 3
Pull-down resistance, VI=VDD
IOH=–1.5mA
—
V
V
SO
SO
0.5
IOL=1.5mA
—
±1
mA SO
VI=VDD/0V
OSC "H" Output Current
OSC "L" Output Current
COM Output Resistance
SEG Output Resistance
—
–0.15 mA OSC2, OSC3
VI=VDD–0.5V
VI=0.5V
IOL
0.15
—
—
6
mA OSC2, OSC3
kW C1 - C17
kW S1 - S80
RC
I0=±50mA
RS
—
18
I0=±10mA
RC oscillation, f=80kHz
C=56pF, RS=10kW
R=66kW, No load
External clock, f=80kHz
IDD1
IDD2
Supply Current 1
Supply Current 2
—
—
—
—
0.5
70
mA
—
—
mA
DC Characteristics (2)
(VDD=4.5 to 5.5V, VBI=3 to 8V, Ta=–40 to +85°C)
Parameter
"H" Input Voltage 1
"L" Input Voltage 1
"H" Input Voltage 2
"L" Input Voltage 2
"H" Input Current 1
"L" Input Current
Symbol
Condition
External clock input
External clock input
—
Min. Typ. Max. Unit Applicable pin
VIH1
VIL1
VIH2
VIL2
IIH1
IIL
0.8VDD
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
0.2VDD
VDD
0.2VDD
1
V
V
V
V
OSC1
OSC1
0.8VDD
0
Input pins except OSC1
Input pins except OSC1
—
—
mA Input pins except TEST
mA Input pins
VI=VDD
—
–1
VI=0V
IIH2
VOH
VOL
IOFF
IOH
IOL
"H" Input Current 2
"H" Output Voltage
"L" Output Voltage
OFF Leakage
0.05
VDD–0.5
—
0.7
mA TEST 1 - 3
Pull-down resistance, VI=VDD
IOH=–1.5mA
—
V
V
SO
SO
0.5
IOL=1.5mA
—
±1
mA SO
VI=VDD/0V
OSC "H" Output Current
OSC "L" Output Current
COM Output Resistance
SEG Output Resistance
—
–0.5 mA OSC2, OSC3
VI=VDD–0.5V
VI=0.5V
0.5
—
6
mA OSC2, OSC3
kW C1 - C17
kW S1 - S80
RC
—
I0=±50mA
RS
—
18
I0=±10mA
RC oscillation, f=80kHz
C=56pF, RS=10kW
R=66kW, No load
External clock, f=80kHz
IDD1
IDD2
Supply Current 1
Supply Current 2
—
—
—
—
1.3
mA
—
—
100
mA
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MSM6665C-xx
AC Characteristics
(VDD=2.5 to 5.5V, Ta=–40 to +85°C)
Parameter
CS Setup Time
Symbol
tCS
Condition
Min.
300
200
—
Max.
—
Unit
—
—
—
—
tCH
—
CS Hold Time
tON
SO ON Delay Time
200
200
tOFF
tDLY
tIS
—
SO OFF Delay Time
ns
CL=45pF
0
SO Output Delay Time
Input Setup Time
200
—
200
200
—
—
—
—
tIH
Input Hold Time
All inputs
tr, tf
tRT
100
—
Input Waveform Rise Time, Fall Time
Reset Pulse Input Pulse Width
5
µs
—
VIH2
VIL2
CS
SI
t CH
VIH2
VIL2
VIH2
VIL2
C/ D
tIS
t IH
VIH2
VIL2
SHT
t CS
"Z"
VOH
VOL
"Z"
SO
t OFF
t ON
t DLY
* VIH2=0.8VDD
RST
VIL2=0.2VDD
VOH=VDD–0.5V
VOL=0.5V
VIL2
t RT
Oscillation circuit
RS
OSC1
R
OSC2
OSC3
C
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Oscillation characteristics 1 (R =10kW, C=56pF, R variable characteristics)
S
1/17 duty
40
VDD=3.0V
VDD=5.0V
30
f=80kHz
Frame cycle¥2=27.2ms
20
10
0
55
65
75
85
95
R Resistance (kW)
Oscillation characteristics 2 (R =10kW, R=66kW, C variable characteristics)
S
1/17 duty
40
VDD=3.0V
VDD=5.0V
30
f=80kHz
Frame cycle¥2=27.2ms
20
10
0
35
45
55
65
75
C Capacitance (pF)
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FUNCTIONAL DESCRIPTION
Pin Functional Description
• SI (Serial Input)
Input pin for inputting serially commands and display data in an 8-bit unit.
"H"=1 and "L"=0.
When CS pin is at “H” level, read-in is executed by the leading edge of SHT.
Whether input data is a command or data is determined by selecting a C/D level at the
8th leading edge of SHT.
The input data is a command if C/D="H", and display data if C/D="L".
• C/D (Command/Data)
Input pin for determining whether input data for SI pin is a command or display data.
Read-in is executed by the 8th leading edge of SHT. The input data is a command if C/
D="H", and display data if C/D="L".
• SHT (Shift Clock)
Clock input pin for reading-in SI input and C/D input.
Read-in is executed by the clock leading edge. Read-in operation is complete with 8
clocks. Maintain this SHT pin at "H" when there is no command and data input from the
SI pin. Inputting data during BUSY may cause malfunction.
Valid if CS pin is at "H" level.
• SO (Serial Out)
Serial output pin for reading-out BUSY/NON-BUSY and display data. "H"="1" and
"L"="0". If CS pin is at "H" level and Serial out Enable is set with the command, output
is executed.
Otherwise, this pin becomes high impedance. BUSY/NON-BUSY is output when CS
pin is at "H" level. BUSY if "L" and NON-BUSY if "H". It goes BUSY after the 8th leading
edge of SHT, then goes NON-BUSY automatically after a certain time.
Display data is output synchronously with the leading edge of SHT.
InputinstructionSOE/DtosetthisoutputtoSerialOutEnableorahighimpedancestate
since the pin status is undefined after the power is applied.
• CS (Chip Select)
Chip Select input pin.
"Chip Select ON" if CS pin is at "H" level, and "Chip Select OFF" at "L" level. When "L"
level is input, SO pin becomes open and SHT pin becomes equivalent to "H" level inside
of the IC. Moreover, it prevents the input rows of SI, C/D and SHT pins from current
flowing.
Note: For SI, C/D, SHT, SO, and CS, refer to "I/O Procedure".
• RST
Direct input reset input pin.
By inputting "L" level pulse into RST pin, SOE/D, DISP, ABBC1/5, and ABB commands
are set as D0="0". Before turning on the power, be sure to set RST pin at "L" level once.
Setting this pin at "L" level during command execution may cause malfunction.
• 9D/17D (1/9Duty/1/17Duty)
Duty setting input pin.
1/9duty is set if this pin is at "H" level, and 1/17duty at "L" level. Choice depends on the
type of panel to be used.
If 1/9duty is selected, common outputs C10 to C17 should be set open.
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• TEST1, TEST2, TEST3
Test signal input pins.
The manufacturer uses these pins for testing.
The user should make these pins short-circuited to GND or open.
• OSC1, OSC2, OSC3
Pins used for 80kHz RC oscillation circuit formation and as external master clock input
pin.OSC2andOSC3areopenduringinputofexternalmasterclock. Seediagrambelow.
OSC1
10k
W
W
OSC1
OSC2
OSC3
80kHz
62±5k
OSC2
OPEN
56pF
OSC3
OPEN
[RC oscillation circuit formation]
< Oscillation circuit wiring diagram >
• C1 to C17, S1 to S80 (Common 1 - 17, Segment 1 - 80)
[External master clock input]
LCDoutputpinstobeconnectedwiththeLCDpanel. TurningintoACismadebyframe
inversion. During use at 1/9duty, C1 to C9 pins are used, and C10 to C17 pins are set
open. See figure below.
Arbitrator
C1
C2
C8
C9
Cursor
Cursor
C10
C16
C17
S1
S80
<Relationship between panel and LCD output>
• V , V
DD
SS
Supply voltage pins. V should be set at "H" level.
DD
V
SS
is a GND pin. If the battery is used, V is connected to the + pin, and V to the
DD SS
– pin.
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• V , V , V , V , V
SS5
SS1
SS2
SS3
SS4
LCD bias voltages input pins.
The voltages that are input via V and V to V are output for driving LCD.
DD
SS1
SS5
The LCD bias voltages are shown below.
[Case of 1/5 bias] (V =V –V
)
BI DD SS5
Highest voltage :
V
DD
V
V
V
V
V
(V –1/5 V )
DD BI
SS1
SS2
SS3
SS4
SS5
(V –2/5 V )
DD
BI
(V –3/5 V )
DD
BI
(V –4/5 V )
DD
BI
Lowest voltage :
[Case of 1/4 bias] (V =V –V
)
BI DD SS5
Highest voltage :
V
DD
V
V
V
V
(V –1/4 V )
DD BI
(V –2/4 V )
DD BI
SS1
, V
SS2 SS3
(V –3/4 V )
SS4
DD
BI
Lowest voltage :
SS5
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List of Commands
X : Don't care
D
No. Mnemonics
Operation
Comments
7
6
5
4
3
2
1
0
1
2
3
LPA
Load Pointer
Address
1
1
A5 A4 A3 A2 A1 A0 Serial addresses 0 to 47
Load Option
LOT
Meanings for I1 and I0 are set as in
the table below.
1
1
0
0
1
0
1
X
0
X
0
I1 I0
Valid only when 1/9duty.
Switching between display addresses
0 and 15, and between 16 and 31.
Bank Change 1/0
BKCG 1/0
X
0
1/0
Switching output and high impedance
of SO
4
5
6
SOE/D
Serial Out
Enable/Disable
1
1
0
0
0
0
X
X
0
1
1
0
1
0
1/0
1/0
Display ON if D0="1"
Display OFF if D0="0"
Display on/off
DISP
Sets arbitrator blink in a 1dot unit or
a 5dot unit. 1dot if D0="1", 5 dot if
D0="0"
Data that is input via SI after setting
D0="1", is set as data for arbitrator
blink (1-dot unit). This is cancelled by
D0="0"
ABBC 1/5
Arbitrator Blink
Control 1/5 dot
1
1
0
0
0
0
1
0
1
1
1
1
0
0
1/0
1/0
Arbitrator Blink
7
ABB
Address Increment
8
9
AINC
CHB
Pointer address is incremented by 1.
1
0
0
0
X
X
1
0
X
0
1
X
X
Controls blinking of characters and
arbitrators (5-dot). Though arbitrator
blink that is set as all-blank dispalyed
is acceptable, blinking does not occur.
Character Blink on/off
X
X
1/0
10
11
CSC
CSB
Cursor Control
on/off
Turns cursor on or off.
0
0
X
X
X
X
X
X
0
1
1
0
1/0
1/0
X
X
Controls blinking of cursor.
But, though blinking setting with
no cursor-on setting is acceptable,
blinking does not occur.
Cursor Blink
on/off
12
13
CCB
BPC
Character & Cursor
Blink on/off
0
1
X
0
X
0
X
X
1
0
1
0
1/0
1
X
CHB + CSB
Sets blink patterns of characters.
Blink Pattern
Control
1/0
(
:chara.) if D0="1" ( :chara.)
n
q
if D0="0"
Notes :
1. Commands number 1 to 7 and command number 13 do not affect pointer address.
2. By entering commands number 8 to 12 or display code data, pointer address is
automatically incremented by 1.
3. When Reset is entered, commands numbers 5 to 7 or number 13 are set to D0="0".
I1
0
I0
0
Operation
Operation is canceled. (No operation)
0
1
Hereafter, equivalent to writing blank code at each AINC execution.
Hereafter, cursor-off and blink-cancellation are executed at each AINC execution.
Both of above two operations are made.
1
0
1
1
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Command Description
[D7, D6, D5, D4, D3, D2, D1, D0], X=don’t care
• LPA (Load Pointer Address)
[1,1,A5,A4,A3,A2,A1,A0]
The command sets "address" data into the address pointer to specify an address on
which command execution affects and an address where display data is stored. The
"address" is a number between 0 and 2FH, given by A0 through A5 in hexadecimal.
When addresses 30H through 3FH are specified, display data and CHB, CSC, CSB, CCB
commands become invalid through an address pointer is set up. Normally, the address
pointer is a loop of 0H through 2FH.
• LOT (Load Option)
[1,0,1,1,X,X,I1,I0]
Thiscommandindicatessomespecificoperationofdisplayatthecurrentaddresswhich
is performed each time of AINC command execution.
Operation is specified by bit I1 and I0 of the command.
I1
0
I0
0
Operation
Operation is cancelled. (No operation)
0
1
Hereafter, equivalent to writing blank code at each AINC execution.
Hereafter, Cursor-off and blink-cancellation are executed at each AINC execution.
Both of above two operations are made.
1
0
1
1
Note: When blink-cancellation is executed, all RAM data, which controls blinks for each bit
of the arbitrator, go zeros.
• BKCG 1/0 (Bank Change 1/0)
[1,0,0,X,0,0,0,1/0]
Command used to do switching between display address groups (switching between
BANKs), which is valid only when 1/9duty display is selected.
When D0 is "0", display address range becomes 0 through 15, and 32 through 47.
When D0 is "1", display address range becomes 16 through 31, and 32 through 47.
Command execution and display data setting are not affected by Bank setting.
The D0 status is not changed by Reset inputting. The D0 status is unknown when the
system is powered on. So D0 must be set to "0" or "1" with the command.
• SOE/D (Serial Out Enable/Disable)
[1,0,0,X,0,1,1,1/0]
Command used to control the impedance of SO output pin.
When D0 is "1", display data is output via SO pin. When D0 is "0", SO pin goes to high
impedance.
The D0 status is not changed by Reset inputting. The D0 status is unknown when the
system is powered on. So D0 must be set to "0" or "1" with the command.
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• DISP (Display on/off)
[1,0,0,X,1,0,0,1/0]
Command used to control display-on and display-off of the LCD panel.
When D0 is "1", the display of the LCD panel goes on, and When D0 is "0", it goes off.
When the display is off, the V level voltage is output on all of pins of both the segment
DD
drivers and the common drivers.
D0 is set to "0" after inputting Reset.
• ABBC 1/5 (Arbitrator Blink Control 1/5 dot)
[1,0,0,1,1,1,0,1/0]
Command used to do switching between arbitrator’s blinking in a 1-dot unit and or in
a 5-dot unit.
When D0 is "1", arbitrator’s blinking comes in the 1 dot unit mode.
When D0 is "0", it comes in the 5-dot unit mode.
D0="0" is set after inputting Reset.
Note: 1-dot unit blink setting Æ See ABB.
5-dot unit blink setting Æ See CHB.
• ABB (Arbitrator Blink)
[1,0,0,0,1,1,0,1/0]
Command used to control on/off of blinking, which is valid only when arbitrator’s
blinking is set in the 1-dot unit mode.
Data , which are entered via SI pin after setting D0="1", are taken as arbitrator blink data
(1-dot unit).
Input blink data correspond to each of arbitrator’s dots. When "1", blinking is on, and
when "0", blinking is off.
Note that the arbitrator, which arbitrator-on is not specified, is not able to blink, though
blink-setting is available. Dummy data must be entered into the arbitrator blink data D5
thru D7.
It is impossible to write data in addresses 00 through 31.
D0="0" is set after inputting Reset.
Note: If blink is set in the 5-dot unit mode, ABB command setting (D0="1" or "0") is
available, but blink-on/off setting via input of display data is impossible.
• AINC (Address Increment)
[1,0,0,X,1,X,1,X]
Command used to increment the value of the address pointer by 1.
The pointer is increment by 1 each time this command is executed. The operation set by
LOT command is given to the address before being increased by 1 each time this
command is execution.
13/32
OKI Semiconductor
MSM6665C-xx
• CHB (Character Blink on/off)
[0,X,X,X,0,0,1/0,X]
Command used to control blinking of characters and arbitrator (5-dot unit).
This command is executed to the address indicated by the address pointer. Blinking is
on by setting D1="1", and off by setting D1="0".
For blinking of characters, all lighting-on or all lighting-off, and characters-displaying
are repeated.
Choosing between all lighting-on and all lighting-off is controlled by BPC command.
For arbitrator, only lighting bits repeat lighting-off and lighting-on. The blink control or
arbitrator is valid only when ABBC1/5="0" and in the 5-dot unit mode.
Refer to BPC.
• CSC (Cursor Control on/off)
[0,X,X,X,0,1,1/0,X]
Command used to control lighting-on and lighting-off of cursor.
This command is executed to the address indicated by the address pointer.The cursor
is lighting on by setting D1="1", and lighting off by setting D1="0".
• CSB (Cursor Blink on/off)
[0,X,X,X,1,0,1/0,X]
Command used to control blinking of cursor.
This command is executed to the address indicated by the address pointer. Blinking is
on by setting D1="1", and off by setting D1="0".
The blinking in the address, where cursor-lighting-on is not specified, does not occur,
though the command of blinking is acceptable. Blinking starts by specifying cursor-
lighting-on.
• CCB (Character & Cursor Blink on/off)
[0,X,X,X,1,1,1/0,X]
Command used to execute both CHB command and CSB command.
• BPC (Blink Pattern Control)
[1,0,0,X,0,0,1,1/0]
Command used to control blink patterns of characters.
When D0="1" is set, all lighting-off (35 dots) and characters-displaying are repeated.
When D0="0" is set, all lighting-on (35 dots) and characters-displaying are repeated.
When D0="1" is set, if characters are blanks, their blinkings do not occur in appearance.
When D0="0" is set, if characters are in all lighting-on, their blinkings do not occur in
appearance.
D0 is set to "0" after inputting Reset.
[D0 = "1"]
[D0 = "0"]
• Increment (+1) in address pointer
When display data or arbitrator data (1-dot unit) is entered or when the following
commands are executed, the address pointer is incremented by 1.
AINC, CHB, CSC, CSB and CCB.
14/32
OKI Semiconductor
MSM6665C-xx
I/O Procedure
• Input timing (command input, display data input)
8-bit input synchronization is taken by this leading edge.
If input in an 8-bit unit is kept, the following leading edges of CS is not needed.
CS
don't care
C/D
C/ D
MSB
MSB
LSB
LSB
SI
SHT
SO
"Z"
BUSY
BUSY
NON-BUSY/
17D : Max=[Master clock cycle] x 10
9D : Max=[Master clock cycle] x 20
• Output timing (display code data output)
Codedataorarbitratordataindicatedbytheaddresspointerisalwaysoutput, provided
that the SOE command has already been input.
Synchronization in an 8-bit unit.
don't care
CS
C/ D
SHT
LSB
"Z"
BUSY
MSB
SO
NON-BUSY
NON-BUSY/ BUSY
17D : Max=[Master clock cycle] x 10
9D : Max=[Master clock cycle] x 20
Note: If CS is set at "L" level when 8-bit read-out is not complete, and CS is set at "H" level
again, then read-out operation is executed, uncomplete data will be output continually
and the remaining read-out data will be zero.
15/32
OKI Semiconductor
MSM6665C-xx
Various Frequency Calculation Method
• Original Clock Frequency and Blink Frequency
Blink cycle calculation
([Original clock cycle] x 5) x 2 = Blink cycle ............................................. Formula 1
From formula 1, the blink frequency can be calculated.
14
Example)
When the original clock frequency is 80kHz.
Clock cycle Ts=12.5[µs]
From formula 1,
Blink cycle Tb=(12.5 x 10 x 5) x 2 = 1.024 [s]
-6
14
Thus,
Blink frequency = 1 [Hz]
• Original Clock Frequency and Frame Frequency
Frame cycle calculation
1/9 DUTY: (Original clock cycle) x 1152 = Frame cycle............................. Formula 2
1/17 DUTY: (Original clock cycle) x 1088 = Frame cycle........................... Formula 3
From Formula 2,3 the blink frequency can be calculated.
Example)
In the original clock 80kHz and 1/17 DUTY specifications
Clock cycle Ts=12.5 [µs]
From formula 3,
Clock cycle Tf=12.5 x 10 x 1088 = 13.6 [ms]
-6
Thus,
Frame frequency = 73.5 [Hz]
16/32
OKI Semiconductor
MSM6665C-xx
Display and Memory Address
Arbitrator
Character 1
Cursor 1
Display
Character 2
Cursor 2
Arbitrator
32
33
47
Character 1
0
0
1
1
15
15
31
Cursor 1
RAM map
16
17
Character 2
16
17
31
Cursor 2
Note: Characters are entered with codes.
Arbitrator is displayed with no CG ROM. The relationship between input data and
display is shown below.
S5n+1
D4
S5n+5
D0
n : 0 - 15
Dummy input is required for serial data D7 through D5. Either "1" or "0" is available
for data to be input into D7 through D5.
17/32
1Semiconductor
Flowchart for Power-On Timing
Turn on power
Reset input
5µs required; external reset input or power-on reset input
10 clocks at 1/17 duty
20 clocks at 1/9 duty
Wait for 20 clocks
CS=“H”
Clock input for initial busy clear.
The device is enabled.
SOE/D, D0=“1”
Wait for 20 clocks
Make the SO output enable, to perform busy detection.
Input a wait for the SOE/D command processing. (For the processing
of each command after this, perform busy detection. *1)
BPC and BKCG
command set
Set the blink pattern and bank change mode.
Set the Load Option. (Blank-code writing and blink-cancellation
are executed each time the AINC command is executed.)
LOT, I1=“1”, I0=“1”
LPA=”00”
Set RAM address to “00”.
AINC executed 48 times Input the AINC command to clear the RAM data.
LOT, I1=“0”, I0=“0”
Release the Load Option.
Input display data for initial screen
NO
Is Input of display data for
initial screen completed?
YES
DISP, D0=“1”
Display is turned on and the initial screen is displayed.
Normal operation
*1 After the required commands and display data are entered, perform busy detection based on the
SO pin status. When it is confirmed that the status has been changed from BUSY (SO = “L”) to
NON-BUSY (SO = “H”), enter the next data.
If busy detection is not performed, wait for 10 master oscillation clocks when used at 1/17 duty or for
20 master oscillation clocks when at 1/9 duty, then enter the next data.
18/32
OKI Semiconductor
MSM6665C-xx
Waveforms Applied to LCD
1/17 duty (1/5 bias)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VDD
VSS1
VSS2
VSS3
VSS4
VSS5
C1
C2
VDD
VSS1
VSS2
VSS3
VSS4
VSS5
VDD
VSS1
VSS2
VSS3
VSS4
VSS5
C17
VDD
VSS1
VSS2
VSS3
VSS4
VSS5
Sn
= lighting on
= lighting off
19/32
OKI Semiconductor
1/9duty (1/4 bias)
MSM6665C-xx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8
9
VDD
VSS1
VSS2, 3
VSS4
VSS5
C1
C2
VDD
VSS1
VSS2, 3
VSS4
VSS5
VDD
VSS1
VSS2, 3
VSS4
VSS5
C9
Sn
VDD
VSS1
VSS2, 3
VSS4
VSS5
= lighting on
= lighting off
20/32
OKI Semiconductor
1/17 duty (1/4 bias)
MSM6665C-xx
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VDD
VSS1
VSS2, 3
VSS4
VSS5
C1
C2
VDD
VSS1
VSS2, 3
VSS4
VSS5
VDD
VSS1
VSS2, 3
VSS4
VSS5
C17
Sn
VDD
VSS1
VSS2, 3
VSS4
VSS5
= lighting on
= lighting off
21/32
OKI Semiconductor
MSM6665C-xx
Character Codes and Fonts of MSM6665C-02
00H :
01H :
02H :
03H :
04H :
05H :
06H :
07H :
08H :
09H :
0AH :
0BH :
0CH :
0DH :
0EH :
0FH :
10H :
11H :
12H :
13H :
14H :
15H :
16H :
17H :
18H :
19H :
1AH :
1BH :
1CH :
1DH :
1EH :
1FH :
20H : SP
21H : !
22H : "
28H : (
29H : )
2AH : *
2BH : +
2CH : ,
2DH : -
2EH : .
2FH : /
30H : 0
31H : 1
32H : 2
33H : 3
34H : 4
35H : 5
36H : 6
37H : 7
38H : 8
39H : 9
3AH : :
23H : #
24H : $
25H : %
26H : &
27H : '
3BH : ;
3CH : <
3DH : =
3EH : >
3FH : ?
22/32
OKI Semiconductor
MSM6665C-xx
58H : X
59H : Y
5AH : Z
5BH : [
5CH : \
5DH : ]
5EH : ^
5FH : _
40H : @
41H : A
42H : B
43H : C
44H : D
45H : E
46H : F
47H : G
48H : H
50H : P
51H : Q
52H : R
53H : S
54H : T
55H : U
56H : V
57H : W
60H : `
61H : a
62H : b
63H : c
64H : d
65H : e
66H : f
67H : g
68H : h
69H : i
6AH : j
6BH : k
6CH : l
6DH : m
6EH : n
6FH : o
78H : x
70H : p
71H : q
72H : r
73H : s
74H : t
75H : u
76H : v
77H : w
49H : I
79H : y
4AH : J
4BH : K
4CH : L
4DH : M
4EH : N
4FH : O
7AH : z
7BH : {
7CH : |
7DH : }
7EH : ~
7FH :
23/32
OKI Semiconductor
MSM6665C-xx
24/32
OKI Semiconductor
MSM6665C-xx
25/32
OKI Semiconductor
MSM6665C-xx
APPLICATION CIRCUITS
Example :
1/17 duty, 1/5 bias
Cursor-contained (5 x 7 dots)16-character x 2-line LCD panel
17 dots
COM
80 dots
SEG
C1 - C17
S1
-
S80
10kW
62kW
OSC1
OSC2
OSC3
OSC1
OSC2
OSC3
VDD
80kHz
OPEN
MSM6665C-xx
or
VSS1
56pF
OPEN
VSS2
VSS3
LCD bias
VSS4
VSS5
9D/
Vss
17D
RST
TEST 1~3
CS C/D SHT SO SI
PORT
26/32
OKI Semiconductor
MSM6665C-xx
PAD CONFIGURATION
Pad Layout
Chip size : 6.09 ¥ 4.97mm
Passivation film etched hole : 110 ¥ 110mm
Y
92
59
93
58
X
117
34
1
33
Pad Coordinates
X (µm)
533
683
833
983
Y (µm)
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–1797
–1647
–1347
–1197
–1047
–897
Pad No. Pad Name
X (µm)
–2486
–2336
–2186
–2036
–1886
–1736
–1586
–1436
–1286
–1136
–986
–836
–686
–536
–386
–227
–67
Y (µm)
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
Pad No.
21
Pad Name
VSS1
CS
1
2
3
4
5
C15
C14
C13
C12
C11
C10
C9
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
C/D
SI
SHT
9D/17D
RST
1133
1283
1433
1583
1733
1891
2308
2489
2639
2870
2870
2870
2870
2870
2870
2870
6
7
8
C8
SO
VDD
9
C7
10
11
12
13
14
15
16
17
18
19
20
C6
C5
C4
C3
C2
C1
VSS
VSS5
VSS4
VSS3
VSS2
OSC1
OSC2
OSC3
TEST1
TEST2
TEST3
S80
S79
S78
S77
S76
83
233
383
38
39
40
–747
27/32
OKI Semiconductor
MSM6665C-xx
Pad No. Pad Name
X (µm)
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2482
2332
2182
2032
1882
1732
1582
1432
1282
1132
982
Y (µm)
–597
–447
–297
–147
3
153
303
453
603
Pad No. Pad Name
X (µm)
Y (µm)
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
1803
1653
1503
1353
1203
1053
903
753
603
453
303
153
3
–147
–297
–447
–597
–747
–897
–1047
–1197
–1347
–1497
–1647
–1797
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
–818
–968
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
–1118
–1268
–1418
–1568
–1718
–1868
–2018
–2168
–2318
–2468
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
753
903
1053
1203
1353
1503
1653
1803
1953
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
S8
S7
S6
S5
S4
S3
S2
S1
832
682
532
382
232
82
–68
–218
–368
–518
–668
C17
C16
28/32
OKI Semiconductor
MSM6665C-xx
Pin and Pad Correspondence
The symbol for each chip pad and package pin is equal, but the numbers for each pad and pin
are not equal.
If both chips and packaged devices are used, the number for each chip pad should be
corresponded to the number for each package pin according to each symbol listed in the table
below.
Chip Package
Chip Package
Chip Package
Chip Package
Symbol
C15
Symbol
Symbol
Symbol
Pad
1
Pin
65
66
67
68
69
70
71
72
73
74
75
76
78
79
81
82
83
84
85
86
88
89
91
92
93
94
95
96
97
98
Pad
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin
100
101
102
103
104
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1
Pad
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Pin
3
Pad
91
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
–
OSC2
OSC3
TEST1
TEST2
TEST3
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
C14
C13
C12
C11
C10
C9
2
4
92
3
5
93
4
6
94
5
7
95
6
8
96
7
9
97
C8
8
10
11
12
14
15
17
18
19
20
21
22
24
25
27
28
29
30
31
32
33
34
35
36
98
C7
9
99
C6
10
11
12
13
14
15
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
–
C5
C4
C3
C2
C1
V
SS(GND) 16
VSS5
VSS4
VSS3
VSS2
VSS1
CS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S8
S7
S6
S5
S4
C/D
S3
SI
S2
SHT
9D/17D
RST
SO
S1
C17
C16
–
VDD
OSC1
–
–
–
2
–
–
–
29/32
OKI Semiconductor
MSM6665C-xx
PACKAGE DIMENSIONS
(Unit : mm)
QFP128-P-1420-0.50-K
.
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
1.19 TYP.
4/Nov. 28, 1996
Oki Electric Industry Co., Ltd.
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
30/32
1Semiconductor
REVISION HISTORY
Page
Document No.
Date
Description
Previous
Current
Edition
Edition
—
FEDL6665C-02
FEDL6665C-03
Aug. 2000
—
27
31
Second edition
Mar. 15, 2002
27
—
Modified pad layout.
Added Revision History.
Added the 9th step and modified the 11th step in
the flowchart.
FEDL6665C-04
Dec. 27, 2004
18
18
31/32
1Semiconductor
NOTICE
1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is
up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party’s right which may result
from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2004 Oki Electric Industry Co., Ltd.
32/32
相关型号：
MSM6665C-02GS-K
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