MSM66Q589 [OKI]
OLMS-66K Series CMOS 16-Bit Microcontroller; OLMS - 66K CMOS系列16位微控制器
| 型号： | MSM66Q589 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | OLMS-66K Series CMOS 16-Bit Microcontroller |
| 文件： | 总27页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2E1031-27-Y4
Preliminary
This version: Jan. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM66589/66P589/66Q589
OLMS-66K Series CMOS 16-Bit Microcontroller
GENERAL DESCRIPTION
The MSM66589/66P589/66Q589 is a high-speed, high-performance 16-bit microcontroller that
employs OKI original nX-8/500S CPU core.
The MSM66589/66P589/66Q589 includes a 16-bit CPU, ROM, RAM, a 10-bit A/D converter,
serial ports, flexible timers, pulse-width modulator (PWM), and I/O ports.
The MSM66Q589 is a Flash EEPROM version.
FEATURES
• Program memory space
Internal ROM
: 128K bytes
: 96K bytes (MSM66589/66P589)
: 128K bytes (MSM66Q589)
: 64K bytes
• Data memory space
Internal RAM
: 4K bytes
• High-speed execution
Minimum instruction execution time : 100 nsec (@ 20 MHz)
• Built-in multiplier
• Powerful instruction set
: Instruction set superior in orthogonal matrix
8/16-bit data transfer instructions
8/16-bit arithmetic instructions
Multiplication and division operation instructions
Bit manipulation instructions
Bit logic instructions
ROM table reference instructions
: Register addressing
• Abundant addressing modes
Page addressing
Pointing register indirect addressing
Stack addressing
Immediate addressing
• I/O port
Analog input only ports
Input-output ports
: 16 channels
: 11 ports ¥ 8 bits, 1 port ¥ 6 bits
(Each bit can be configured to be an input or output)
• Flexible timers
Free run counters
19-bit CAP with a divider
16-bit double buffer RTO
16-bit RTO/PWM
16-bit CAP/RTO
: 19 bits ¥ 1, 16 bits ¥ 1
: 4
: 6
: 2
: 6
: 1
: 1
: 8
: 1
• 8-bit general timer
8-bit event counter
• 16-bit PWM
Input clock divider
• 8-bit serial ports
1/27
¡ Semiconductor
MSM66589/66P589/66Q589
UART mode with BRG
Synchronous/UART switchable mode
with BRG
: 1
: 1
• 10-bit A/D converter
• Transition detector
• Watchdog timer
• Interrupts
: 16 channels
: 6
: 1
Non-maskable
: 1
Maskable
: Internal 47/external 2
(4-level priority can be set)
• ROM window function
• Standby modes
HALT mode
STOP mode
• Package:
128-pin plastic QFP (QFP128-P-2828-BK)
(Product name: MSM66589-¥¥¥GS-BK)
(Product name: MSM66P589-¥¥¥GS-BK)
(Product name: MSM66Q589GS-BK)
¥¥¥ indicates the code number.
2/27
¡ Semiconductor
MSM66589/66P589/66Q589
BLOCK DIAGRAM
BUS PORT CONTROL
3/27
P6_1/INT1 33
P6_2/RXD1 34
P6_3/TXD1 35
P6_4/RXC1 36
P6_5/TXC1 37
P6_6/RXD0 38
P6_7/TXD0 39
GND 40
128 TRNS2/P4_4
127 TRNS1/P4_3
126 TRNS0/P4_2
125 ECTCK/P4_1
124 ETMCK/P4_0
123 P11_7
122 P11_6
121 P11_5
OSC0 41
120 P11_4
OSC1 42
119 P11_3
P5_5/ALE 43
P5_4/PSEN 44
P7_0/WR 45
P7_1/RD 46
P7_2/WAIT 47
P7_3/CLKOUT 48
P7_4/PWM0 49
P7_5/PWM1 50
P7_6/PWM2 51
P7_7/PWM3 52
VDD 53
118 P11_2
117 P11_1
116 P11_0
115 VDD
114 CAP3/P3_7
113 CAP2/P3_6
112 CAP1/P3_5
111 CAP0/P3_4
110 FTM11D/P3_3
109 FTM11C/P3_2
108 FTM11B/P3_1
107 FTM11A/P3_0
106 GND
P8_0/PWM4 54
P8_1/PWM5 55
P8_2/PWM6 56
P8_3/PWM7 57
P8_4 58
105 P10_7
104 P10_6
103 FTM17/P10_5
102 FTM16/P10_4
101 FTM15/P10_3
100 FTM14/P10_2
99 RTO13/P10_1
98 RTO12/P10_0
97 P2_7
P8_5 59
P8_6 60
P8_7 61
GND 62
OE 63
P0_0/AD0 64
¡ Semiconductor
MSM66589/66P589/66Q589
PIN DESCRIPTION
Symbol
Type
Description
P0: 8-bit input-output port. Each bit can be assigned to be an input or an output.
AD: When an external memory is used, these pins output the lower 8 bits of the address.
These pins also input or output the data.
P0_0-P0_7/
AD0-AD7
I/O
P1_0-P1_7/
A8-A15
P1: 8-bit input-output port. Each bit can be assigned to input or output.
A: When an external memory is used, these pins output the upper 8 bits of the address.
I/O
I/O
P2_0-P2_5/
RTO4-RTO9
P2_6/FTM10
P2_7
P2: 8-bit input-output port. Each bit can be assigned to input or output.
RTO: Output pin for real time output
FTM10: Capture input pin or real-time output pin
P3_0-P3_3/
FTM11A-FTM11D
P3_4-P3_7/
P3: 8-bit input-output port. Each bit can be assigned to input or output.
FTM11A: Capture input pin or real-time output pin
FTM11B-D: 4-port real-time output pin
I/O
I/O
CAP0-CAP3
CAP : Capture input pin
P4_0/ETMCK
P4_1/ECTCK
P4_2-P4_7/
P4: 8-bit input-output port. Each bit can be assigned to input or output.
ETMCK: External clock input pin of 8-bit general timer
ECTCK: External clock input pin of 8-bit event counter
TRNS: Transition detector input pin
TRNS0-TRNS5
P5_0-P5_3
P5_4/PSEN
P5_5/ALE
P5: 6-bit input-output port. Each bit can be assigned to input or output.
PSEN: Strobe pulse output pin to fetch to external program memory
ALE: Timing pulse output pin to latch the lower 8 bits of the address output from port 0
when the CPU accesses the external memory
I/O
I/O
P6: 8-bit input-output port. Each bit can be assigned to input or output.
INT0, 1: External interrupt request input pin
RXD1 : SCI1 Receiver data input pin
TXD1 : SCI1 Transmitter data output pin
RXC1 : SCI1 Receiver circuit clock pin
TXC1 : SCI1 Transmitter circuit clock pin
RXD0 : SCI0 Receiver data input pin
TXD0 : SCI0 Transmitter data output pin
P6_0/INT0
P6_1/INT1
P6_2/RXD1
P6_3/TXD1
P6_4/RXC1
P6_5/TXC1
P6_6/RXD0
P6_7/TXD0
P7: 8-bit input-output port. Each bit can be assigned to input or output.
WR: Write strobe output pin for external data memory
RD: Read strobe output pin for external data memory
WAIT: CPU wait request input pin when accessing external data memory
CLKOUT: Output pin to output clock pulse specified by PRPHF
PWM: PWM output pin
P7_0/WR
P7_1/RD
P7_2/WAIT
P7_3/CLKOUT
P7_4-P7_7/
PWM0-PWM3
I/O
P8: 8-bit input-output port. Each bit can be assigned to input or output.
PWM: PWM output pin
P8_0-P8_3/
PWM4-PWM7
P8_4-P8_7
I/O
I/O
P9_0/A16
P9_1-P9_7
P9: 8-bit input-output port. Each bit can be assigned to input or output.
A16: When an external program memory is used, this pin outputs the MSB of the
address.
P10: 8-bit input-output port. Each bit can be assigned to input or output.
RTO: Output pin for real time output.
FTM: Capture input pin or real-time output pin
P10_0-P10_1/
RTO12-RTO13
P10_2-P10_5/
FTM14-FTM17
P10_6-P10_7
I/O
I/O
P11_0-P11_7
P11: 8-bit input-output port. Each bit can be assigned to input or output.
5/27
¡ Semiconductor
MSM66589/66P589/66Q589
PIN DESCRIPTION (Continued)
Symbol
Type
Description
Analog signal input pin for A/D converter
I
AI0-AI15
I
AVDD
Power supply input pin for A/D converter
Reference voltage input pin for A/D converter
GND input pin for A/D converter
I
I
VREF
AGND
OSC0
OSC1
I
Basic clock oscillation pin
O
When P0, P1, P2, P7_4-P7_7, and P8-P11 are in an output state and OE pin is "H"
level, P0, P1, P2, P7_4-P7_7, and P8-P11 go to a high-impedance state.
When P0, P1, P2, P7_4-P7_7, and P8-P11 are in an output state and OE pin is "L"
level, P0, P1, P2, P7_4-P7_7, and P8-P11 output "H" or "L" level.
However, when P0, P1, P2, P7_4-P7_7, and P8-P11 are in an input state, these
ports are not under the influence of OE pin.
I
OE
I
I
NMI
Nonmaskable interrupt request input pin
Low-active RESET input pin
RES
Normally set to "H" level. If set to "L" level, the program memory goes into
external access mode and accesses external program memory
I
EA
I
I
VDD
Power supply pin
Ground pin
GND
6/27
¡ Semiconductor
MSM66589/66P589/66Q589
REGISTERS
Accumulator
15
15
0
ACC
Control Register (CR)
Program Status Word
0
PSW
Bit 15 : Carry flag (CY)
Bit 14 : Zero flag (ZF)
Bit 13 : Half carry flag (HC)
Bit 12 : Data descriptor (DD)
Bit 11 : Sign flag (S)
Bit 10 : Master interrupt priority flag (MIP)
Bit 9 : Overflow flag (OV)
Bit 8 : Master interrupt enable flag (MIE)
Bit 7 : Multiply and accumulate operation bank flag (MAB)*
Bit 6 : User flag (F1)
Bit 5 : Bank common base (BCB1)*
Bit 4 : Bank common base (BCB0)*
Bit 3 : User flag (F0)
Bit 2-0 : System control base 2-0 (SCB2-0)
* Bit 7 (MAB), Bit 5 (BCB1), and Bit 4 (BCB0) can be used
as the User flag.
15
0
Program Counter
Local Register Base
System Stack Pointer
PC
LRB
SSP
Segment Register
7
0
Code Segment Register
CSR
TSR
Table Segment Register
Pointing Register (PR)
15
0
Index Register 1
Index Register 2
Data pointer
X1
X2
DP
User Stack Pointer
USP
7/27
¡ Semiconductor
MSM66589/66P589/66Q589
7
0 7
0
Local Register
ER0
ER1
ER2
R1
R3
R5
R7
R0
R2
R4
R6
ER3
8/27
¡ Semiconductor
MSM66589/66P589/66Q589
SFR
Abbreviated Abbreviated
Name (BYTE) Name (WORD)
8/16
Operation
Reset
Status
Address [H]
Name
R/W
0000
0001
0002
0003
0004
0005
0006
0007
0008✩
0009
000A
000B
000C✩
000D✩
000E
000F✩
0010
0011
0012
0013
0014
0015✩
0016
0017
0018
0019
001A
001B
001C
001D✩
001E
001F
—
SSP
LRB
PSW
16
FFFF
System Stack Pointer
Local Register Base
Program Status Word
LRBL
LRBH
PSWL
PSWH
ACCL
ACCH
TSR
Undefined
00
00
00
00
00
R/W
8/16
8
ACC
—
Accumulator
Table Segment Register
ROMWIN
ROMRDY
RAMRDY
STPACP
SBYCON
P0
—
—
—
—
—
00
FF
ROM Window Register
ROM Ready Control Register
RAM Ready Control Register
Stop Code Acceptor
Standby Control Register
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Port 6 Data Register
Port 7 Data Register
Port 0 Mode Register
Port 1 Mode Register
Port 2 Mode Register
Port 3 Mode Register
Port 4 Mode Register
Port 5 Mode Register
Port 6 Mode Register
Port 7 Mode Register
Port 8 Data Register
Port 9 Data Register
Port 10 Data Register
Port 11 Data Register
R/W
W
8
FF
"0"
C8
00
00
00
00
00
C0
00
00
00
00
00
00
00
C0
00
00
00
00
00
00
P0P1
P2P3
P1
P2
P3
P4
P4P5
P5
P6
P6P7
P7
P0IO
P1IO
P2IO
P3IO
P4IO
P5IO
P6IO
P7IO
P8
P0P1IO
P2P3IO
P4P5IO
P6P7IO
P8P9
8/16
R/W
0020
0021
0022
0023
0024
0025✩
0026✩
0027
P9
P10
P10P11
TRNSCON
P11
—
16
8
F000
TRNS Control Register
—
TRNSIT
WDT
—
—
C0
Transition Detector
Watchdog Timer
Stop
W
✩ mark in the address column indicates that there is a nonexistent bit in its register.
9/27
¡ Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Abbreviated Abbreviated
Name (BYTE) Name (WORD)
8/16
Operation
Reset
Status
Address [H]
Name
R/W
0028
0029
002A
002B
002C✩
002D✩
002E
002F
Port 8 Mode Register
P8IO
00
00
00
00
C0
F0
P8P9IO
P9IO
Port 9 Mode Register
8/16
Port 10 Mode Register
P10IO
P10P11IO
P11IO
Port 11 Mode Register
R/W
A/D Interrupt Control Register
A/D Hardware Select Enable Register
ADINTCON
ADHENCON
—
—
—
8
A/D Hardware Select Register
ADHSEL
16
0000
—
0030
0031
0032✩
0033
0034
0035✩
0036
0037
0038✩
0039✩
003A✩
003B
003C
003D
003E
003F
Port 1 Secondary Function Control Register
Port 2 Secondary Function Control Register
Port 3 Secondary Function Control Register
Port 4 Secondary Function Control Register
Port 5 Secondary Function Control Register
Port 6 Secondary Function Control Register
Port 7 Secondary Function Control Register
Port 8 Secondary Function Control Register
Port 9 Secondary Function Control Register
Port 10 Secondary Function Control Register
P1SF
P2SF
P3SF
P4SF
P5SF
P6SF
P7SF
P8SF
P9SF
P10SF
—
—
—
—
—
—
—
—
—
-—
00
80
00
00
CF
00
00
F0
00
00
R/W
8
IRQD0L
IRQD0H
IRQD1L
IRQD1H
IRQ0L
IRQ0H
IRQ1L
IRQ1H
IE0L
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Interrupt Request Flag
Disable Register 0
IRQD0
IRQD1
IRQ0
IRQ1
IE0
Interrupt Request Flag
Disable Register1
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
004A
004B
004C
004D
004E
004F
Interrupt Request Register 0
Interrupt Request Register 1
Interrupt Enable Register 0
Interrupt Enable Register 1
8/16
R/W
IE0H
IE1L
IE1
IE1H
Interrupt Priority Control
Register 00
IP00L
IP00H
IP01L
IP01H
IP10L
IP10H
IP11L
IP11H
IP00
IP01
IP10
IP11
Interrupt Priority Control
Register 01
Interrupt Priority Control
Register 10
Interrupt Priority Control
Register 11
✩ mark in the address column indicates that there is a nonexistent bit in its register.
10/27
¡ Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Abbreviated Abbreviated
Name (BYTE) Name (WORD)
8/16
Operation
Reset
Status
Address [H]
Name
R/W
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005A
005B
005C
005D
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
006A
006B
006C
006D
006E
006F
0070
0071
0072
0073
0074
0075
0076
0077
PWM Counter 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PWC0
PWC1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
0000
0000
0000
0000
PWM Counter 1
PWM Counter 2
PWC2
PWM Counter 3
PWC3
R
PWM Counter 4
PWC4
PWM Counter 5
PWC5
PWM Counter 6
PWC6
PWM Counter 7
PWC7
PWC0 Buffer Register
PWC1 Buffer Register
PWC2 Buffer Register
PWC3 Buffer Register
PWC4 Buffer Register
PWC5 Buffer Register
PWC6 Buffer Register
PWC7 Buffer Register
PWR0 Buffer Register
PWR1 Buffer Register
PWR2 Buffer Register
PWR3 Buffer Register
PWC0BF
PWC1BF
PWC2BF
PWC3BF
PWC4BF
PWC5BF
PWC6BF
PWC7BF
PW0BF
PW1BF
PW2BF
PW3BF
16
R/W
✩ mark in the address column indicates that there is a nonexistent bit in its register.
11/27
¡ Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Abbreviated Abbreviated
Name (BYTE) Name (WORD)
8/16
Operation
Reset
Status
Address [H]
Name
R/W
0078
0079
007A
007B
007C
007D
007E
007F
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
008A
008B
008C
008D
008E
008F
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
009A
009B
009C
009D
009E
009F
PWR4 Buffer Register
PWR5 Buffer Register
PWR6 Buffer Register
PWR7 Buffer Register
Timer Register 0
Timer Register 1
Timer Register 2
Timer Register 3
Timer Register 4
Timer Register 5
Timer Register 6
Timer Register 7
Timer Register 8
Timer Register 9
Timer Register 10
Timer Register 11
Timer Register 12
Timer Register 13
Timer Register 14
Timer Register 15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PW4BF
PW5BF
PW6BF
PW7BF
TMR0
0000
0000
R/W
0000
0000
Undefined
Undefined
Undefined
Undefined
0000
TMR1
R
TMR2
TMR3
TMR4
TMR5
0000
16
TMR6
0000
TMR7
0000
TMR8
0000
TMR9
0000
R/W
TMR10
TMR11
TMR12
TMR13
TMR14
TMR15
0000
0000
0000
0000
0000
0000
✩ mark in the address column indicates that there is a nonexistent bit in its register.
12/27
¡ Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Abbreviated Abbreviated
Name (BYTE) Name (WORD)
8/16
Reset
Address [H]
Name
R/W
Operation Status
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
00A8
00A9
00AA
00AB
00AC
00AD
00AE
00AF
Timer Register 16
—
—
—
—
—
—
—
—
TMR16
TMR17
0000
Timer Register 17
0000
0000
TMR4 Buffer Register
TMR5 Buffer Register
TMR6 Buffer Register
TMR7 Buffer Register
TMR12 Buffer Register
TMR13 Buffer Register
TMR4BF
TMR5BF
TMR6BF
TMR7BF
TMR12BF
TMR13BF
0000
16
0000
0000
0000
0000
RTOCON0
RTOCON1
RTOCON2
RTOCON3
RTOCON4
RTOCON5
RTOCON6
RTOCON7
RTOCON8
RTOCON9
RTOCON10
RTOCON11
RTOCON12
RTOCON13
RTOCON14
TM0L
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F8
F8
F8
F8
FC
FC
F8
00B0✩ RTO Control Register 0
00B1✩ RTO Control Register 1
00B2✩ RTO Control Register 2
00B3✩ RTO Control Register 3
00B4✩ RTO Control Register 4
00B5✩ RTO Control Register 5
00B6✩ RTO Control Register 6
00B7✩ RTO Control Register 7
R/W
8
F8
00
F8
F8
F8
F8
F8
F8
1F
00B8
RTO Control Register 8
00B9✩ RTO Control Register 9
00BA✩ RTO Control Register 10
00BB✩ RTO Control Register 11
00BC✩ RTO Control Register 12
RTO Control Register 13
00BD✩
00BE✩ RTO Control Register 14
00BF✩ Timer Counter 0 Low-order 3 bits
00C0
—
—
TM0
TM1
0000
0000
Timer Counter 0
00C1
16
8
00C2
Timer Counter 1
00C3
TMR0L
TMR1L
TMR2L
TMR3L
—
—
—
—
Undefined
Undefined
Undefined
Undefined
00C4✩ TMR0 Low-order 3 Bits
TMR1 Low-order 3 Bits
TMR2 Low-order 3 Bits
TMR3 Low-order 3 Bits
00C5✩
00C6✩
00C7✩
R
✩ mark in the address column indicates that there is a nonexistent bit in its register.
13/27
¡ Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Abbreviated Abbreviated
Name (BYTE) Name (WORD)
8/16
Reset
Address [H]
Name
R/W
Operation Status
00C8✩ Event Dividing Counter 0
EVDV0
EVDV1
—
—
C0
C0
C0
00C9✩ Event Dividing Counter 1
00CA✩ Event Dividing Counter 2
00CB✩ Event Dividing Counter 3
00CC✩ EVDV0 Buffer Register
00CD✩ EVDV1 Buffer Register
00CE✩ EVDV2 Buffer Register
00CF✩ EVDV3 Buffer Register
EVDV2
—
EVDV3
—
C0
C0
C0
C0
C0
R/W
8
EVDV0BF
EVDV1BF
EVDV2BF
EVDV3BF
ADCR0
—
—
—
—
00D0
00D1
00D2
00D3
00D4
00D5
00D6
00D7
00D8
00D9
00DA
00DB
00DC
00DD
00DE
00DF
A/D Result Register 0
A/D Result Register 1
A/D Result Register 2
A/D Result Register 3
A/D Result Register 4
A/D Result Register 5
A/D Result Register 6
A/D Result Register 7
A/D Result Register 8
A/D Result Register 9
A/D Result Register 10
A/D Result Register 11
A/D Result Register 12
A/D Result Register 13
A/D Result Register 14
A/D Result Register 15
ADCR0W
ADCR1W
ADCR2W
ADCR3W
ADCR4W
ADCR5W
ADCR6W
ADCR7W
ADCR8W
ADCR9W
ADCR10W
ADCR11W
ADCR12W
ADCR13W
ADCR14W
ADCR15W
—
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
R/W
(*1)
8/16
(*1)
Undefined
ADCR8
ADCR9
ADCR10
ADCR11
ADCR12
ADCR13
ADCR14
ADCR15
ADCONL
ADCONH
TMCON
TMSEL2
80
80
00
C0
00E0✩ A/D Control Register L
00E1✩ A/D Control Register H
—
8
—
00E2
Timer Control Register
—
00E3✩ TM Setting Register 2
00E4
16
8
—
TMSEL
0000
TM Setting Register
00E5✩
TMRMODE
—
—
00
C0
00E6
TMR Mode Register
TMRMODE2
00E7✩ TMR Mode Register 2
R/W
00E8
—
CAPCON
16
0000
Capture Control Register
00E9✩
CAPCON2
PWRUN
—
—
—
—
—
—
00
00
00
00
00
00
00EA
00EB
00EC
00ED
00EE
00EF
Capture Control Register 2
PWM RUN Register
PWCON0
PWCON1
PWCON2
PWCON3
PWM Control Register 0
PWM Control Register 1
PWM Control Register 2
PWM Control Register 3
8
✩ mark in the address column indicates that there is a nonexistent bit in its register.
14/27
¡ Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Abbreviated Abbreviated
Name (BYTE) Name (WORD)
8/16
Reset
Address [H]
Name
R/W
Operation Status
00F0
00F1
00F2
00F3
00F4
00F5
00F6
00F7
00F8✩
00F9
00FA
00FB
00FC✩
00FD✩
00FE
00FF
PWM Interrupt Register 0
PWINTQ0
PWINTQ
PWINTQ1
00
PWM Interrupt Register 1
00
8/16
00
PWM Interrupt Enable Register 0
PWM Interrupt Enable Register 1
SCI0 Transmit/Receive Buffer Register
SCI0 Status Register
PWINTE0
PWINTE
PWINTE1
00
Undefined
00
S0BUF
S0STAT
S1BUF
—
—
—
—
—
—
—
—
—
—
SCI1 Transmit/Receive Buffer Register
SCI1 Status Register
R/W
Undefined
00
S1STAT
GTMCON
GEVC
General-purpose 8-bit Timer Control Register
8-bit Event Counter
30
8
00
General-purpose 8-bit Timer Counter
General-purpose 8-bit Timer Register
GTMC
00
00
88
88
GTMR
EVNTCONL
EVNTCONH
Event Control Register
Emulator Use Area
* Note 3
0100
Memory Size Acceptor
MEMSACP
MEMSCON
—
—
"0"
W
8
0101✩ Memory Size Control Register
FC
R/W
0102
0103
0104
0105
0106
0107✩ Peripheral Control Register
PRPHF
NMICON
EXICON
—
—
—
(*3)
R/W
0108✩ NMI Control Register
FC or 7C
00
8
0109✩ External Interrupt Control Register
010A
010B
010C
010D
010E
010F
0110
SCI0 Timer
0111
—
S0TM
0000
16
8
R/W
SCI0 Timer Control Register
SCI0 Transmit Control Register
SCI0 Receive Control Register
S0CON
ST0CON
SR0CON
—
—
—
02
8A
1A
0112✩
0113✩
0114✩
0115
0116
0117
15/27
¡ Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Abbreviated Abbreviated
Name (BYTE) Name (WORD)
8/16
Reset
Address [H]
Name
R/W
Operation Status
0118
—
S1TM
0000
SCI1 Timer
16
8
0119
R/W
S1CON
ST1CON
SR1C0N
—
—
—
02
88
08
SCI1 Timer Control Register
SCI1 Transmit Control Register
SCI1 Receive Control Register
011A✩
011B✩
011C✩
011D
011E✩
011F✩
0120
R
TBCKDVC
TBCKDVR
—
—
F0
F0
TBC Clock Dividing Counter
TBC Clock Dividing Register
8
R/W
0121
0122
0123
0124
0125
0126
0127
✩ mark in the address column indicates that there is a nonexistent bit in its register.
*1 The 8/16 bit operation for the ADCR items is a special word manipulation. If a byte access is made, high-order 8 bits of
the A/D Result register are accessed, and if a word access is made, the 10-bit contents of the A/D Result register are
accessed.
Data can be written in the even number A/D Result registers and the odd number A/D Result registers separately.
When data is first written in the A/D Result register 0 (ADCR0), data is also written in other even number A/D Result
registers at a time. When data is first written in the A/D Result register 1 (ADCR1), data is also written in other odd A/D
Result registers at a time.
*2 Do not access the emulator use area.
*3 The initial values of PRPHF (SFR=107H) are as follows:
At reset by RES pin: VBFF (bit 6) is "1"; CKOUT1 (bit 1) and CKOUT0 (bit 0) are "0".
At reset by WDT and BRK instructions and operation code trap: VBFF (bit 6) holds the value just before reset; CKOUT1
(bit 1) and CKOUT0 (bit 0) are "0".
In both cases, the OE pin status is read for OERD (bit 7).
16/27
¡ Semiconductor
MSM66589/66P589/66Q589
ADDRESSING MODES
The MSM66589/66P589/66Q589 provides independent 64K-byte data and 128K-byte program
spaces with various types of addressing modes. These modes are shown below for both RAM
(for data space) and ROM (for program space).
RAM Addressing Mode (for data space)
• Register addressing
Example
INC USP
USP
• Page addressing
a) sfr page
Example
0000H
0040H
L A, sfr IRQ0
SFR
b) Fixed page
Example
Example
Example
0200H
02C0H
ST A, fix 0C0H
RAM
c) Current page
xx00H
xx78H
ROR off 078H
RAM
• Direct data addressing
0700H
0780H
CLR dir 780H
RAM
17/27
¡ Semiconductor
MSM66589/66P589/66Q589
• Pointing register indirect addressing
a) DP/X1 indirect
Example
XCHG A, [DP]
DP
RAM
b) Post increment DP indirect
Example
ADD A, [DP+]
DP
RAM
After access, DP is incremented by 2.
c) Post decrement DP indirect
Example
SUB A, [DP-]
DP
RAM
RAM
RAM
After access, DP is decremented by 2.
d) DP/USP indirect with 7-bit displacement
Example
AND A, 12[DP]
DP
–64 to +63
e) X1/X2 indirect with 16-bit base
Example
XOR A, 1234H[X1]
X1
0-65535
f) X1 indirect with 8-bit register (A, R0) displacement
Example
OR A, [X1+A]
RAM
AL
X1
18/27
¡ Semiconductor
MSM66589/66P589/66Q589
• Special bit area addressing
a) Fixed page SBA area (02C0H to 02FFH)
Example
02C0H
RAM
SB sbafix 2D1H.3
02D1H
b) Current page SBA area (¥¥C0H to ¥¥FFH)
Example
¥¥C0H
RB sbaoff 2E9H.7
RAM
¥¥E9H
ROM Addressing Mode (for program space)
• Immediate addressing
Example
MOV SSP, #7FFH
ROM
Address
xxxxH
• Table data addressing
TSR specifies the address segment.
a) Direct
Example
LC A, 5678H
ROM
5678H
b) RAM addressing indirect
Example
CMPC A, [USP]
ROM
USP
c) RAM addressing indirect with 16-bit base
Example
LC A, 1234H[ER0]
0-65535
ROM
RAM
ER0
19/27
¡ Semiconductor
MSM66589/66P589/66Q589
MEMORY MAP
Program Memory Space
Segment 0
0000H
Segment 1
0000H
Vector table area
(74 bytes)
0049H
004AH
VCAL table area
Internal
ROM area
Internal
ROM area
(32 bytes)
0069H
006AH
0FFFH
1000H
0FFFH
1000H
ACAL area
(2K bytes)
ACAL area
(2K bytes)
17FFH
1800H
17FFH
1800H
7FFFH
8000H
External
ROM area *
FFFFH
FFFFH
*
For MSM66Q589 (Flash EEPROM version), 8000H to 0FFFFH in Segment 1 are in the internal
ROM area.
Data Memory Space
0000H
SFR Area
00FFH
0100H
01FFH
0200H
02FFH
0300H
Expanded
SFR Area
Expanded SFR Area
01FFH
0200H
X1
FIX Area
X2
Internal RAM Area
SCB=0
SCB=1
DP
USP
X1
Area where
local
0208H
0210H
X2
DP
USP
X1
Pointing
Register Set
register
can be set
09FFH
0A00H
USP
X1
0238H
0240H
11FFH
1200H
X2
SCB=7
DP
USP
External Memory Area
02C0H
0300H
Area where SB, RB,
JBS, and JBR
instructions can be
performed in shorter
byte count.
Area where ROM
window can be set
SBA Area
(64 bytes)
FFFFH
20/27
¡ Semiconductor
MSM66589/66P589/66Q589
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
Parameter
Digital Power Supply Voltage
Input Voltage
Symbol
VDD
Condition
Rating
Unit
–0.3 to 7.0
VI
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to AVDD+0.3
–0.3 to VREF
Output Voltage
GND=AGND=0 V
Ta = 25°C
VO
V
Analog Power Supply Voltage
Analog Reference Voltage
Analog Input Voltage
AVDD
VREF
VAI
Per package
Per output
—
855
50
–50 to +150
Ta=85°C
Power Dissipation
PD
mW
°C
Storage Temperature
TSTG
RECOMMENDED OPERATING CONDITIONS
Parameter
Digital Power Supply Voltage
Analog Power Supply Voltage
Analog Reference Voltage
Analog Input Voltage
Symbol
VDD
Condition
Range
4.5 to 5.5
4.5 to 5.5
AVDD–0.3 to AVDD
AGND to VREF
2.0 to 5.5
0 to 20
Unit
fOSC£20 MHz
VDD=AVDD
—
AVDD
VREF
VAI
V
—
Memory Hold Voltage
fOSC=0 Hz
VDDH
fOSC
V
DD=5 V 10ꢀ
—
Operating Frequency
MHz
°C
Ambient Temperature
–40 to +85
20
Ta
MOS load
2
Fan Out
P0, P5_4, P5_5, P7_0, P7_1
P1 to P11 (except P5_4,P5_5, P7_0, P7_1)
—
N
TTL load
1
21/27
¡ Semiconductor
MSM66589/66P589/66Q589
ELECTRICAL CHARACTERISTICS
DC Characteristics (Preliminary)
(VDD=5 V 10ꢀ, Ta=–40 to +85˚C)
Typ.
–
Unit
Min.
Max.
VDD+0.3
VDD+0.3
0.8
Parameter
Symbol
Condition
H Level Input Voltage
2.2
1
VIH
–
–
2, 4, 5, 6, 7
0.80VDD
H Level Input Voltage
–
L Level Input Voltage
L Level Input Voltage 2, 4, 5, 6, 7
1
–0.3
–
VIL
VOH
VOL
–
–0.3
0.2VDD
–
V
–
I
OH=–400 mA
H Level Output Voltage
H Level Output Voltage
L Level Output Voltage
L Level Output Voltage
Input Leakage Current
Input Current
1, 4
2
VDD–0.4
–
–
IOH=–200 mA
VDD–0.4
–
–
–
IOL=3.2 mA
1, 4
2
0.4
–
IOL=1.6 mA
0.4
–
–
3, 6
5
1/–1
–
–
µA
VI=VDD/0 V
1/–250
IIH/IIL
–
–
Input Current
15/–15
7
–
–
–
–
–
2
–
–
H Level Output Current
H Level Output Current
L Level Output Current
L Level Output Current
1, 4
2
–2
–1
10
5
IOH
IOL
–
mA
VO=2.4 V
–
1, 4
2
–
–
–
Output Leakage Current 1, 2, 4
Input Capacitance
VO=VDD/0 V
ILO
CI
µA
pF
–
5
f=1 MHz, Ta=25˚C
–
Output Capacitance
CO
7
–
–
6
mA
µA
A/D in operation
A/D stopped
Analog Reference Current
IREF
–
–
10
–
VDD=2 V, Ta=25˚C*
0.2
1
10
Current Consumption
(in STOP mode)
µA
IDDS
–
100
*
Current Consumption
(in HALT mode)
–
–
45
80
IDDH
IDD
f
OSC=20 MHz
No load
mA
Current Consumption
1. Applied to P0
2. Applied to P1 to P11 (except P5_4, P5_5, P7_0, P7_1)
3. Applied to A
IN
4. Applied to P5_4, P5_5, P7_0, P7_1
5. Applied to RES
6. Applied to EA, OE, NMI
7. Applied to OSC0
*
Ports for input pins are V
or GND, otherwise no load.
DD
22/27
¡ Semiconductor
MSM66589/66P589/66Q589
AC Characteristics (Preliminary)
• External program memory control
(VDD=5 V 10ꢀ% Ta=–40 to +85ꢁC)
Parameter
Clock (OSC) pulse width
ALE pulse width
Symbol
tøW
Condition
Min.
25
Max.
—
Unit
—
tAW
2tøW–10
2tøW–10
tøW–10
—
PSEN pulse width
tPW
—
PSEN pulse delay time
Low-order address set-up time
Low-order address hold time
High-order address set-up time
High-order address hold time
Instruction set-up time
Instruction hold time
tPAD
tALS
tALH
tAHS
tAPH
tIS
tøW+10
2tøW–10 2tøW+10
tøW–10 tøW+10
nsec
CL=50 pF
3tøW–10 3tøW+10
tøW+10
—
tIH
tøW–10
• External data memory control
(VDD=5 V 10ꢀ% Ta=–40 to +85ꢁC)
Parameter
Clock (OSC) pulse width
ALE pulse width
Symbol
tøW
tAW
Condition
Min.
25
Max.
—
Unit
—
2tøW–10
2tøW–10
2tøW–10
tøW–10
tøW–10
—
RD pulse width
WR pulse width
tRW
tWW
tRAD
tWAD
tALS
tALH
tAHS
tAHH
tMS
—
—
RD pulse delay time
tøW+10
tøW+10
WR pulse delay time
Low-order address set-up time
Low-order address hold time
High-order address set-up time
High-order address hold time
Memory data set-up time
Memory data hold time
Data set-up time
2tøW–10 2tøW+10
tøW–10 tøW+10
3tøW–10 3tøW+10
nsec
CL=50 pF
tøW–0
tøW+10
—
tMH
tDD
tøW–10
tALH+10
tøW+10
tALH–0
tøW–10
Data hold time
tDH
23/27
¡ Semiconductor
MSM66589/66P589/66Q589
CLK
ALE
t
t
øW
ø
W
tAW
PSEN
tPAD
tPW
AD 0-7
A 8-16
PC 0-7
tALS tALH
INST 0-7
tIS tIH
PC 8-16
tAHS
tAPH
RD
tRAD
tRW
AD 0-7
A 8-15
RAP 0-7
tALS tALH
DIN 0-7
tMS tMH
RAP 8-15
tAHH
tAHS
WR
tWAD
tWW
AD 0-7
RAP 0-7
tALS tALH
DOUT 0-7
tDH
tDD
A 8-15
RAP 8-15
tAHS
tAHH
24/27
¡ Semiconductor
MSM66589/66P589/66Q589
A/D CONVERTER CHARACTERISTICS (Preliminary)
(Ta=–40 to +85˚C, AVDD=VDD=VREF=5 V 10ꢀ, AGND=GND=0 V, fOSC=20 MHz)
Typ.
—
Unit
Min.
—
Max.
Parameter
Resolution
Symbol
Condition
n
10
Bit
Refer to the recommended
circuit.
—
Linearity Error
EL
—
Analog input source
impedance
—
ED
—
Differential Linearity Error
Zero Scale Error
Full Scale Error
Crosstalk
—
EZS
EFS
ECT
RI
£ 5 kW
LSB
t
CONV=19.2 msec
—
—
—
—
Refer to the measuring
circuit.
tCONV
–
19.2
6.4
µs/CH
Conversion Time
by ADTM set data
47 W
AVDD
0.1
µF
Reference
Voltage
+5 V
VREF
VDD
+
+
0.1 47
µF µF
0.1
µF
47
µF
RI
–
AI 0-15
+
Analog input
AGND
GND
0 V
0.1 µF
RI (Analog input source impedance)
£ 5 kW
Recommended Circuit
25/27
¡ Semiconductor
MSM66589/66P589/66Q589
Crosstalk is defined as the
difference between the A/D
conversion result when ap-
plying the identical analog
input to AI0 to AI15 and the A/D
conversion result in the circuit
in the left figure.
–
5 kW
AI0
AI1
+
Analog input
0.1mF
AI15
VREF or AGND
Crosstalk Measuring Circuit
Definitions of Terms
Resolution
10
The minimum distinguishable analog input value. For 10 bits, 2 =1024, i.e. (V –AGND)
REF
÷ 1024.
Linearity error
The variance between the ideal conversion characteristics as a 10-bit A/D converter and the
actual conversion characteristics. (Quantized error is therefore not included.)
In the ideal conversion, a voltage between V
and AGND is divided into 1,024 equal steps.
REF
Differential linearity error
The smoothness of the conversion. The width of analog input voltage corresponding to the
change by one bit of digital output is 1 LSB=(V –AGND) ÷ 1024 ideally. The variance
REF
between this ideal bit size and bit size at arbitrary point in the conversion range.
Zero scale error
The variance between the ideal conversion characteristics at the switching point of digital
output "000H to 001H" and actual conversion characteristics.
Full scale error
The variance between the ideal conversion characteristics at the switching point of digital
output "3FEH to 3FFH" and actual conversion characteristics.
26/27
¡ Semiconductor
MSM66589/66P589/66Q589
PACKAGE DIMENSIONS
(Unit : mm)
QFP128-P-2828-0.80-BK
QFP128-P-2828-0.80-ZK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
5.95 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
27/27
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