MSM7509BJS [OKI]
PCM Codec, A-Law, 1-Func, CMOS, PQCC28, 0.450 INCH, 1.27 MM PITCH, PLASTIC, QFJ-28;
| 型号： | MSM7509BJS |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | PCM Codec, A-Law, 1-Func, CMOS, PQCC28, 0.450 INCH, 1.27 MM PITCH, PLASTIC, QFJ-28 PC |
| 文件： | 总17页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0013-28-81
This version: Aug. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7508B/7509B
Single Rail CODEC
GENERAL DESCRIPTION
The MSM7508B and MSM7509B are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
optimized for telephone terminals in ISDN and digital wireless systems.
The MSM7508B/MSM7509B are the transmission-clocks extended versions of the MSM7508/
MSM7509. It is recommended to use the MSM7508/MSM7509 for the transmission clocks of 64,
128, 256kHz.
FEATURES
• Single power supply: +5 V ±5%
• Low power consumption
Operating mode:
Power down mode:
• ITU-T Companding law
17.5 mW Typ.
1.5 mW Typ.
37mW Max.
3mW Max.
MSM7508B:
MSM7509B:
m-law
A-law
• Built-in PLL eliminates a master clock
• Transmission clock: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
• Adjustable transmit gain
• Built-in reference voltage supply
• Package options:
16-pin plastic DIP (DIP16-P-300-2.54-W1)
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name : MSM7508BRS)
(Product name : MSM7509BRS)
(Product name : MSM7508BGS-K)
(Product name : MSM7509BGS-K)
28-pin plastic QFJ (PLCC) (QFJ28-P-S450-1.27) (Product name : MSM7508BJS)
(Product name : MSM7509BJS)
Note: The product names are indicated in PIN CONFIGURATION.
1/17
¡ Semiconductor
MSM7508B/7509B
BLOCK DIAGRAM
PCMOUT
XSYNC
+
–
AIN+
AIN–
RC
Active
AD
Conv.
Transmit
Controller
BPF
(8th)
BCLOCK
GSX
Auto
Zero
TPLL
RPLL
SGC
SG
Signal
Ground
Voltage
Ref.
DA
Conv.
Receive
Controller
LPF
(5th)
RSYNC
PCMIN
+
–
AOUT
PDN
PWD
Logic
PWD
VDD
AG
DG
2/17
¡ Semiconductor
MSM7508B/7509B
PIN CONFIGURATION (TOP VIEW)
SGC 1
SG 2
16 AIN+
15 AIN–
14 GSX
SGC 1
NC 2
24 AIN+
23 AIN–
22 NC
AOUT 3
SG 3
VDD
4
13 NC
NC 4
21 GSX
20 NC
DG 5
PDN 6
12 AG
AOUT 5
11 BCLOCK
10 XSYNC
9 PCMOUT
VDD
6
19 NC
RSYNC 7
PCMIN 8
DG 7
NC 8
18 AG
17 NC
NC 9
16 BCLOCK
15 NC
NC : No connect pin
PDN 10
RSYNC 11
PCMIN 12
16-Pin Plastic DIP
14 XSYNC
13 PCMOUT
NC : No connect pin
24-Pin Plastic SOP
VDD
5
25 NC
24 NC
23 NC
22 NC
21 NC
20 NC
19 AG
NC 6
NC 7
NC 8
NC 9
NC 10
DG 11
NC : No connect pin
28-Pin Plastic QFJ (PLCC)
3/17
¡ Semiconductor
MSM7508B/7509B
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is in a high impedance state.
1) Inverting input type
R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)
GSX
AIN–
AIN+
SG
C1
R2
–
+
Analog input
R1
Gain = R2/R1 £ 10
2) Non inverting input type
C2
R3 > 20 kW
AIN+
AIN–
GSX
+
–
Analog input
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)
R5
R4
R3
SG
Gain = 1 + R4 / R3 £ 10
AG
Analog signal ground.
AOUT
Analog output.
Theoutputsignalamplitudeisamaximumof2.4V aboveandbelowthesignalgroundvoltage
PP
level (V /2).
DD
The output load resistance is a minimum of 20 kW.
During power saving or power down mode, the output of AOUT is at the voltage level of signal
ground.
4/17
¡ Semiconductor
MSM7508B/7509B
V
DD
Power supply for +5 V.
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLOCK signal.
The data rate of the PCM signal is equal to the frequency of the BCLOCK signal.
The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLOCK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee
the AC characteristics which are mainly frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are
not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to
the power saving state.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLOCK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.
5/17
¡ Semiconductor
MSM7508B/7509B
DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.
PDN
Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.
PCMOUT
PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLOCK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between
BCLOCK and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down modes.
Apull-upresistormustbeconnectedtothispinbecauseitsoutputisconfiguredasanopendrain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7509B (A-law) outputs the character signal, inverting the even bits.
PCMIN/PCMOUT
Input/Output Level
MSM7508B (m-law)
MSM7509B (A-law)
MSD
MSD
+Full scale
+0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
–0
–Full scale
SG
Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is ±300 mA.
This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down modes.
SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
6/17
¡ Semiconductor
MSM7508B/7509B
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
Rating
Unit
V
—
—
—
—
0 to 7
VAIN
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–55 to +150
V
VDIN
TSTG
V
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Analog Input Voltage
Symbol
VDD Voltage must be fixed
Ta
Condition
Min.
Typ.
5.0
Max.
Unit
V
4.75
–10
—
5.25
+70
2.4
+25
—
—
°C
VAIN Connect AIN– and GSX
VPP
Input High Voltage
Input Low Voltage
VIH
2.2
0
—
—
VDD
0.8
V
V
XSYNC, RSYNC, BCLOCK,
PCMIN, PDN
VIL
64, 128, 256, 512, 1024,
2048, 96, 192, 384, 768,
1536, 1544, 200
Clock Frequency
FC
BCLOCK
kHz
Sync Pulse Frequency
Clock Duty Ratio
FS
DC
tIr
XSYNC, RSYNC
7.0
40
8.0
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10.0
60
kHz
%
BCLOCK
Digital Input Rise Time
Digital Input Fall Time
XSYNC, RSYNC, BCLOCK,
PCMIN, PDN
—
50
ns
tIf
—
50
ns
tXS
tSX
tRS
tSR
BCLOCKÆXSYNC, See Timing Diagram
XSYNCÆBCLOCK, See Timing Diagram
BCLOCKÆRSYNC, See Timing Diagram
RSYNCÆBCLOCK, See Timing Diagram
100
100
100
100
1 BCLK
100
100
20
—
ns
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
—
ns
—
ns
—
ns
Sync Pulse Width
PCMIN Set-up Time
PCMIN Hold Time
tWS XSYNC, RSYNC
100
—
ms
ns
tDS
tDH
—
—
—
ns
AOUT
GSX
—
kW
kW
pF
RAL
Analog Output Load
Digital Output Load
20
—
CAL AOUT, GSX
RDL Pull-up resistor
—
100
—
0.5
kW
pF
CDL
Voff
—
—
—
100
+100
+10
500
Transmit gain stage, Gain = 1
Transmit gain stage, Gain = 10
XSYNC, RSYNC, BCLOCK
–100
–10
—
mV
mV
ns
Analog Input Allowable DC Offset
Allowable Jitter Width
7/17
¡ Semiconductor
MSM7508B/7509B
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = +5 V 5%, Ta = –10°C to +70°C)
Parameter
Symbol
Condition
Min.
—
Typ.
3.5
Max.
7.0
Unit
mA
IDD1 Operating mode
IDD2 Power-down mode, PDN = 0
—
0.3
0.5
mA
Power Supply Current
Power-save mode, PDN = 1,
IDD3
—
2.2
0.0
0.8
—
—
1.2
VDD
0.8
mA
V
SYNC Æ OFF
Input High Voltage
Input Low Voltage
VIH
VIL
—
—
V
High Level Input Leakage Current
Low Level Input Leakage Current
Digital Output Low Voltage
Digital Output Leakage Current
Analog Output Offset Veltage
Input Capacitance
IIH
IIL
—
—
—
—
—
—
0.2
—
—
5
2.0
0.5
0.4
10
mA
mA
V
VOL Pull-up resistance > 500 W
IO
VOFF AOUT with respect to SG
0.0
—
—
mA
mV
pF
–100
—
+100
—
CIN
—
Analog Input Resistance
RIN AIN+, AIN–
—
10
—
MW
8/17
¡ Semiconductor
AC Characteristics
Parameter
MSM7508B/7509B
(VDD = +5 V 5%, Ta = –10°C to +70°C)
Freq.
(Hz)
Level
(dBm0)
Symbol
Condition Min.
Typ.
Max.
Unit
Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
LossR1
LossR2
LossR3
LossR4
LossR5
SD T1
SD T2
SD T3
60
300
20
26
+0.07
Reference
–0.04
+0.06
0.40
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
–0.15
+0.20
1020
2020
3000
3400
300
Transmit Frequency Response
Receive Frequency Response
0
0
–0.15
–0.15
0
+0.20
+0.20
0.80
–0.15
–0.03
Reference
–0.02
+0.15
0.56
+0.20
1020
2020
3000
3400
–0.15
–0.15
0.0
+0.20
+0.20
0.80
—
3
0
35
43
35
41
—
–30
35
38
—
Transmit Signal to Distortion Ratio
1020
30.0
dB
SD T4
SD T5
–40
–45
28
*1
—
—
29.5
25.0
*2
23
24.5
SD R1
SD R2
SD R3
3
0
36
36
36
43
—
—
—
41
–30
40
Receive Signal to Distortion Ratio
1020
dB
33.5
SD R4
SD R5
–40
–45
30
*1
—
32
25
30
*2
—
24
27
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
3
–0.2
+0.01
Reference
0.0
+0.2
–10
–40
–50
–55
3
Transmit Gain Tracking
1020
1020
–0.2
–0.4
–1.2
–0.2
+0.2
+0.4
+1.2
+0.2
dB
dB
–0.03
+0.15
0
–10
–40
–50
–55
Reference
–0.06
–0.20
–0.27
Receive Gain Tracking
–0.2
–0.4
–0.8
+0.2
+0.4
+0.8
*1 Psophometric filter is used
*2 Upper is specified for the MSM7508B, lower for the MSM7509B
9/17
¡ Semiconductor
MSM7508B/7509B
AC Characteristics (Continued)
(VDD = +5 V 5%, Ta = –10°C to +70°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
Unit
AIN = SG
—
–72.5
–70.5
–76.5
–70
–69
–74
Nidle T
—
—
—
—
Idle Channel Noise
*1
*2
*2
*3
dBmOp
NidleR
AV T
—
0.5671 0.6007 0.6363
0.5671 0.6007 0.6363
Absolute Level (Initial Difference)
Absolute Delay
Vrms
ms
1020
1020
0
0
AV R
Td
A to A
BCLOCK
= 64 kHz
—
—
0.60
tgd T1
tgd T2
tgd T3
tgd T4
tgd T5
tgdR1
tgdR2
tgdR3
tgdR4
tgdR5
CR T
500
600
*4
—
—
—
—
—
—
—
—
—
—
75
70
0.19
0.11
0.02
0.05
0.07
0.00
0.00
0.00
0.09
0.12
85
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
—
Transmit Group Delay
Receive Group Delay
1000
2600
2800
500
0
ms
*4
600
1000
2600
2800
0
0
ms
dB
TRANS Æ RECV
RECV Æ TRANS
Crosstalk Attenuation
1020
CR R
77
—
*1 Psophometric filter is used
*2 Upper is specified for the MSM7508B, lower for the MSM7509B
*3 MSM7508B: All "0" code to PCMIN, MSM7509B: "11010101" to PCMIN
*4 Minimum value of the group delay distortion
10/17
¡ Semiconductor
MSM7508B/7509B
AC Characteristics (Continued)
(VDD = +5 V 5%, Ta = –10°C to +70°C)
Freq.
(Hz)
4.6 kHz to
72 kHz
300 to
Level
(dBm0)
Parameter
Discrimination
Symbol
Condition Min.
Typ.
32
Max.
—
Unit
dB
0 to
DIS
S
0
0
30
4000 Hz
4.6 kHz to
—
Out-of-band Spurious
–37.5
–52
30
–35
–35
—
dBmO
dBmO
dB
3400
100 kHz
fa = 470
fb = 320
Intermodulation Distortion
Power Supply Noise Rejection Ratio
IMD
–4
2fa – fb
*5
—
—
PSR T 0 kHz to
PSR R 50 kHz
50 mVPP
t
50
50
50
50
—
—
—
—
200
200
200
200
SD
t
XD1
XD2
XD3
Digital Output Delay Time
CL = 100 pF + 1 LSTTL
ns
t
t
*5 The measurement under idle channel noise
11/17
¡ Semiconductor
MSM7508B/7509B
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing
BCLOCK
XSYNC
1
2
3
4
5
6
7
8
9
10
11
tXS
tSX
tWS
tXD1
tSD
MSD
tXD2
D3
tXD3
D8
PCMOUT
D2
D4
D5
D6
D7
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1
When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD
.
.
Receive Timing
BCLOCK
tRS
1
2
3
4
5
6
7
8
9
10
11
tSR
tWS
RSYNC
tDS
tDH
PCMIN
MSD
D2
D3
D4
D5
D6
D7
D8
12/17
¡ Semiconductor
MSM7508B/7509B
APPLICATION CIRCUIT
1 kW
MSM7508B/7509B
+5 V Digital interface
Analog input
AIN–
GSX
PCMOUT
PCM signal output
AOUT
PCMIN
Analog output
PCM data input
AIN+
SG
BCLOCK
PCM shift clock input
0.1 mF
XSYNC
RSYNC
PDN
8 kHz SYNC signal input
Power Down control input
SGC
AG
DG
0 V
–
+
10 mF 1 mF
"1" = Operation
"0" = Power down
+5 V
VDD
0 to 20W
The analog output signal has an amplitude of ±1.2 V above and below the offset voltage level of
/2.
V
DD
13/17
¡ Semiconductor
MSM7508B/7509B
RECOMMENDATIONS FOR ACTUAL DESIGN
• Toassureproperelectricalcharacteristics,usebypasscapacitorswithexcellenthighfrequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.
• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-
DD
up phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
powersupplytoavoiderroneousoperationandthedegradationofthecharacteristicsofthese
devices.
14/17
¡ Semiconductor
PACKAGE DIMENSIONS
DIP16-P-300-2.54-W1
MSM7508B/7509B
(Unit : mm)
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
1.00 TYP.
15/17
¡ Semiconductor
MSM7508B/7509B
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/17
¡ Semiconductor
MSM7508B/7509B
(Unit : mm)
QFJ28-P-S450-1.27
Spherical surface
Package material
Epoxy resin
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Cu alloy
Solder plating
5 mm or more
1.00 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/17
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