MSM7541 [OKI]
Single Rail CODEC; 单铁CODEC
| 型号： | MSM7541 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Single Rail CODEC |
| 文件： | 总20页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0014-28-81
This version: Aug. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7541/7542
Single Rail CODEC
GENERAL DESCRIPTION
The MSM7541 and MSM7542 are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
optimized for telephone terminals in digital wireless systems.
The MSM7541 and MSM7542 use newly designed operational amplifiers to maintain small
current deviations caused by power voltage fluctuations.
The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal, which is of a differential type, directly drives a piezoelectric type
handset receiver.
FEATURES
• Single power supply: +3.0 V to +3.8 V
• Low power consumption
Operating mode:
Power save mode:
Power down mode:
23 mW Typ.
1 mW Typ.
0.04 mW Typ.
V
DD
V
DD
V
DD
= 3.3 V
= 3.3 V
= 3.3 V
• ITU-T Companding law
MSM7541:
MSM7542:
m-law
A-law
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Built-in analog loop back test mode
• Differential type analog output. Directly drives a piezoelectric type receiver equivalent to 1.2
kW + 55 nF
• Package options:
20-pin plastic skinny DIP (DIP20-P-300-2.54-S1) (Product name : MSM7541RS)
(Product name : MSM7542RS)
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name : MSM7541GS-K)
(Product name : MSM7542GS-K)
26-pin plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product name : MSM7541TS-K)
(Product name : MSM7542TS-K)
1/20
¡ Semiconductor
MSM7541/7542
BLOCK DIAGRAM
+
–
AIN+
AIN–
PCMOUT
XSYNC
RC
Active
BPF
(8th)
AD
Conv.
Transmit
Controller
BCLOCK
Auto
Zero
GSX
TMC
PLL
R–TIM
–
+
VFRO
LPF
(5th)
DA
Conv.
Receive
Controller
RSYNC
PCMIN
SG
SG
PDN
PWD
Logic
Power
Down
PWI
VDD
–
+
AG
AOUT–
DG
SG
SG
SG
–
+
SGC
SG
Voltage
Ref.
Signal
Ground
AOUT+
2/20
¡ Semiconductor
MSM7541/7542
PIN CONFIGURATION (TOP VIEW)
SG
AOUT+
AOUT–
PWI
1
2
3
4
5
6
7
8
9
20 SGC
19 AIN+
18 AIN–
17 GSX
16 TMC
SG
AOUT+
AOUT–
NC
1
2
3
4
5
6
7
8
9
24 SGC
SG
1
2
3
4
5
26 SGC
25 AIN+
24 AIN–
23 GSX
22 TMC
23 AIN+ AOUT+
22 AIN– AOUT–
21 GSX
20 NC
PWI
PWI
VFRO
VFRO
NC
19 TMC
18 NC
VFRO
VDD
VDD
17 NC
VDD
9
18 NC
15
NC
DG
16 AG
DG 10
PDN 11
17 AG
PDN 10
15 BCLOCK
14 XSYNC
DG
14 AG
16 BCLOCK
15 XSYNC
14 PCMOUT
RSYNC 11
RSYNC 12
PDN
13 BCLOCK PCMIN 12
13 PCMOUT
PCMIN 13
NC : No connect pin
24-Pin Plastic SOP
RSYNC
12 XSYNC
NC : No connect pin
26-Pin Plastic TSOP
PCMIN 10
11 PCMOUT
NC : No connect pin
20-Pin Plastic Skinny DIP
3/20
¡ Semiconductor
MSM7541/7542
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.
1) Inverting input type
R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)
GSX
AIN–
AIN+
SG
C1
R2
–
+
Analog input
R1
Gain = R2/R1 £ 10
2) Non inverting input type
C2
R3 > 20 kW
AIN+
AIN–
GSX
+
–
Analog input
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)
R5
R4
R3
SG
Gain = 1 + R4 / R3 £ 10
AG
Analog signal ground.
VFRO
Receive filter output.
The output signal has an amplitude of 2.0 V above and below the signal ground voltage (SG)
PP
when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of 20 kW or less, the output signal of AOUT+ and AOUT– is available.
ToapplytheoutputsignalofAOUT+andAOUT–fordriving, connectaresistorof20kWormore
between the pins VFRO and PWI.
Whenaddingthefrequencycharacteristicstothereceivesignal, refertotheapplicationexample.
During power saving or power down mode, the output of VFRO is at the voltage level of AG.
4/20
¡ Semiconductor
MSM7541/7542
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver. The receive driver output is
connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO,
PWI, and AOUT–. When the PWI pin is not used, connect the PWI pin to the AOUT– pin, and
leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the
output of AOUT–. Since the signal from which provides differential drives of an impedance of
1.2 kW + 55 nF, these outputs can directly be connected to a receiver of handset using a
piezoelectric earphone. Refer to the application example.
VI
R6
R6 > 20 kW
ZL ≥ 2.4 kW
VFRO
PWI
Receive Filter
–
R7
Gain = VO/VI = 2 ¥ R7/R6 £ 2
AOUT–
+
SG
VO
ZL
–
+
AOUT+
SG
During power saving and power down modes, the outputs of AOUT+ and AOUT– are in a high
impedance state.
The electrical driving capability of the AOUT– pin and AOUT+ pin is ±1.3 V maximum. The
output load resistor has a minimum value of 1.2 kW.
If an output amplitude less than ±1.3 V is allowed, these outputs can drive a load resistance less
than that described above.
For more details, refer to SINGLE POWER SUPPLY PCM CODEC APPLICATION NOTE.
V
DD
Power supply for +3.0 V to +3.8 V. (Typically 3.3 V)
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLOCK signal.
The data rate of the PCM signal is equal to the frequency of the BCLOCK signal.
The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLOCK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.
5/20
¡ Semiconductor
MSM7541/7542
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee
the AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLOCK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.
TMC
Control signal input for mode selection.
This pin select the normal operating mode or the analog loop-back mode.
In the analog loop-back mode, the receive filter output is connected to the transmit filter input
and the digital signal input to the PCMIN pin is converted from a digital to an analog signal (D/
A conversion). Next, the analog signal is converted to a digital signal (A/D conversion) through
the receive filter and transmit filter. The result is output to the PCMOUT pin.
When in the analog loop-back mode, the VFRO pin outputs the SG level. (signal ground)
TMC Input
< 0.16 ¥ VDD
> 0.45 ¥ VDD
Mode
Normal operation
Analog loop-back
6/20
¡ Semiconductor
MSM7541/7542
DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.
PDN
Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.
PCMOUT
PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLOCK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between
BCLOCK and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down modes.
Apull-upresistormustbeconnectedtothispinbecauseitsoutputisconfiguredasanopendrain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7542(A-law) outputs the character signal, inverting the even bits.
PCMIN/PCMOUT
Input/Output Level
MSM7541 (m-law)
MSM7542 (A-law)
MSD
MSD
+Full scale
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
+0
–0
–Full scale
7/20
¡ Semiconductor
MSM7541/7542
SG
Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is ±200 mA.
This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down modes.
SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
8/20
¡ Semiconductor
MSM7541/7542
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
Rating
Unit
V
—
—
—
—
0 to 7
VAIN
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–55 to +150
V
VDIN
TSTG
V
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Analog Input Voltage
Symbol
VDD Voltage must be fixed
Ta
Condition
Min.
Typ.
3.3
Max.
Unit
V
3.0
–30
—
3.8
+85
1.4
—
+25
—
°C
VAIN Connect AIN– and GSX
VPP
Digital Input High Voltage
Digital Input Low Voltage
VIH
0.45 ¥ VDD
—
—
VDD
V
V
XSYNC, RSYNC, BCLOCK,
PCMIN, PDN, TMC
VIL
0
0.16 ¥ VDD
64, 128, 256, 512, 1024,
2048, 96, 192, 384, 768,
1536, 1544, 200
Clock Frequency
FC
BCLOCK
kHz
Sync Pulse Frequency
Clock Duty Ratio
FS
DC
tIr
XSYNC, RSYNC
6.0
40
8.0
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10.0
60
kHz
%
BCLOCK
Digital Input Rise Time
Digital Input Fall Time
XSYNC, RSYNC, BCLOCK,
PCMIN, PDN, TMC
—
50
ns
tIf
—
50
ns
tXS
tSX
tRS
tSR
BCLOCKÆXSYNC, See Timing Diagram
XSYNCÆBCLOCK, See Timing Diagram
BCLOCKÆRSYNC, See Timing Diagram
RSYNCÆBCLOCK, See Timing Diagram
100
100
100
100
1 BCLK
100
100
0.5
—
ns
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
—
ns
—
ns
—
ns
Sync Pulse Width
PCMIN Set-up Time
PCMIN Hold Time
tWS XSYNC, RSYNC
100
—
ms
ns
tDS
tDH
—
—
—
ns
RDL Pull-up resistor
—
kW
pF
Digital Output Load
CDL
Voff
—
—
—
100
+100
+10
500
Transmit gain stage, Gain = 1
Transmit gain stage, Gain = 10
XSYNC, RSYNC, BCLOCK
–100
–10
—
mV
mV
ns
Analog Input Allowable DC Offset
Allowable Jitter Width
9/20
¡ Semiconductor
MSM7541/7542
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 3.0 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Symbol
IDD1
Condition
Min.
—
Typ.
10.0
7.0
Max.
12.0
9.0
Unit
mA
V
DD = 3.8 V
Operating mode
IDD4
VDD = 3.3 V
—
mA
Power-save mode, PDN = 1,
Power Supply Current
IDD2 XSYNC or BCLOCK Æ OFF
—
0.3
1.0
mA
IDD3 Power-down mode, PDN = 0
—
0.45 ¥
VDD
5
50
mA
Input High Voltage
Input Low Voltage
VIH
VIL
—
—
—
VDD
V
0.16 ¥
VDD
2.0
0.0
—
V
High Level Input Leakage Current
Low Level Input Leakage Current
Digital Output Low Voltage
Digital Output Leakage Current
Input Capacitance
IIH
IIL
—
—
—
—
0.0
—
—
—
—
0.2
—
5
mA
mA
V
0.5
VOL Pull-up resistance > 500 W
0.4
IO
—
—
10
mA
pF
CIN
—
10/20
¡ Semiconductor
MSM7541/7542
Transmit Analog Interface Characteristics
(VDD = 3.0 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Input Resistance
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
MW
kW
pF
RINX AIN+, AIN–
Output Load Resistance
Output Load Capacitance
Output Amplitude
RLGX GSX with respect to SG
20
—
—
CLGX
VOGX
—
—
50
–0.7
–20
—
+0.7
+20
V
Offset Voltage
VOSGX
Gain = 1
—
mV
Receive Analog Interface Characteristics
(VDD = 3.0 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Input Resistance
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
MW
kW
RINPW PWI
RLVF VFRO with respect to SG
20
—
—
Output Load Resistance
Output Load Capacitance
AOUT+, AOUT– (each) with
RLAO
1.2
—
—
kW
respect to SG
CLVF VFRO
—
—
—
—
100
50
pF
pF
CLAO AOUT+, AOUT–
VFRO, RL = 20 kW with
VOVF
–1.0
—
+1.0
V
respect to SG
Output Amplitude
Offset Voltage
AOUT+, AOUT–, RL = 1.2 kW
VOAO
–1.3
–100
–100
—
—
—
+1.3
+100
+100
V
with respect to SG
VOSVF VFRO with respect to SG
mV
mV
AOUT+, AOUT–, Gain = 1 with
VOSAO
respect to SG
11/20
¡ Semiconductor
AC Characteristics
Parameter
MSM7541/7542
(VDD = 3.0 V to 3.8 V, Ta = –30°C to +85°C)
Freq.
(Hz)
Level
(dBm0)
Symbol
Condition Min.
Typ.
Max.
Unit
Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
LossR1
LossR2
LossR3
LossR4
LossR5
SD T1
SD T2
60
300
20
26
+0.1
Reference
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
–0.15
+0.20
1020
2020
3000
3400
300
Transmit Frequency Response
Receive Frequency Response
0
0
–0.15
–0.15
0
+0.20
+0.20
0.80
—
—
–0.15
—
+0.20
1020
2020
3000
3400
Reference
—
–0.15
–0.15
0.0
+0.20
+0.20
0.80
—
—
—
3
35
43
0
35
42
—
Transmit Signal to Distortion Ratio SD T3
1020
–30
–40
–45
3
35
39
—
dB
dB
dB
dB
SD T4
SD T5
SD R1
SD R2
28
30.5
25
—
*1
23
36
36
36
—
43
—
0
41
—
Receive Signal to Distortion Ratio SD R3 1020
–30
–40
–45
3
41
—
SD R4
SD R5
GT T1
GT T2
30
*1
33
—
24
27
—
–0.2
0
+0.2
–10
–40
–50
–55
3
Reference
–0.02
+0.2
+0.4
0
Transmit Gain Tracking
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
1020
1020
–0.2
–0.5
–1.2
–0.2
+0.2
+0.5
+1.2
+0.2
–10
–40
–50
–55
Reference
–0.06
–0.10
–0.20
Receive Gain Tracking
–0.2
–1.0
–1.5
+0.2
+1.0
+1.5
*1 Psophometric filter is used
12/20
¡ Semiconductor
MSM7541/7542
AC Characteristics (Continued)
(VDD = 3.0 V to 3.8 V, Ta = –30°C to +85°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
Unit
AIN = SG
—
Nidle T
—
—
—
—
–70
–68
Idle Channel Noise
*1
dBmOp
Nidle R
AV T
*1 *2
VDD = 3.3 V
Ta = 25°C
*3
—
–76
–74
0.338
0.35
0.362
Absolute Level (Initial Difference)
Vrms
AV R
AV Tt
0.483
–0.2
0.50
—
0.518
+0.2
1020
1020
0
VDD = +3 to
dB
dB
Absolute Level
3.8 V
(Deviation of Temperature and Power)
Ta = –30
AV Rt
Td
–0.2
—
—
—
+0.2
0.60
to +85°C
*3
A to A
Absolute Delay
0
0
BCLOCK
= 64 kHz
ms
ms
tgd T1
tgd T2
tgd T3
tgd T4
tgd T5
tgdR1
tgdR2
tgdR3
tgdR4
tgdR5
CR T
500
600
*4
—
—
—
—
—
—
—
—
—
—
75
65
0.19
0.11
0.02
0.05
0.07
0.00
0.00
0.00
0.09
0.12
85
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
—
Transmit Group Delay
1000
2600
2800
500
*4
600
Receive Group Delay
Crosstalk Attenuation
1000
2600
2800
0
0
ms
dB
TRANS Æ RECV
RECV Æ TRANS
1020
CR R
70
—
*1 Psophometric filter is used
*2 Input "0" code to PCMIN
*3 AVR is defined at VFRO output
*4 Minimum value of the group delay distortion
13/20
¡ Semiconductor
MSM7541/7542
AC Characteristics (Continued)
(VDD = 3.0 V to 3.8 V, Ta = –30°C to +85°C)
Freq.
(Hz)
4.6 kHz to
72 kHz
300 to
Level
(dBm0)
Parameter
Discrimination
Symbol
Condition Min.
Typ.
32
Max.
—
Unit
dB
0 to
DIS
S
0
0
30
4000 Hz
4.6 kHz to
—
Out-of-band Spurious
–37.5
–52
–35
–35
dBmO
dBmO
3400
100 kHz
fa = 470
fb = 320
Intermodulation Distortion
IMD
–4
2fa – fb
—
–1.0
—
TMC = 1
PCMIN to
PCMOUT
*1
D-to-D Mode Gain
—
1020
0 to
0
—
+1.0
dB
dB
PSR T
Power Supply Noise Rejection Ratio
50 mVPP
30
—
PSR R 50 kHz
t
50
50
50
50
—
—
—
—
200
200
200
200
SD
t
XD1
XD2
XD3
Digital Output Delay Time
CL = 100 pF + 1 LSTTL
ns
t
t
*1 The measurement under idle channel noise
14/20
¡ Semiconductor
MSM7541/7542
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing
BCLOCK
XSYNC
1
2
3
4
5
6
7
8
9
10
11
tXS
tSX
tWS
tXD1
tSD
MSD
tXD2
D3
tXD3
D8
PCMOUT
D2
D4
D5
D6
D7
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1
When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD
.
.
Receive Timing
BCLOCK
tRS
1
2
3
4
5
6
7
8
9
10
11
tSR
tWS
RSYNC
tDS
tDH
PCMIN
MSD
D2
D3
D4
D5
D6
D7
D8
15/20
¡ Semiconductor
MSM7541/7542
APPLICATION CIRCUIT
Analog interface
Digital interface
+3.3 V
MSM7541/7542
0.1 mF
AIN–
PCMOUT
XSYNC
RSYNC
BCLOCK
PCMIN
PDN
PCM signal output
Analog input
51 kW
8 kHz SYNC signal input
GSX
AIN+
SG
BCLOCK input
PCM data input
AOUT–
PWI
Power Down control input
Analog output
TMC
Analog loop-back
control input
VFRO
SGC
AG
51 kW
0.1 mF
0 V
DG
10 mF
0 to 10 W
+
1 mF
+3.3 V
VDD
FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT
Microphone amp
C1
Transmit frequency
characteristic
Adjustment determined with
C1, C2, R1, R2.
R1
M
AIN–
C2
R2
GSX
AIN+
SG
Receive frequency
characteristic
Adjustment determined with
C3, C4, R3, R4.
AOUT+
AOUT–
R4
C4
PWI
Receiver impedance to
1.2 kW + 55 nF
VFRO
R3 C3
16/20
¡ Semiconductor
MSM7541/7542
RECOMMENDATIONS FOR ACTUAL DESIGN
• Toassureproperelectricalcharacteristics,usebypasscapacitorswithexcellenthighfrequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.
• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-
DD
up phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
powersupplytoavoiderroneousoperationandthedegradationofthecharacteristicsofthese
devices.
17/20
¡ Semiconductor
PACKAGE DIMENSIONS
DIP20-P-300-2.54-S1
MSM7541/7542
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.49 TYP.
18/20
¡ Semiconductor
MSM7541/7542
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
19/20
¡ Semiconductor
MSM7541/7542
(Unit : mm)
TSOPII26/20-P-300-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.38 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
20/20
相关型号：
MSM7543TS-K
PCM Codec, MU-Law, 1-Func, CMOS, PDSO20, 0.300 INCH, 1.27 MM PITCH, PLASTIC, TSOP2-26/20
OKI
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