MSM7620-001GS-K [OKI]
Echo Canceler; 回波消除器
| 型号： | MSM7620-001GS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Echo Canceler |
| 文件： | 总28页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0038-28-81
This version: Aug. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7620
Echo Canceler
GENERAL DESCRIPTION
The MSM7620 is an improved version of the MSM7520 with the same basic configuration. The
MSM7620 includes following improvements: a modified through mode, timing control of the
control pin input, and a thinner package. The MSM7620 also provides a pin-for-pin replacement
with the MSM7520.
The MSM7620 is a low-power CMOS IC device for canceling echo (in an acoustic system or
telephone line) generated in a speech path.
Echo is canceled (in digital signal processing) by estimating the echo path and generating a
pseudo-echo signal.
Used as an acoustic echo canceler, the MSM7620 cancels the acoustic echo between the loud
speaker and the microphone which occurs during hands free communication, such as on a car
phone or a conference system phone.
Usedasalineechocanceler, thedevicecancelsthelineechoimpedancemismatchinginahybrid.
In addition, a quality conversation is made possible by controlling the level and preventing
howling with a howling detector, double talk detector, attenuation function and a gain control
function, and by controlling the low level noise with a center clipping function.
The MSM7620 I/O interface supports m-law PCM. The use of a single chip CODEC, such as the
MSM7543, allows the configuration an economic and efficient echo canceler to be configured.
Note: If the object is to cancel line echo, the use of the MSM7602 is recommended, for the
MSM7602isprovidedwithahowlingdetectcontrolpin. Inaddition,theMSM7602,whilehaving
characteristics equivalent to the MSM7620, is packaged small.
FEATURES
• Handles both acoustic echoes and telephone line echoes.
• Cancelable echo delay time:
MSM7620-001................. For a single chip: 23 ms (max.)
MSM7620-011................. For a cascade connection (can also be used for a single chip)
Master chip: 23 ms (max.)
Slave chip: 31 ms (max.)
Cancelable up to 213 ms (one master plus six slaves)
For a single chip: 23 ms (max.)
• Echo attenuation
• Clock frequency
: 30 dB (typ.)
: 18 MHz (36 MHz cannot be used)
External input and internal oscillator circuit are provided.
• Power supply voltage : 5 V (4.5 V to 5.5 V)
• Power consumption
: 150 mW (typ.) When powered down: 20 mW (typ.)
• Package options:
32-pin plastic SSOP (SSOP32-P-640-0.80-K) (Product name : MSM7620-001GS-K)
64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name : MSM7620-011GS-BK)
1/28
¡ Semiconductor
MSM7620
BLOCK DIAGRAM
MSM7620-001 (Single chip only)
RIN
ROUT
Non-linear/
Linear
Linear/
Non-linear
S/P
ATT
Gain
P/S
Howling
Detector
Double Talk
Detector
Power
Calculator
Adaptive
FIR Filter
(AFF)
–
+
SOUT
SIN
WDT
VDD
VSS
Linear/
Center
Clip
Non-linear/
Linear
P/S
ATT
S/P
+
Non-linear
RST
PWDWN
Clock Generator
Mode Selector
I/O Controller
X1/CLKIN
X2 SCKO SYNCO NLP HCL ADP ATT GC
IRLD INT SCK SYNC
MSM7620-011 (Cascade connection or Single chip)
RIN
ROUT
Non-Linear
/Linear
Linear/
Non-linear
S/P
ATT
Gain
P/S
PD15 *
Parallel
I/O Port
PD 0 *
Howling
Detector
Double Talk
Detector
Power
Adaptive
FIR Filter
(AFF)
OF1 *
OF2 *
SF1 *
SF2 *
Calculator
Parallel
I/O
Controller
–
+
SOUT
SIN
Linear/
Non-linear
Center
Clip
Non-linear/
Linear
P/S
ATT
S/P
+
WDT
*RST
VDD
VSS
*
*
*PWDWN
Clock Generator
Mode Selector
I/O Controller
X1/CLKIN
*
X2 SCKO SYNCO NLP HCL ADP ATT GC MS IRLD INT SCK SYNC
*
*
*
* If the MSM7620-011 is used in the slave mode, only the diagonally hatched blocks and
the pins marked with * are used.
2/28
¡ Semiconductor
MSM7620
PIN CONFIGURATION (TOP VIEW)
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-Pin Plastic SSOP
Pin
1
Symbol
*
Pin
9
Symbol
SIN
Pin
17
18
19
20
21
22
23
24
Symbol
Pin
25
26
27
28
29
30
31
32
Symbol
SCKO
*
*
2
NLP
HCL
ADP
VSS
10
11
12
13
14
15
16
RIN
*
*
3
SCK
RST
WDT
GC
4
SYNC
SOUT
ROUT
*
X1/CLKIN
X2
5
6
ATT
*
*
7
INT
PWDWN
SYNCO
*
8
IRLD
VSS
VDD
*: No connect pin
Note:
Pin 26 of the MSM7520 is CKSEL, while that of the MSM7620 is in open state.
It is possible to replace the MSM7520 with the MSM7620.
3/28
¡ Semiconductor
MSM7620
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-Pin Plastic SSOP
Pin
1
Symbol
NLP
HCL
ADP
MS
Pin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Symbol
*
Pin
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Symbol
PD12
PD13
X1/CLKIN
X2
Pin
Symbol
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
*
*
2
*
3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
*
PD14
PD15
*
4
5
ATT
INT
*
6
PWDWN
*
SF2
OF1
*
7
*
8
IRLD
*
SYNCO
SCKO
*
9
*
10
11
12
13
14
15
16
SIN
*
RIN
*
SF1
OF2
*
SCK
SYNC
SOUT
ROUT
VSS
RST
WDT
GC
VDD
*
VDD
*
VDD
*
*: No connect pin
Note:
Pins43,53,and61oftheMSM7520areCKSEL,V ,andTST2respectively.Whilethese
pins of the MSM7620 are in open state, it is possible to replace the MSM7520 with the
MSM7620.
DD
4/28
¡ Semiconductor
MSM7620
PIN DESCRIPTIONS (1/5)
Pin
Symbol
32-pin 64-pin
SSOP QFP
Type
Description
2
1
NLP
I
The control pin for the center clipping function. This forces the SOUT
output to a minimum value (FF) when the SOUT signal is below -54
dBm0. Effective for reducing low-level noise.
• Single Chip or Master Chip in a Cascade Connection
"H": Center clip ON
"L": Center clip OFF
• Slave Chip in a Cascade Connection
Fixed at "L"
This input signal is loaded in synchronization with the falling edge of
the INT signal or the rising edge of the RST signal.
3
2
I
HCL
The through mode control.
When this pin is in the through mode, RIN and SIN data are output to
ROUT and SOUT. At the same time, the coefficient of the adaptive FIR
filter is cleared.
• Single Chip or Master Chip in a Cascade Connection
"H": Through mode
"L": Normal mode (echo canceler operates)
• Slave Chip in a Cascade Connection
Same as master
This input signal is loaded in synchronization with the falling edge of
the INT signal or the rising edge of the RST signal.
4
3
ADP
I
AFF coefficient control pin. This pin stops updating of the adaptive FIR
filter (AFF) coefficient and sets the coefficient to a fixed value, when this
pin is configured to be the coefficient fix mode.
This pin is used when holding the AFF coefficient which has been once
converged.
• Single Chip or Master Chip in a Cascade Connection
"H": Coefficient fix mode
"L": Normal mode (coefficient update)
• Slave Chip in a Cascade Connection
Fixed at "L"
This input signal is loaded in synchronization with the falling edge of
the INT signal or the rising edge of the RST signal.
Selection of the Master Chip and slave chip when used in a cascade
connection.
—
4
I
MS
"L": Single chip or master chip
"H": Slave chip
5/28
¡ Semiconductor
MSM7620
(2/5)
Pin
32-pin 64-pin
SSOP QFP
Symbol
Description
Type
6
5
I
Control for the ATT function that prevents howling by attenuators (ATT)
for the RIN input and SOUT output.
ATT
If there is input only to RIN, then the ATT for the SOUT output is
activated.
If there is no input to SIN, or if there is input to both SIN and RIN, the
ATT for the RIN input is activated.
Either the ATT for the RIN output or the ATT for the SOUT is always
activated in all cases, and the attenuation of ATT is 6 dB.
• Single Chip or Master Chip in a Cascade Connection
"H": ATT OFF
"L": ATT ON
"L" is recommended for echo cancellation.
• Slave Chip in a Cascade Connection
• Fixed at "L"
This input signal is loaded in synchronization with the falling edge of the
INT signal or the rising edge of the RST signal.
7
6
INT
I
Interrupt signal which starts 1 cycle (8 kHz) of the signal processing.
Signal processing starts when H-to-L transition is detected.
• Single Chip or Master Chip in a Cascade Connection
Connect the IRLD pin.
• Slave Chip in a Cascade Connection
Connect the IRLD pin of the master chip.
INT input is invalid for 100 ms after reset due to initialization. Refer to
the control pin connection example.
8
8
O
IRLD
Load detection signal when the SIN and RIN serial input data is loaded
in the internal registers.
• Single Chip
Connect to the INT pin.
• Master Chip in a Cascade Connection
Connect to the INT pin of the master chip and all the slave
chips.
• Slave Chip in a Cascade Connection
Leave open.
Refer to the control pin connection example.
9
10
I
Transmit serial data.
SIN
Input the m-law PCM signal synchronized to SYNC and SCK. Data is
read in at the fall of SCK.
6/28
¡ Semiconductor
MSM7620
(3/5)
Pin
Type
Symbol
Description
32-pin 64-pin
SSOP QFP
Receive serial data.
10
11
RIN
I
I
Input the m-law PCM signal synchronized to SYNC and SCK. Data is read in at the fall of SCK.
12
11
SCK
Clock pin for transmit/receive serial data. This pin uses the external
SCK or the SCKO.
Input the PCM CODEC transmit/receive clock (64 to 2048 kHz).
Sync signal for transmit/receive serial data. This pin uses the external
SYNC or SYNCO.
12
13
14
—
13
14
15
19
SYNC
SOUT
ROUT
PD0
I
O
Input the PCM CODEC transmit/receive sync signal (8 kHz).
Transmit serial data.
This pin outputs the m-law PCM signal synchronized to SYNC and SCK.
This pin is in a high impedance state while there is no data output.
Receive serial data.
O
This pin outputs the m-law PCM signal synchronized to SYNC and SCK.
This pin is in a high impedance state while there is no data output.
Bidirectional bus for parallel data transfer between the Master Chip and
Slave Chip when used in a cascade connection.
The PD15 pin corresponds to MSB.
I/O
30
33
34
51
52
35
PD11
PD12
—
—
—
—
—
20
This pin is in a high impedance state while there is no data output. Data
is loaded in at the falling edge of SFx.
PD13
PD14
PD15
X1/CLKIN
I
External input for the basic clock or for the crystal oscillator.
Input the basic clock (18 MHz).
Refer to the internal clock generator circuit example.
Crystal oscilator.
O
36
38
21
23
X2
Used to configure the oscillation circuit.
Refer to the internal clock generator circuit example.
When inputting the basic clock externally, insert a 5 pF capacitor with
excellent high frequency characteristics between X2 and GND.
Power-down mode control.
I
PWDWN
"L": Power-down mode
"H": Normal operation mode
During power-down, all input pins are disabled and output pins are in
the following sates :
High impedance : SOUT, ROUT, PD0 to 15
"L": SYNCO, SCKO
"H": OF1, OF2
Holds the last state : WDT, IRLD
Not affected: X2, MCKO
Reset after power-down is released.
7/28
¡ Semiconductor
MSM7620
(4/5)
Pin
Symbol
Type
Description
32-pin 64-pin
SSOP QFP
40
24
SYNCO
O
8 kHz sync signal for the PCM CODEC.
Connect this pin to the SYNC pin andthePCMCODECtransmit/receive
sync pin.
Leave it open if using an external SYNC.
Transmit clock signal (200 kHz) for the PCM CODEC.
Connect this pin to the SCK pinandthe PCM CODECtransmit/receive
clock pin.
41
SCKO
O
25
Not affected by reset. Outputs "0" during power-down.
Leave it open if using an external SCK.
Reset signal.
27
44
I
RST
"L": Reset mode
"H": Normal operation mode
During initialization, input signals, except for PWDWN are disabled for
100 ms after reset (after RST is returned from "L" to "H").
Input the basic clock during the reset.
Output pins during reset are in the following sates :
High impedance: SOUT, ROUT, PD0 to 15
"L": WDT
"H": OF1, OF2
Not affected: X2, SYNCO, SCKO, IRLD, MCKO
Test pin.
28
29
WDT
GC
O
I
45
46
Leave this pin open.
Input signal for the gain controller when RIN input is controlled and the
RIN input level is controlled and howling is prevented.
The gain controller adjusts the RIN input level when it is –20 dBm0 or
above. RIN input levels from –20 to –11.5 dBm0 will be suppressed to
–20 dBm0 in the attenuation range from 0 to 8.5 dB.
RIN input levels above –11.5 dBm0 will always be attenuated by 8.5 dB.
• Single Chip or Master Chip in a Cascade Connection
"H": Gain control ON
"L": Gain control OFF
"H" is recommended for echo cancellation.
• Slave Chip in a Cascade Connection
Fixed at "L"
This pin is loaded in synchronization with the falling edge of the INT
signal or the rising edge of RST.
8/28
¡ Semiconductor
MSM7620
(5/5)
Pin
Symbol
Type
Description
32-pin 64-pin
SSOP QFP
Parallel data transfer flag.
• Single Chip
—
54
SF2
I
Fixed at "H"
• Master Chip in a Cascade Connection
Fixed at "H"
• Slave Chip in a Cascade Connection
Connect OF2 of the master chip to the first stage slave chip.
Connect OF1 of the previous stage slave chip to the second and
later stage slave chips.
Refer to the control pin connection example.
—
55
OF1
O
Parallel data transfer flag.
• Single Chip
Leave this pin open.
• Master Chip in a Cascade Connection
Connect to the SF1 of all slaves.
• Slave chip in a Cascade Connection
Connect to the SF2 of the next stage slave chip.
Connect the last stage slave chip to the SF1 of the master chip.
Refer to the control pin connection example.
Parallel data transfer flag.
—
59
I
SF1
• Single Chip
Connect OF2.
• Master Chip in a Cascade Connection
Connect OF1 of the last stage slave chip.
• Slave Chip in a Cascade Connection
Connect OF1 of master chip for all slave chips.
Refer to the control pin connection example.
—
O
Parallel data output flag.
60
OF2
• Single Chip
Connect to SF1.
• Master Chip in a Cascade Connection
Connect to SF2 of the first stage slave chip.
• Slave Chip in a Cascade Connection
Leave open.
Refer to the control pin connection example.
9/28
¡ Semiconductor
MSM7620
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Input Voltage
Symbol
VDD
Condition
Ta = 25°C
—
Rating
–0.3 to +7
–0.3 to VDD + 0.3
1
Unit
V
VIN
V
Power Dissipation
Storage Temperature
PD
W
TSTG
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Power Supply Voltage
Symbol
VDD
Condition
Min.
Typ.
5
Max.
Unit
V
—
4.5
—
5.5
—
VSS
—
0
V
Pins other than X1
2.4
3.5
0
—
—
—
+25
VDD
VDD
0.8
+85
V
Input High Voltage
VIH
X1 pin
—
V
Input Low Voltage
VIL
Ta
V
Operating Temperature
—
–40
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = –40°C to +85°C)
Parameter
Output High Voltage
Symbol
VOH
Condition
IOH = 40 mA
IOL = 1.6 mA
IH = VDD
VIL
SS to VDD
Min.
4.2
0
Typ.
—
Max.
VDD
0.4
Unit
V
Output Low Voltage
VOL
—
V
High Level Input Current
IIH
V
—
0.1
10
mA
=
SF1, SF2
–100
–50
–10
mA
V
with pull-up
Input other than
the above
IIL
Low Level Input Current
High Level Output Current
Low Level Output Current
–10
—
–0.1
0.1
—
10
mA
mA
mA
IOZH
VOH = VDD
VOL
SS to VDD
=
PD15 to PD0
with pull-up
Input other than
the above
–100
–50
+10
V
IOZL
–10
—
–0.1
30
4
—
40
5
mA
mA
mA
mA
Power Supply Current
(Operating)
IDDO
—
When extarnal input is used
Power Supply Current(Stand-by)
—
as basic clock
IDDS
When oscillation circuit is
PWDWN="L"
—
6
8
used as basic clock
Input Capacitance
CI
—
—
—
—
—
—
15
20
pF
pF
Output Load Capacitance
CLOAD
10/28
¡ Semiconductor
MSM7620
Echo Canceler Characteristics (Refer to Characteristics Diagram)
Parameter
Symbol
Condition
RIN = –10 dBm0
Min.
Typ.
Max.
Unit
(5 kHz band white noise)
E. R. L. (echo return loss)
= 6 dB
Echo Attenuation
LRES
—
30
—
dB
TD = 20 ms
ATT, GC, NLP: OFF
Cancelable Echo Delay Time for a
Single Chip or a Master Chip in a
Cascade
RIN = –10 dBm0
TD
—
—
—
—
23
31
ms
ms
(5 kHz band white noise)
E.R.L. = 6 dB
Cancelable Echo Delay Time for a
Slave Chip in a Cascade
ATT, GC, NLP: OFF
TDS
11/28
¡ Semiconductor
MSM7620
AC Characteristics
(Ta = –40°C to +85°C)
Typ.
18.0
55.56
50
Parameter
Condition
Min.
17.5
54.1
40
Max.
18.5
57.1
60
Unit
MHz
ns
Symbol
fC
Clock Frequency
—
tMCK
tDMC
tMCH
tMCL
tr
Clock Cycle Time
—
%
Clock Duty Ratio
—
ns
Clock "H" Level Pulse Width
Clock "L" Level Pulse Width
Clock Rise Time
—
23.5
23.5
—
—
—
ns
—
—
—
ns
—
—
5
ns
Clock Fall Time
tf
—
—
5
—
tDCM
fCO
ns
Sync Clock Output Time
—
—
100
—
—
Internal Sync Clock Frequency
Internal Sync Clock Output Cycle Time
Internal Sync Clock Duty Ratio
Internal Sync Signal Output Delay Time
Internal Sync Signal Period
Internal Sync Signal Output Width
Transmit/receive Operation Clock Frequency
Transmit/receive Sync Clock Cycle Time
Transmit/receive Sync Clock Duty Ratio
Transmit/receive Sync Signal Period
fc = 18 MHz
200
5
kHz
ms
%
—
tCO
fc = 18 MHz
—
—
tDCO
tDCC
tCYO
tWSO
fSCK
tSCK
tDSC
tCYC
tXS
50
—
fc = 18 MHz
—
5
ns
—
fc = 18 MHz
—
125
tCO
—
—
ms
ms
kHz
ms
%
fc = 18 MHz
—
—
fc = 18 MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2048
15.6
60
64
—
0.488
40
50
123
45
125
—
—
ms
ns
—
Sync Timing
tSX
45
—
—
ns
tSCK
tWSY
tDS
—
tCYC–tSCK
—
ms
ns
Sync Signal Width
—
Receive Signal Setup Time
Receive Data Hold Time
Receive Data Input Time
IRLD Signal Output Delay Time
IRLD Signal Output Width
45
45
—
—
—
—
—
—
tDH
—
ns
7tSCK
tID
—
ms
ns
tDIC
tWIR
tSD
—
138
—
tSCK
ms
90
—
—
Serial Output Delay Time
ns
tXD
90
12/28
¡ Semiconductor
MSM7620
AC Characteristics (Continued)
(Ta = –40°C to +85°C)
Parameter
Reset Signal Input Width
Reset Start Time
Symbol
Condition
Min.
1
Typ.
—
Max.
—
Unit
ms
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWR
tDRS
tDRE
tDIT
—
—
5
—
—
Reset End Time
—
—
100
—
—
20
120
20
10
—
—
—
—
—
—
—
52
Processing Operation Start Time
Power Down Start Time
Power Down End Time
Control Pin Setup Time (INT)
Control Pin Hold Time (INT)
Control Pin Setup Time (RST)
Control Pin Hold Time (RST)
Parallel Data Output Signal Width
Flag Signal Output Time
Flag Signal Output Width
Flag Signal Input Width
Data Read Setup Time
—
—
—
tDPS
tDPE
tDTS
tDTH
tDSR
tDHR
tWPD
tDF
—
—
111
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2tMCK
tMCK
tMCK/2
tWFO
20
—
—
—
tWFO
tWFI
tFS
—
—
OFz connected to SFx
—
—
—
—
Data Read Hold Time
tFH
10
—
13/28
¡ Semiconductor
MSM7620
TIMING DIAGRAM
Clock Timing
fc. tMCK
tMCH
tMCL
tr
tf
tDMC
X1/CLKIN
tDCM
SCKO
SCKO
fco. tCO
tDCO
tDCC
tDCC
tCYO
SYNCO
tWSO
Serial Input Timing
fsck. tSCK
tDSC
SCK
tSX
tXS
tCYC
SYNC
tWSY
tDH
tDS
SIN
RIN
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
tID
tDIC
tDIC
IRLD
tWIR
14/28
¡ Semiconductor
MSM7620
Serial Output Timing
fsck. tSCK
tDSC
SCK
tSX
tXS
tCYC
SYNC
tWSY
tXD
tSD
tXD
tXD
High-Z
High-Z
SOUT
ROUT
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
Operation Timing After Reset
tWR
*Reset timing can be asynchronous
RST
tDIT
tDRS
tDRE
Reset
Initialization
Processing Start
Internal operation
Note: INT is invalid in the diagonally shaded interval.
Power Down Timing
PWDWN
*tDPS
tDPE
Power Down
Processing Start
Internal Operation
*Input MCK in the tDPS interval.
15/28
¡ Semiconductor
MSM7620
Control Pin Load-in Timing
*tCYC
INT(IRLD)
tDTH
*Refer to the Serial Input Timing
tDTS
NLP, HCL,
ATT, ADP, GC
tWR
RST
tDHR
tDSR
NLP, HCL,
ATT, ADP, GC
Parallel Output Timing
tWPD
PD15
High-Z
High-Z
Output Data
PD 0
tDF
tWFO
OF1
OF2
Parallel Input Timing
tWFI
SF1
SF2
tFS
tFH
PD15
PD 0
Input Data
16/28
¡ Semiconductor
MSM7620
HOW TO USE THE MSM7620
The MSM7620 cancels the echo which returns to SIN using the RIN signal.
Connect the base signal to the R-side and the echo generated signal to the S-side.
Connection Methods According to Echos
Example 1:
Canceling acoustic echo (to handle acoustic echo from line input)
CODEC
MSM7620
CODEC
ROUT
SIN
RIN
Line input
AFF
m-law
m-law
H
Acoustic echo
–
SOUT
+
+
Example 2:
Canceling line echo (to handle line echo from microphone input)
CODEC
MSM7620
CODEC
RIN
ROUT
Microphone Input
AFF
m-law
m-law
H
–
+
SOUT
SIN
+
Line echo
Example 3:
Canceling line echo in a cascade connection
(to handle line echo from microphone input)
CODEC
MSM7620
Master
CODEC
RIN
ROUT
SIN
Microphone input
AFF
m-law
m-law
H
H
–
SOUT
+
+
Line echo
PD0 - 15
Slave
AFF
17/28
¡ Semiconductor
MSM7620
Example 4: Canceling of both acoustic echo and line echo
(to handle both acoustic echo from line input and line echo from microphone input)
CODEC
MSM7620
AFF
MSM7620
CODEC
Line input
ROUT
SIN
RIN SOUT
SOUT RIN
SIN
+
+
–
m-law
m-law
H
Acoustic echo
–
AFF
ROUT
+
+
Line echo
For acoustic echo
For line echo
Microphone input
18/28
¡ Semiconductor
MSM7620
Control Pin Connection Example
Two-stage Cascade Connection
Single Chip Connection
Master + (slave ¥ 1)
+5 V
Master chip
Slave chip
MS * * PD15
MS
PD15
PD 0
MS
PD15
PD 0
NLP
HCL
NLP
NLP
HCL
NLP
HCL
ADP
ATT
NLP
HCL
ADP
ATT
HCL * PD 0
ADP
ADP
ADP
ATT
ATT
ATT
GC
GC
GC
GC
GC
PWDWN
RST
PWDWN
RST
INT
SF1 * * OF1
SF2 * * OF2
PWDWN
RST
PWDWN
RST
INT
SF1
SF2
PWDWN
RST
INT
SF1
SF2
IRLD
IRLD
OF1
OF2
IRLD
OF1
OF2
+5 V
+5 V
Asterisk * mark indicates a pin only for the MSM7620-011.
Four-stage Cascade Connection
Master + (slave ¥ 3)
+5 V
+5 V
+5 V
Master chip
Slave chip 1
Slave chip 2
Slave chip 3
MS
PD15
PD 0
MS
PD15
PD 0
MS
PD15
PD 0
MS
PD15
PD 0
NLP
HCL
NLP
HCL
ADP
ATT
GC
NLP
HCL
ADP
ATT
NLP
HCL
ADP
ATT
NLP
HCL
ADP
ATT
ADP
ATT
GC
GC
GC
GC
PWDWN
RST
PWDWN
RST
INT
SF1
SF2
PWDWN
RST
INT
SF1
SF2
PWDWN
RST
INT
SF1
SF2
PWDWN
RST
INT
SF1
SF2
IRLD
OF1
OF2
IRLD
OF1
OF2
IRLD
OF1
OF2
IRLD
OF1
OF2
+5 V
19/28
¡ Semiconductor
MSM7620
Clock Circuit Example
Internal clock generator circuit
MSM7620
X1/CLKIN
X2
XTAL : 18 MHz
: 1 MW
C1 : 27 pF
C2 : 27 pF
R
R
XTAL
C1
C2
GND
GND
External clock input circuit
MSM7602
X1/CLKIN
X2
5pF
18 MHz
GND
20/28
¡ Semiconductor
MSM7620
ECHO CANCELER CHARACTERISTICS DIAGRAM
ERL vs. echo attenuation
RIN input level vs. echo attenuation
40
30
20
10
0
40
30
20
10
0
40 30 20 10
ERL. [dB]
0
–10
–50 –40 –30 –20 –10
0
RIN input level [dBm]
0 dBm = 2.2 dBm0
Measurement Conditions
RIN input = –10 dBm 5 kHz band white noise
(0 dBm = 2.2 dBm0)
Echo delay time TD = 20 ms
ATT, GC, NLP = OFF
Measurement Conditions
RIN input: 5 kHz band white noise
Echo delay time TD = 20 ms
ERL = 6 dB
ATT, GC, NLP = OFF
Echo delay time vs. echo attenuation
30
20
10
0
1
2
3
4
5
6
7chip
0
50
100
150
200
Echo delay time [ms]
Measurement Conditions
RIN input = –10 dBm
5 kHz band white noise
(0 dBm = 2.2 dBm0)
ERL = 6 dB
ATT, GC, NLP = OFF
The second through seventh chips
are connected in a cascade.
21/28
¡ Semiconductor
MSM7620
Measurement System Block Diagram
White noise generator
MSM7543
PCM
MSM7543
TD
RIN input
A
RIN
ROUT
SIN
PCM
A
Delay
L. P. F.
5 kHz
Echo delay time
m-law
CODEC
m-law
CODEC
MSM7620
Level meter
A
PCM
SOUT
PCM
A
ATT
ERL
(echo return loss)
22/28
MSM7543GS-VK
MSM7543GS-VK
For cancellation of acoustic echo
For cancellation of line echo
R6
R12
R4
13
R5
R11
9
R10
13
Mike input
C1
SIN
Circuit input
C5
23
6
9
13
10
2
13
10
2
23
6
AIN+
VFRO
GSX
PCMOUT
PCMIN
SIN
SOUT
RIN
SOUT
SIN
ROUT
SCK
PCMOUT
PCMIN
AIN+
VFRO
GSX
RIN
12
15
14
11
14
11
12
15
ROUT
Speaker output
ROUT
SCK
RIN
NLP
HCL
ADP
ATT
GC
SOUT
Circuit output
21
21
BCLOCK
NLP
HCL
ADP
ATT
GC
BCLOCK
R2
R3
R8
R9
11
14
12
7
3
3
12
7
11
14
RSYNC
XSYNC
SYNC
INT
SYNC
INT
RSYNC
XSYNC
22
22
R1
R7
AIN–
SG
AIN–
SG
4
4
8
8
IRLD
IRLD
6
6
1
3
5
1
10
19
23
27
28
23
27
28
10
19
PDN
TMC
PWDWN
RST
PWDWN
RST
PDN
TMC
3
5
24
29
29
AOUT–
PWI
SGC
AOUT–
PWI
SGC
24
WDT
WDT
C7
C3
R13
C2
24
25
24
25
R14
8
8
SYNCO
SCKO
SYNCO
SCKO
VDD
AG
VDD
AG
32
C4
5
32
C8
5
+
C6
+
VDD
+
+
VDD
C10
C9
9
9
16
16
DG
DG
20
21
20
21
X1
X2
VSS
VSS
VSS
VSS
X1
X2
16
16
32-Pin SSOP
32-Pin SSOP
R1 > 50 kW
R2 > 20 kW
R3 > 20 kW
R4 = 2.2 kW
R5 = 10 kW
R6 = 10 kW
R7 > 50 kW
C1 = 0.1 mF
C2 = 10 mF
C3 = 0.1 mF
C4 = 10 mF
C5 = 0.1 mF
R8 > 20 kW
R9 > 20 kW
CLK
EXT.
SCK
R10 = 2.2 kW
R11 = 10 kW
R12 = 10 kW
R13 = 0-22 W
R14 = 0-22 W
C6 = 10 mF
C7 = 0.1 mF
C8 = 10 mF
C9 = 1.0 mF
C10 = 1.0 mF
EXT.
SYNC
RST
PWDWN
¡ Semiconductor
MSM7620
Cascade Connection Example
MSM7620-011GS-BK
MSM7620-011GS-BK
24/28
¡ Semiconductor
MSM7620
NOTES ON USE
1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be
amplified, the echo can not be eliminated.
Refer to the characteristics diagram for ERL vs. echo attenuation quantity.
2. Set the level of the analog input so that the PCM CODEC does not overflow.
3. The recommended input level is –10 to –20 dBm0. Refer to the characteristics
diagram for the RIN input level vs. echo attenuation quantity.
4. Applying the tone signal to this echo canceler will decrease echo attenuation. If the
tone signal is input to the SIN pin during the time that a signal is input to the RIN
pin, this echo cancceler operates faultily.
A signal must be input to either the RIN pin or the SIN pin. The ADP or HCL pin
must be driven at "H" if the tone signal is input to the SIN pin during the time that
a signal is input to the RIN pin.
5. Forchangesintheechopath(retransmit,circuitswitchingduringtransmission,and
so on), convergence may be difficult.
Perform a reset to make it converge.
Ifthestateoftheechopathchangesafterareset, convergencemayagainbedifficult.
In cases such as a change in the echo path, perform a reset when possible.
6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock
simultaneouly with power ON.
IfpoweringdownimmediatelyafterpowerON,besurefirstinput10ormoreclocks
of the basic clock.
7. After powering ON, be sure to reset.
8. After the power down pin is changed to a "1" from a "0", be sure to reset.
9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less
than 30 dB.
25/28
¡ Semiconductor
MSM7620
EXPLANATION OF TERMS
Attenuating Function :
Echo Attenuation :
Thisfunctionpreventshowlingandcontrolsthenoiselevelwithan
attenuator for the RIN input and SOUT output. Refer to the
explanation of pins (ATT pin).
If there is talking (input only to RIN) in the path of a rising echo
arises, the echo attenuation refers to the difference in the echo
return loss (canceled amount) when the echo canceler is not used
and when it is used.
Echo attenuation = (SOUT level during through mode operation)
– (SOUT level during echo canceler operation) [dB]
This is the time from when the signal is output from ROUT until it
returns to SIN as an echo or other similar device.
When using a hands free phone, and so on, the signal output from
the speaker echoes and is input again to the microphone. The
return signal is referred to as acoustic echo.
Echo Delay Time :
Acoustic Echo :
Telephone Line Echo :
Gain Control Function :
This is a signal which is delayed midway in a telephone line and
returns as an echo, due to reasons such as a hybrid impedance
mismatch.
This function prevents howling and controls the sound level by
with a gain controller for the RIN input. Refer to the explanation
of pins (GC pin).
Center Clipping Function : This function forces the SOUT output to a minimum value when
thesignalisbelow–57dBm0. Refertotheexplanationofpins(NLP
pin).
Double talk refers to a state in which the SIN and RIN signals are
input simultaneously. In a double talk state, a signal outside the
echo signal which is to be canceled can be input to the SIN input,
resulting in misoperation.
Double Talk Detection :
Thedoubletalkdetectorpreventssuchmisoperationsofthecanceler.
Thisistheoscillatingstatecausedbytheacousticcouplingbetween
the loud speaker and the microphone during hands free talking.
Howling not only interferes with talking, but can also cause
misoperation of the echo canceler.
Howling Detection :
The howling detector prevents such misoperation and prevents
howling.
Echo Return Loss (ERL) :
When the signal output from ROUT returns to SIN as an echo, ERL
refers to how much loss there is in the signal level during ROUT.
ERL = (ROUT level) – (SIN level of the ROUT signal which returns
as an echo) [dB]
IfERLispositive(ROUT>SIN),thesystemisanattenuatorsystem.
If ERL is negative (ROUT < SIN), the system is an amplifier system.
26/28
¡ Semiconductor
PACKAGE DIMENSIONS
SSOP32-P-640-0.80-K
MSM7620
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.83 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
27/28
¡ Semiconductor
MSM7620
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.87 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
28/28
相关型号：
©2020 ICPDF网 联系我们和版权申明