MSM7661B [OKI]
NTSC/PAL Digital Video Decoder; NTSC / PAL数字视频解码器
| 型号： | MSM7661B |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | NTSC/PAL Digital Video Decoder |
| 文件： | 总42页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2F0009-18-62
Preliminary
This version: Jun. 1998
¡ Semiconductor
MSM7661B
NTSC/PAL Digital Video Decoder
GENERAL DESCRIPTION
The MSM7661B is an LSI device which converts digitally sampled NTSC or PAL video signals
to 8-bit format based on ITU-RBT601.
The input video signals available are composite video signals and S video signals.
The composite video signals are converted to YUV data via a 2-dimensional Y/C separation
circuit.
The A-to-D converted data is data sampled at pixel clock frequency or double pixel clock
frequency (the built-in decimation filter is used). Input signal synchronization can lock
synchronization and color burst at high speed through internal digital processing.
The MSM7661B is upward compatible with the MSM7661. It provides additional features which
are added to the MSM7661 indicated by the mark n and is superior to the MSM7661 in picture
quality and synchronization stability. The device, which includes an additional register added
to the MSM7661, has electrical characteristics which are nearly equal to those of the MSM7661.
The MSM7661B allows a pin-for-pin replacement with the MSM7661.
FEATURES (• indicates a new feature compared with MSM7660. n indicates a
new feature compared with MSM7661.)
• Input video signals include the following two types of digital data that are A-to-D converted
at pixel frequency or double pixel frequency :
NTSC/PAL composite video signal
NTSC/PAL S video signal
8-bit Y/8-bit C (CbCr) output (conforms to ITU-RBT601)
°
YCbCr
4 : 2 : 2
YCbC4 : 1 : 1
nYCbCr 8-bit multiplex output (27 MHz) (not including SAV and EAV)
• 2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S video
signal input)
NTSC: 3 lines/2 lines
PAL: 2 lines (3 virtual lines)
• Input signal synchronization can lock synchronization and color burst at high speed through
internal digital processing.
Sampling frequency
13.5 MHz (ITU-R601)
°
12.27 MHz (NTSC Square Pixel)
14.31818 MHz (NTSC 4Fsc)
14.75 MHz (PAL Square Pixel)
• Internal AGC/ACC circuit
Switchable between AGC and MGC (fixed gain)
nSwitchable between ACC and MCC (fixed gain)
• Built-in decimation filter located in the input stage allows easy configuration of an external
filter circuit (located ahead of A/D converter).
• Automatic NTSC/PAL recognition (only for ITU-RBT.601)
• Sleep mode
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¡ Semiconductor
MSM7661B
• Multiplex signal recognition (Teletext)
Data during vertical blanking is output in 8 bits in Through mode.
2
I C-bus interface
°
• 3.3 V single power supply (each I/O pin is 5 V tolerable)
• Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7661B GS-BK)
2/42
SYNC
(CSYNC_L)
CLKX2O
CLKSEL
HSY
VSYNC_L
VVALID
PLLSEL
CLKX2
CLKXO SYSSEL
HSYNC_L HVALID
ODD
VCO_CP
YD[7:0]
Synchronization Block
lum.
8 bits
(YCbCr)
Y[7:0]
Luminance Block
(AGC + LPF)
Decimation
Filter
Epilogue
Block
Prologue Block
(2Dim.Y/Cseparate)
(Output Formatter)
Line Memory
(1kbyte) ¥ 2
Decimation
Filter
CD[7:0]
Chrominance Block
(ACC + LPF)
chr.
MODE[3:0]
C[7:0]
I2C-bus Control Logic
Test Control Logic
SCL
SDA
RESET_L
TE
TEST1 TEST2
(SLEEP)
¡ Semiconductor
MSM7661B
PIN CONFIGURATION (TOP VIEW)
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CD[0]
CD[1]
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
3
CD[2]
4
CD[3]
5
CD[4]
6
CD[5]
7
CD[6]
8
CD[7]
9
CVBS[0]
CVBS[1]
CVBS[2]
CVBS[3]
CVBS[4]
CVBS[5]
CVBS[6]
CVBS[7]
10
11
12
13
14
15
16
64-Pin Plastic QFP
4/42
¡ Semiconductor
MSM7661B
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
Chrominance signal input pin (valid only for S video input)
Set each pin to "L" level at composite signal input.
Composite signal input pin
1 to 8
CD[0 to 7]
I
9 to 16
CVBS[0 to 7]
I
Luminance signal is input for S video input.
17
18
VDD
GND
19
SCL
I
I2C-bus clock pin
20
SDA
I/O I2C-bus data pin
21 to 24
MODE[0 to 3]
I
Mode input pins. These pins are internally pulled-down.
MODE[3]
0: composite
MODE[2]
0: NTSC
1: PAL
1: S video
MODE[1:0]
00: ITU-R601
01: Square Pixel
10: 4Fsc (only for NTSC)
11: none
If ITU-R signals are input when registers are set to automatic NTSC/PAL
recognition mode, NTSC/PAL is automatically recognized irrespective of
MODE2 setting.
25
26
RESET_L
PLLSEL
I
I
System reset pin (active at "L")
Unused.
Fixed to "H" externally.
27
CLKSEL
I
Clock select input pin.
"L" Æ double-speed 27 MHz, "H" Æ ordinary 13.5 MHz
Input pin for testing. Normally "L". Internally pulled down.
Sleep mode setting pin. Normally "L". Internally pulled down.
Input pin for testing. Normally "L". Internally pulled down.
28
29
30
31
32
TEST1
SLEEP
TE
I
I
I
GND
VDD
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MSM7661B
Pin
Symbol
Type
Description
Chrominance signal output pins
33 to 40
Y[7 to 0]
O
YCbCr 8-bit multiplex output pins
Luminance signal output pins
41 to 48
49
C[7 to 0]
VDD
O
O
50
GND
51
ODD
Field display output pin
Outputs "H" for odd field.
52
53
54
55
56
57
VVALID
HVALID
VSYNC_L
HSYNC_L
CLKXO
O
O
O
O
O
O
Vertical valid line timing output pin
Horizontal valid pixel timing output pin
V sync output pin
H sync output pin
Internal operation clock output pin
SYSSEL
Display select output pin for NTSC-PAL detect / multiplex signal detect /
HLOCK sync detect.
Selection by register. (Default : NTSC-PAL detect)
NTSC mode : "L", PAL mode : "H"
Multiplex signal detect : "H"
HLOCK sync detect : "H"
58
59
CLKX2O
VCO_CP
O
O
Clock output pin
Unused.
Open normally.
60
SYNC
I/O Composite sync output.
Unused as input pin.
61
62
63
64
HSY
CLKX2
GND
O
I
Clamp signal timing output pin for A/D converter
Clock input pin
VDD
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MSM7661B
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Input Voltage
Symbol
VDD
Condition
Rating
–0.3 to +4.5
–0.3 to +5.5
800
Unit
V
—
—
—
—
VI
V
Power Consumption
Storage Temperature
PW
mW
°C
TSTG
–55 to +150
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Power Supply Voltage
"H" Level Input Voltage
"L" Level Input Voltage
Operating Temperature
Symbol
VDD
Condition
Min.
3.0
—
2.2
0
Typ.
3.3
0
Max.
3.6
Unit
V
—
—
—
—
—
GND
VIH
—
V
—
VDD
0.8
V
VIL
—
V
Ta
0
25
70
°C
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¡ Semiconductor
MSM7661B
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 0 to 70°C, VDD = 3.3 V 0.3 V)
Parameter
Symbol
Condition
IOH = –4 mA (*1)
IOH = –6 mA (*2)
IOH = –8 mA (*3)
IOL = 4 mA (*1)
IOL = 6 mA (*2)
IOL = 8 mA (*3)
Min.
Typ.
Max.
Unit
"H" Level Output Voltage
VOH
0.7 VDD
—
—
V
"L" Level Output Voltage
Input Leak Current
VOL
—
—
0.4
V
VI
=
GND to VDD
Rpull-down
50 kW (*4)
GND to VDD
–10
20
—
—
+10
250
+10
190
II
=
mA
Output Leak Current
IO
VI
=
–10
—
—
mA
CLK = 27 MHz
VDD = 3.3 V
CLK = 13.5 MHz
VDD = 3.3 V
SLEEP ON
—
Power Supply Current (operating)
IDDO
155
mA
Power Supply Current (operating)
IDDO2
—
125
160
mA
Power Supply Current (SLEEP)
SDA Output Voltage
IDDS
—
0
1
5
mA
V
SDAVL
SDAIO
—
—
0.4
—
SDA Output Current
—
3
mA
*1:
*2:
*3:
*4:
HSYNC_L, VSYNC_L, SYSSEL
Y[7:0], C[7:0], HSY, HVALID, VVALID, ODD, CLKXO
CLKX2O
MODE[3:0], SLEEP, TEST1, TE
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¡ Semiconductor
MSM7661B
AC Characteristics (Single Speed Mode)
(Ta = 0 to 70°C, VDD = 3.3 V 0.3 V)
Parameter
Symbol
Condition
ITU-R601
Min. Typ. Max. Unit
—
—
—
—
40
0
74.07
69.84
81.5
67.8
—
—
—
—
—
60
—
—
8
ns
ns
ns
ns
%
NTSC 4Fsc
CLKX2 Cycle Time
tCLKX1
NTSC Square Pixel
PAL Square Pixel
—
CLKX2 Duty
tD_D1
tIS1
Input Data Setup Time
CLKSEL : H
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Data Hold Time
tIH1
CLKSEL : H
30
2
—
Output Data Delay Time 1 (*)
Output Data Delay Time 2 (*)
Output Data Delay Time 3 (*)
Output Clock Delay Time (*) (External)
Output Clock Delay Time (*) (Internal)
SCL Clock Cycle Time
tODX1
tOD2X1
tOD1
CLKSEL : H
—
CLKSEL : H
2
—
7
CLKSEL : H
9
—
25
17
18
—
—
tCXD1
tCD1
tC_SCL
tL_SCL
CLKSEL : H
7
—
CLKSEL : H
7
—
Rpull_up = 4.7 kW
Rpull_up = 4.7 kW
200
100
—
Low Level Cycle
—
(*output load 40 pF)
AC Characteristics (Double Speed Mode)
(Ta = 0 to 70°C, VDD = 3.3 V 0.3 V)
Parameter
Symbol
Condition
ITU-R601
Min. Typ. Max. Unit
—
—
—
—
40
5
37.05
34.9
40.75
33.9
—
—
—
—
—
60
—
—
7
ns
ns
ns
ns
%
NTSC 4Fsc
CLKX2 Cycle Time
tCLKX2
NTSC Square Pixel
PAL Square Pixel
—
CLKX2 Duty
tD_D2
tIS2
Input Data Setup Time
CLKSEL : L
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Data Hold Time
tIH2
CLKSEL : L
15
2
—
Output Data Delay Time 1 (*)
Output Data Delay Time 2 (*)
Output Data Delay Time 3 (*)
Output Clock Delay Time (*) (External)
Output Clock Delay Time (*) (Internal)
SCL Clock Cycle Time
tODX2
tOD2X2
tOD2
CLKSEL : L
—
CLKSEL : L
2
—
6
CLKSEL : L
9
—
24
17
18
—
—
tCXD2
tCD2
tC_SCL
tL_SCL
CLKSEL : L
7
—
CLKSEL : L
7
—
Rpull_up = 4.7 kW
Rpull_up = 4.7 kW
200
100
—
Low Level Cycle
—
(*output load 40 pF)
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¡ Semiconductor
MSM7661B
Input and Output Timing
CLKSEL:H
tCLKX1
CLKSEL:L
tCLKX2
CLKX2
CLKX2O
CLKXO
tCXD1
tCXD2
tCD1
tCD2
tIS1
tIS2
tIH1
tIH2
not valid
not valid
not valid
not valid
CVBS
CD
RESET_L
tOD2X1
tODX1
tOD2X2
tODX2
tOD1
tOD2
HSY,
HVALID, VVALID,
ODD, SYSSEL,
Y,C,
HSYNC_L,
VSYNC_L
2
I C-bus Interface Input/Output Timing
2
The basic input/output timing of the I C-bus interface is as follows.
SDA
SCL
MSB
1
S
2
7
8
9
1
2
9
P
tC_SCL
ACK
3-8
ACK
Start Condition
Stop Condition
Data Line Stable: Data Valid Change of Data Allowed
2
I C-bus Basic Input/Output Timing
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¡ Semiconductor
MSM7661B
BLOCK DESCRIPTION
1.
Prologue Block
The prologue block performs Y/C separation by inputting data.
Data can be input either at ordinary pixel frequency (ITU-R : 13.5 MHz) or at double pixel
frequency (ITU-R: 27 MHz).
When the double pixel frequency is used, data is processed after changing to the ordinary pixel
frequency via a decimeter circuit.
By changing the register setting, the decimeter circuit can be bypassed irrespective of whether
data is input at ordinary pixel frequency or at double pixel frequency.
The prologue block performs Y/C separation using a 2-dimensional adaptive comb filter when
composite signals (CVBS) are input.
2
The following operation modes can be changed via the I C-bus. The * mark indicates a default.
The default is a state that is selected when reset.
1) Video input mode select
Composite video input *
S video input
2) Video input mode select
Auto NTSC/PAL select* (Only for ITU-R601)
Dependent on Operation mode selected
WhenITU-R601isselected, thevideoinputmodeisautomaticallydeterminedbythenumber
of lines per field.
3) Operation mode select
NTSC CCIR601
MTSC Square Pixel
NTSC 4Fsc
13.5 MHz*
12.27 MHz
14.31818 MHz
13.5 MHz
PAL CCIR601
PAL Square Pixel
14.75 MHz
4) Decimeter circuit pass/bypass select
Decimeter circuit is passed. *
Decimeter circuit is bypassed.
5) Y/C separation mode select
Adaptive comb filter is used. *
Unadaptive comb filter is used.
Trap filter is used.
The adaptive comb filter detects the correlation up to 3 lines between continuous lines. The Y/
C is separated by the comb filter according to the way of correlation if theses lines are correlated.
The Y/C is separated by the trap filter if these lines are not correlated (only 2 lines in the case of
PAL).
In the unadaptive comb filter, the Y/C is always separated by removing the luminance
component based on the average of preceding and following lines (when there is the correlation
between 3 lines).
11/42
¡ Semiconductor
MSM7661B
If the comb filter is not used, the Y/C is separated by the trap filter.
The Y/C separation circuit is bypassed by S video signal input.
In adittion, the functions of this block work only when lines are valid as image information.
The processing of CVBS signals is not made during V-blanking.
2.
Luminance Block
The luminance block removes synchronous signals from the signals containing luminance
components after Y/C separation. The signals are corrected and output as luminance signals.
The luminance signal output level gain control functions include three selectable modes such as
AGC (Auto Gain Control), MGC (manual Gain Control) + No Clamp, and MGC + Pedestal
Clamp.
In the AGC mode, the luminance level amplification is determined by comparing the depth of
SYNC with the reference value. The default is 40IRE which can be changed by the register. The
input is a sync chip clamp type.
IntheMGC+NoClampmode, theluminancesignaloutputlevelisnotaffectedbytheinput, and
the amplification and black level are controlled by setting the register.
In the MGC + Pedestal Clamp mode, the signal output level is clamped to the pedestal level of
the input. The signal amplification and black level are controllable from the clamped point by
setting the register.
This block can select the follwing operation modes.
1) Use of prefilter and sharp filter
Used*
Not used
These filters are used for enhancing the edges of luminance component signals.
2) Selection of aperture bandpass filter coefficient
Middle range*
High range
3) Coring range select
off*
±4LBS
±5LBS
±7LBS
4) Aperture weighting factor select
0*
0.25
0.75
1.5
The profile of these signals can be corrected by coring and aperture correction.
5) Use of pixel position correction circuit
Used*
Not used
6) AGC loop filter time constant select
Slow
Factor value 1/1024n
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¡ Semiconductor
MSM7661B
Medium
Fast
Fixed
1/64n*
1/n
0
7) Parameter for AGC reference level fine adjustment
8) Parameter for sync separation level fine adjustment
The black level is controlled. When the default is specified, the depestal position is output as a
black level (=16).
9) Pedestral clamp selecton
Pedestral clamp is not used.*
Pedestral clamp is used. (AGC will not operate)
3.
Chrominance Block
This is a chroma signal processing block.
The following modes can be selected.
1) Use of color bandpass filter
Used*
Not used
2) ACC loop filter time constant select
Slow
Factor value 1/1024n
Medium
Fast
Fixed
1/64n*
1/n
0
3) ACC reference level fine adjustment
4) Parameter for burst level fine adjustment
The threshold level for valid chroma amplitude is selected based on a color burst ratio.
0.5
0.25*
0.125
off
5) Color killer mode select
Auto color killer mode*
Forcible color killer
6) Parameter for color subcarrier phase fine adjustment
In this block, chroma signals pass through the chroma bandpass filter to cut an unnecessary
band. To maintain a constant chroma level, UV demodulation is performed on these signals
via the ACC correction circuit. (This filter can be bypassed.)
If the demodulation result does not reach a specified level, color killer signals are generated
to fix the ACC gain. This functions as an auto color killer control circuit.
The UV demodulation result is output as chrominance signals via a low pass filter.
13/42
¡ Semiconductor
MSM7661B
4.
Synchronization Block
This is a synchronizing signal processing block.
Chip output synchronizing signals and synchronizing signals for internal use are generated by
this block. Various signals are output in this block and the following operation modes can be
selected.
1) SYNC threshold level adjustment
2-1) Fine adjustment of HSY signal (start side)
2-2) Fine adjustment of HSY signal (stop side)
3) HSY signal enable select
High Level
Active*
These signal are used to sync chip and clamp timing to the A/D converter
4) Fine adjustment of HSYNC_L signal
5-1) Fine adjustment of HVALID signal (start side)
5-2) Fine adjustment of HVALID signal (stop side)
6-1) Fine adjustment of VVALID signal (start side)
6-2) Fine adjustment of VVALID signal (stop side)
The data signals are transmitted or received at the rising edge of the HVALID signal.
7) TV, VTR mode select
TV mode
VTR mode*
The TV mode outputs a fixed pixel number per one line and absorbs a jitter that does not appear
on the TV receiver normally.
The VTR mode outputs the results of decoding in accordance with the HSYNC signal regardless
of whether a jitter exists or not.
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¡ Semiconductor
MSM7661B
5.
Epilogue Block
The Epilogue Block outputs UV signals from the chrominance block and Y signals from the
luminance block in the format based on the signal obtained by setting of the control register.
In this block, the following modes can be selected.
1) Display of blue back when synchronization fails.
OFF
ON*
2) Output modes
2.1) ITUR 601 mode
Output signal Y/CbCr format select
YCbCr
YCbCr
4 : 2 : 2*
4 : 1 : 1
The chrominance signal (U, V component) outputs Cb and Cr data to the C pin in an
output format described later.
2.2) YCbCr 8-bit multiplex output mode
This mode does not include SAV and EAV.
3) Selection of 8-bit chroma signal output format
Offset binary*
2's Complement
4) Output pin enable select
High impedance
Output enable*
5) Multiplex signal detect level adjustment
The levels to detect multiplexed signals sent during the vertical blanking period are configured
to be variable. The binary values after input signals are A-to-D converted are employed as the
levels to detect multiplexed signals, and the levels are set in eight steps with respect to the SYNC
tip level.
Detect level
OMR [5:3]
80 to 136
video in
6) Various modes detection
NTSC/PAL detect mode*
Multiplex signal detect mode
HSYNC synchronization detect mode
7) Output signal phase control
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MSM7661B
2
6.
I C Control Block
2
This is the serial interface block based on the I C standard of Phillips Corporation.
This block functions only as a Slave-Receiver.
The external control can set the internal registers (MRA, MRB, HSYT, etc.).
7.
Test Control Block
This block is used to test this LSI. Normally it is not used.
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MSM7661B
Register Description
2
Registers controlled by I C bus are shown below.
A register setting value with an "*" indicates the default.
Enter "0" to the undefined register when setting registers.
Mode Register A (MRA) <default: 0xC0>
MRA[7]
MRA[6]
MRA[5]
MRA[4]
MRA[3]
MRA[2:0]
NTSC/PAL Auto select
Synchronization mode
Chroma format
0: Fix
*1: Auto
0: TV mode
*1: VTR mode
*0: Offset binary
1: 2's Complement
Override
*0: external terminal mode
1: register mode
Video Input mode
Video Input mode
*0: composite video input
1: S video input
*000: NTSC CCIR601
001: NTSC Square Pixel
010: NTSC 4Fsc
100: PAL CCIR601
101: PAL Square Pixel
13.5 MHz
12.27 MHz
14.31818 MHz
13.5 MHz
14.75 MHz
Mode Register B (MRB) <default: 0x18>
MRB[7]
MRB[6]
Sub Pixel Alignment
Color killer mode
*0: Sub Pixel Alignment is used.
1: Sub Pixel Alignment is not used.
*0: Autocolorkiller(Chrominance signallevel
becomes "0" when color burst level is below
specified value.)
*1: ForcedcolorkillerON(Chrominance signal
level is forced to be "0".)
MRB[5]
MRB[4]
Pixel Sampling Ratio
Blue Back
*0: (4:2:2)
1:
(4:1:1)
0: OFF (Video signal is demodulated and
output regardless of synchronization
detection .)
*1: AUTO (Blue Back is output when synchro-
nization is not detected.)
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¡ Semiconductor
MSM7661B
MRB[3]
MRB[2]
Sync enable, clamping pulse 0: HSY outputs "HIGH" level.
*1: HSY outputs active.
Data-pass control
*0: DECIMETER is used at 2X sampling.
1: No DECIMETER is used.
(Note) This register becomes valid at doube-speed clock input(27 MHz).
MRB[1:0]
Y/C separation mode
*00: Adaptive comb filter (Operation mode is
selected monitoring the correlation of 3
lines.)
01: Nonadaptive comb filter (Operation mode
is always fixed.)
10: Comb filter is not used. (Trap filter is used.)
11: Undefined
(Note) Adaptive comb filter:
Non-adaptive comb filter:
2/3-line comb filter at NTSC
Comb filter/trap filter at PAL
3-line comb filter at NTSC
2-line cosine comb filter at PAL
Horizontal Sync Trimmer (HSYT) <default: 0x00>
HSYT[7:4]
HSYT[3:0]
HSY begin trimmer (8/pixel)
HSY stop trimmer (8/pixel)
0xC: –4 (–32) to 0xB: +11 (+88)
0xC: –4 (–32) to 0xB: +11 (+88)
Sync Threshold level adjust (STHR) <default: 0x00>
STHR[7:0] Sync depth
0x0: –0 to *0x37:55 to 0xFF:255
(Note) The sync signal detect threshold level is adjusted.
Horizontal Sync Delay (HSDL) <default: 0x00>
HSDL[7:0]
HSYNC_L delay trimmer (4/pixel) 0x80: –128 (–512) to 0x7F: +127 (508)
Horizontal Valid Trimmer (HVALT) <default: 0x00>
HVALT[7:0]
HVALT[3:0]
HVALID begin trimmer (1/pixel)
HVALID stop trimmer (1/pixel)
0x8: –8 to 0x7: +7
0x8: –8 to 0x7: +7
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Vertical Valid Trimmer (VVALT) <default: 0x00>
VVALT[7:4]
VVALT[3:0]
VVALID begin trimmer (1/line)
VVALID stop trimmer (1/line)
0x8: –8 to 0x7: +7
0x8: –8 to 0x7: +7
Luminance Control (LUMC) <default: 0x40>
LUMC[7] Output level limiter
(Note) The limit range is from 16 to 235 at limiter ON.
*0: OFF
1: ON
LUMC[6]
Use of Pre-filter
0: Prefilter is not used.
*1: Prefilter is used.
LUMC[5:4]
Aperture bandpass select *00: middle range
01:
10:
11: high range
LUMC[3:2]
LUMC[1:0]
Coring range select
*00: coring off
01: +/–4LSB
10: +/–5LSB
11: +/–7LSB
Aperture filter weighting factor
*00:
0
01: 0.25
10: 0.75
11: 1.5
AGC/Pedestral Loop filter control (AGCLF) <default: 0x40>
AGCLF[7:6]
AGC loop filter time constant
00: slow
*01: medium
10: fast
11: fixed
AGCLF[5:0]
AGC reference level
0x20: –32 to
0x1F: +31
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Sync separation level (SSEPL) <default: 0x00>
SSEPL[7]
Pedestal clamp on/off
*0: Pedestal clamp is not used.
1: Pedestal clamp is used.
(AGC will not operate.)
SSEPL[6:0]
Sync separation level
0x40: –64 to
0x3F: +63
Chrominance Control (CHRC) <default: 0x5>
CHRC[7:4]
CHRC[7:3]
Undefined
C-Output level limiter
0: *OFF
1: ON
(Note) The limit range is from16 to 224 at limiter ON.
CHRC[2]
Chroma bandpass filter
0: OFF
*1: ON
CHRC[1:0]
Color kill threshold factor 00: 0.5 color burst level
*01: 0.25 color burst level
10: 0.125 color burst level
11: 0 (Color killer off)
ACC Loop filter control (ACCLF) <default: 0x20>
ACCLF[7]
Undefined
ACCLF[6:5]
ACC loop filter time constant
00: slow
*01: medium
10: fast
11: fixed
ACCLF[4:0]
ACC reference level
0x10: –16 to
0x0F: +15
Hue control (HUE) <default: 0x00>
HUE[7:0] Hue control
0x80: –180 degrees
to
0x7F: 178.6 degrees
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MSM7661B
Optional Mode Register (OMR) <default: 0x00>
OMR[7:6]
OMR[5:3]
Undefined
Multiplex signal detection level
(VBID etc.)
00: 80
01: 88
*10: 96
•
•
11: 136
OMR[2]
Hi-Z on Sleep for Out-pin
Signal Indicate mode
*0: Active
1: Hi-Z
OMR[1:0]
*00: NTSC/PAL
01: SOUT (Multiplex signal detect)
10: HDET (H-Sync detect)
11: Undefined
Output phase control for data Y (OPCY) <default: 0x00>
OPCY[7:3]
OPCY[2]
Undefined
YCbCr 8-bit multiplex output
*0: YCbCr 16-bit output
1: YCbCr 8-bit multiplex output
OPCY[1:0]
Output phase control for data Y *00: normal
01: forward l clock
10: Undefined
11: Undefined
Output phase control for data C (OPCC) <default: 0x00>
OPCC[7:2]
OPCC[1:0]
Undefined
Output phase control for data C *00: normal
01: forward l clock
10: Undefined
11: Undefined
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MSM7661B
FUNCTIONAL DESCRIPTION
Input Signal Level
Input signal is 8 bits in a straight binary format.
The recommended input range is shown below.
255
200
reserved
246
chrominance
+DC
Iuminance
NTSC:60
(PAL:63)
input black level
sync
13
input sync-tip level
4
0
CVBS[7:0] input range
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Output format
The YCbCr 4:2:2 format and 4:1:1 format are shown below.
The output format can be changed by register settings.
OUTPUT PIXEL BYTE SEQUENCE
OUTPUT
PIXEL BYTE SEQUENCE
Y7(MSB) Y7 Y7 Y7 Y7 Y7 Y7
Y7(MSB) Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y6 Y6 Y6 Y6 Y6 Y6
Y5 Y5 Y5 Y5 Y5 Y5
Y4 Y4 Y4 Y4 Y4 Y4
Y3 Y3 Y3 Y3 Y3 Y3
Y2 Y2 Y2 Y2 Y2 Y2
Y1 Y1 Y1 Y1 Y1 Y1
Y6
Y5
Y4
Y3
Y2
Y1
Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6
Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5
Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4
Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3
Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2
Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1
Y0(LSB) Y0 Y0 Y0 Y0 Y0 Y0
Y0(LSB) Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0
C7(MSB) Cb7 Cr7 Cb7 Cr7 Cb7 Cr7
C7(MSB) Cb7 Cb5 Cb3 Cb1 Cb7 Cb5 Cb3 Cb1
C6
C5
C4
C3
C2
C1
Cb6 Cr6 Cb6 Cr6 Cb6 Cr6
Cb5 Cr5 Cb5 Cr5 Cb5 Cr5
Cb4 Cr4 Cb4 Cr4 Cb4 Cr4
Cb3 Cr3 Cb3 Cr3 Cb3 Cr3
Cb2 Cr2 Cb2 Cr2 Cb2 Cr2
Cb1 Cr1 Cb1 Cr1 Cb1 Cr1
C6
C5
C4
C3
C2
C1
C0(LSB)
Cb6 Cb4 Cb2 Cb0 Cb6 Cb4 Cb2 Cb0
Cr7 Cr5 Cr3 Cr1 Cr7 Cr5 Cr3 Cr1
Cr6 Cr4 Cr2 Cr0 Cr6 Cr4 Cr2 Cr0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C0(LSB) Cb0 Cr0 Cb0 Cr0 Cb0 Cr0
Y point
C point
0
1
2
3
4
5
Y point
C point
0
1
2
3
4
5
6
7
0
2
4
0
4
YCbCr 4:2:2 format
YCbCr 4:1:1 format
YCbCr 8-bit multiplex output mode format
1T
CLKX2
HVALID
INVALID
Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3
Y717 Cb718 Y718 Cr718 Y719
INVALID
Y (7:0)
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MSM7661B
TIMING DESCRIPTION
A/D Converter Support Signal
The timing wave form of HSY/HCL signals, which measure the sync chip and clamp timing for
the A/D converter, is as follows.
CVBS
HSY
COLOR
BURST
A/D Converter Support Signal
Line control signal
The line control signal timing is as follows.
CLK
CLKO
HVALID
Y[7:0]
C[7:0]
Y0
Y1
Y2
Y3
Y(n)
Cb(n)
Y(n+1)
Cr(n)
Cb0
Cr0
Cb2
Cr2
Line Control Timing
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Total Number of Pixels
The total number of pixels vary depending on the mode and frequency used, as shown below
(default values when typical signals are input).
Video and Sampling Mode
Video Mode Sampling Rate
13.5 MHz
Total
Pixels
858
Active
Pixels
720
HBLK Pixels
Front-porch Hsync.Back-porch
Total
138
16
28
8
122
112
134
12.27 MHz (SQ)
NTSC
780
640
140
14.32 MHz (4FSC)
910
768
142
—
13.5 MHz
864
944
720
768
14
34
130
142
144
176
14.75 MHz (SQ)
PAL
—
—
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Vertical Synchronizing Signal
The vertical synchronizing signal timing is as follows.
524 525
1
2
3
4
5
6
7
8
9
21
22
CVBS
HVALID
HSYNC_L
VSYNC_L
SYNC
(CSYNC_L)
VVALID
ODD
262 263 264 265 266 267 268 269 270 271
283 284 285
CVBS
HVALID
HSYNC_L
VSYNC_L
SYNC
(CSYNC_L)
VVALID
ODD
Vertical Synchronizing Signal (NTSC 60 Hz)
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621 622 623 624 625
1
2
3
4
5
6
23
24
CVBS
HVALID
HSYNC_L
SYNC
(CSYNC_L)
VSYNC_L
VVALID
ODD
309 310 311 312 313 314 315 316 317 318
336 337 338
CVBS
HVALID
HSYNC_L
SYNC
(CSYNC_L)
VSYNC_L
VVALID
ODD
Vertical Synchronizing Signal (PAL 50 Hz)
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MSM7661B
Horizontal Synchronizing Signal
The horizontal synchronizing signal timing is as follows.
Y[7:0]
HVALID
HSYNC_L
60 pixels
Horizontal Timing
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MSM7661B
2
I C BUS FORMAT
2
The I C-bus interface input format is shown below.
......
S
Slave Address
A
Subaddress
A
Data 0
A
Data n
A
P
Symbol
Description
S
Start condition
Slave Address
Slave address 1000001X, 8th bit is write signal.
Acknowledge. Generated by slave
Subaddress byte
A
Subaddress
Data n
P
Data to write to address designated by subaddress.
Stop condition
As mentioned above, the write operation can be executed from subaddress to subaddress
continuously. When the write operation is executed at subaddresses discontinuously, the
Acknowledge and Stop condition formats are input repeatedly after Data 0.
If one of the following matters occurs, the decoder will not return "A" (Acknowledge).
• The slave address does not match.
• A non-existent subaddress is specified.
• The write attribute of a register does not match "X" (read/write control bit).
The input timing is shown below.
SDA
SCL
MSB
1
S
2
7
8
9
1
2
9
P
tC_SCL
ACK
3-8
ACK
Start Condition
Stop Condition
Data Line Stable: Data Valid Change of Data Allowed
2
I C-bus Basic Input/Output Timing
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MSM7661B
OPERATION MODE SETTING
The video mode includes ;
1. Internal terminal mode to be directly set by a dedicated terminal
2. Register setting mode to be specified by setting the internal registers
These modes can be changed by the mode register MRA [4].
The reset state (default) is the external terminal mode.
The following registers can be set in the external terminal mode.
MRA[3]
input signal mode
input mode
*0: Composite video input
1: S-video input
MRA[2 : 0]
*000: NTSC ITU-R601
001: NTSC Square Pixel
010: MTSC 4Fsc
13.5 MHz
12.27 MHz
14.31818 MHz
13.5 MHz
100: PAL ITU-R601
101: PAL Square Pixel
14.75 MHz
OPERATION CLOCK SETTING
The operation clock settings at ITU-R601 are shown below.
Input clock Input data CLKSEL Pin
Register (MRB2)
"0" (decimation filter used)
"1" (Unused)
Clock for A/D converter
CLKX2O (27 MHz)
27.0 MHz
27.0 MHz
13.5 MHz
27.0 MHz
13.5 MHz
13.5 MHz
"L"
"L"
"H"
CLKXO (13.5 MHz)
"1" (Unused)
CLKX2O or CLKXO (13.5 MHz)
When the double speed clock is used, data can be input at a double speed or at an ordinary speed
by setting the internal register (MRB2) and the clock for the A/D converter.
The internal processing after decimation filter is performed at an ordinary speed.
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INTERNAL REGISTERS
Register List
Data byte
Register Function
Subaddress
D7
MRA7
MRB7
D6
MRA6
MRB6
D5
MRA5
MRB5
D4
MRA4
MRB4
D3
MRA3
MRB3
D2
MRA2
MRB2
D1
MRA1
MRB1
D0
MRA0
MRB0
Mode Register A (MRA)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Mode Register B (MRB)
Horizontal Sync Trimmer (HSYT)
Sync Threshold level adjust (STHR)
Horizontal Sync Delay (HSDL)
Horizontal Valid Trimmer (HVALID)
Vertical Valid Trimmer (VVALID)
Luminance Control (LUMC)
HSYT7 HSYT6 HSYT5 HSYT4 HSYT3 HSYT2 HSYT1 HSYT0
STHR7 STHR6 STHR5 STHR4 STHR3 STHR2 STHR1 STHR0
HSDL7 HSDL6 HSDL5 HSDL4 HSDL3 HSDL2 HSDL1 HSDL0
HVALID7 HVALID6 HVALID5 HVALID4 HVALID3 HVALID2 HVALID1 HVALID0
VVALID7 VVALID6 VVALID5 VVALID4 VVALID3 VVALID2 VVALID1 VVALID0
LUMC7 LUMC6 LUMC5 LUMC4 LUMC3 LUMC2 LUMC1 LUMC0
AGCLF7 AGCLF6 AGCLF5 AGCLF4 AGCLF3 AGCLF2 AGCLF1 AGCLF0
SSEPL7 SSEPL6 SSEPL5 SSEPL4 SSEPL3 SSEPL2 SSEPL1 SSEPL0
CHRC7 CHRC6 CHRC5 CHRC4 CHRC3 CHRC2 CHRC1 CHRC0
ACCLF7 ACCLF6 ACCLF5 ACCLF4 ACCLF3 ACCLF2 ACCLF1 ACCLF0
AGC/Pedestal Loop Filter Control (AGCLF)
Sync separation level (SSEPL)
Chrominance Control (CHRC)
ACC Loop Filter Control (ACCLF)
Hue Control (HUE)
HUE7
HUE6
HUE5
HUE4
HUE3
HUE2
HUE1
HUE0
Optional Mode Register (OMR)
Output Phase Control for Data Y (OPCY)
Output Phase Control for Data C (OPCC)
OMR7
OMR6
OMR5
OMR4
OMR3
OMR2
OMR1
OMR0
OPCY7 OPCY6 OPCY5 OPCY4 OPCY3 OPCY2 OPCY1 OPCY0
OPCC7 OPCC6 OPCC5 OPCC4 OPCC3 OPCC2 OPCC1 OPCC0
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Relationship between Register Setting Value and Adjusted Value
Horizontal Sync Trimmer
Position adjustment of sync chip clamp timing signal
HSYT [7:4]
:Adjusting the starting position
Register Setting Value (Ox)
C
D
E
F
0
0
1
2
3
4
5
6
7
8
9
A
B
Adjusted Value (Pixel) –32 –24 –16 –8
+8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
HSYT [3:0]
:Adjusting the end position
Register Setting Value (Ox)
C
D
E
F
0
0
1
2
3
4
5
6
7
8
9
A
B
Adjusted Value (Pixel) –32 –24 –16 –8
+8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
Horizontal Sync Delay
Adjustment of the starting position of horizontal sync signal
HSDL [7:0]
MSB[7 : 4]
8
9
A
B
C
D
E
F
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–512 –448 –384 –320 –256 –192 –128 –64
+64 +128 +192 +256 +320 +384 +448
–508 –444 –380 –316 –252 –188 –124 –60 +4 +68 +132 +196 +260 +324 +388 +452
–504 –440 –376 –312 –248 –184 –120 –56 +8 +72 +136 +200 +264 +328 +392 +456
–500 –436 –372 –308 –244 –180 –116 –52 +12 +76 +140 +204 +268 +332 +396 +460
–496 –432 –368 –304 –240 –176 –112 –48 +16 +80 +144 +208 +272 +336 +400 +464
–492 –428 –364 –300 –236 –172 –108 –44 +20 +84 +148 +212 +276 +340 +404 +468
–488 –424 –360 –296 –232 –168 –104 –40 +24 +88 +152 +216 +280 +344 +408 +472
–484 –420 –356 –292 –228 –164 –100 –36 +28 +92 +156 +220 +284 +348 +412 +476
–480 –416 –352 –288 –224 –160 –96 –32 +32 +96 +160 +224 +288 +352 +416 +480
–476 –412 –348 –284 –220 –156 –92 –28 +36 +100 +164 +228 +292 +356 +420 +484
–472 –408 –344 –280 –216 –152 –88 –24 +40 +104 +168 +232 +296 +360 +424 +488
–468 –404 –340 –276 –212 –148 –84 –20 +44 +108 +172 +236 +300 +364 +428 +492
–464 –400 –336 –272 –208 –144 –80 –16 +48 +112 +176 +240 +304 +368 +432 +496
–460 –396 –332 –268 –204 –140 –76 –12 +52 +116 +180 +244 +308 +372 +436 +500
–456 –392 –328 –264 –200 –136 –72 –8 +56 +120 +184 +248 +312 +376 +440 +504
–452 –388 –324 –260 –196 –132 –68 –4 +60 +124 +188 +252 +316 +380 +444 +508
LSB
[3 : 0]
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MSM7661B
Horizontal Valid Trimmer
Position adjustment of horizontal valid pixel timing signal
HVALT [7:4]
:Adjusting the starting position
Register Setting Value (Ox)
8
9
A
B
C
D
E
F
0
0
1
2
3
4
5
6
7
Adjusted Value (Pixel) –8 –7 –6 –5 –4 –3 –2 –1
+1 +2 +3 +4 +5 +6 +7
HVALT [3:0]
:Adjusting the end position
Register Setting Value (Ox)
8
9
A
B
C
D
E
F
0
0
1
2
3
4
5
6
7
Adjusted Value (Pixel) –8 –7 –6 –5 –4 –3 –2 –1
+1 +2 +3 +4 +5 +6 +7
Vertical Valid Trimmer
Position adjustment of vertical valid line timing signal
VVALT [7:4]
:Adjusting the starting position
Register Setting Value (Ox)
8
9
A
B
C
D
E
F
0
0
1
2
3
4
5
6
7
Adjusted Value (Line) –8 –7 –6 –5 –4 –3 –2 –1
+1 +2 +3 +4 +5 +6 +7
VVALT [3:0]
:Adjusting the end position
Register Setting Value (Ox)
8
9
A
B
C
D
E
F
0
0
1
2
3
4
5
6
7
Adjusted Value (Line) –8 –7 –6 –5 –4 –3 –2 –1
+1 +2 +3 +4 +5 +6 +7
AGC Loop filter control
AGCLF [5:0]
:Adjusting sync level
Register Setting
Value
MSB [5 : 4]
2
3
0
0
1
(Ox)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–32 –16
+16
–31 –15 +1 +17
–30 –14 +2 +18
–29 –13 +3 +19
–28 –12 +4 +20
–27 –11 +5 +21
–26 –10 +6 +22
LSB
–25 –9
–24 –8
–23 –7
+7 +23
+8 +24
+9 +25
[3 : 0]
–22 –6 +10 +26
–21 –5 +11 +27
–20 –4 +12 +28
–19 –3 +13 +29
–18 –2 +14 +30
–17 –1 +15 +31
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Sync separation level
SSEPL [6:0]
:Adjusting the blanking level
Register Setting
Value
MSB [6 : 4]
4
5
6
7
0
0
1
2
3
(Ox)
0
1
2
3
4
5
6
–64 –48 –32 –16
+16 +32 +48
–63 –47 –31 –15 +1 +17 +33 +49
–62 –46 –30 –14 +2 +18 +34 +50
–61 –45 –29 –13 +3 +19 +35 +51
–60 –44 –28 –12 +4 +20 +36 +52
–59 –43 –27 –11 +5 +21 +37 +53
–58 –42 –26 –10 +6 +22 +38 +54
LSB
7
8
9
A
B
C
D
E
F
–57 –41 –25 –9
–56 –40 –24 –8
–55 –39 –23 –7
+7 +23 +39 +55
+8 +24 +40 +56
+9 +25 +41 +57
[3 : 0]
–54 –38 –22 –6 +10 +26 +42 +58
–53 –37 –21 –5 +11 +27 +43 +59
–52 –36 –20 –4 +12 +28 +44 +60
–51 –35 –19 –3 +13 +29 +45 +61
–50 –34 –18 –2 +14 +30 +46 +62
–49 –33 –17 –1 +15 +31 +47 +63
ACC Loop filter control
ACCLF [4:0]
:Adjusting the color burst level
Register Setting
MSB [4]
Value
1
0
0
(Ox)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–16
–15 +1
–14 +2
–13 +3
–12 +4
–11 +5
–10 +6
LSB
–9
–8
–7
+7
+8
+9
[3 : 0]
–6 +10
–5 +11
–4 +12
–3 +13
–2 +14
–1 +15
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MSM7661B
Hue control
Adjustment of color subcarrier phase
HUE [7:0]
Register Setting
Value
MSB [7 : 4]
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
(Ox)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–180.0 –157.5 –135.0 –112.5 –90.0
–178.6 –156.1 –133.6 –111.1 –88.6
–177.2 –154.7 –132.2 –109.7 –87.2
–175.8 –153.3 –130.8 –108.3 –85.8
–174.4 –151.9 –129.4 –106.9 –84.4
–173.0 –150.5 –128.0 –105.5 –83.0
–171.6 –149.1 –126.6 –104.1 –81.6
–170.2 –147.7 –125.2 –102.7 –80.2
–168.8 –146.3 –123.8 –101.3 –78.8
–67.5
–66.1
–64.7
–63.3
–61.9
–60.5
–59.1
–57.7
–56.3
–54.8
–53.4
–52.0
–50.6
–49.2
–47.8
–46.4
–45.0
–43.6
–42.2
–40.8
–39.4
–38.0
–36.6
–35.2
–33.8
–32.3
–30.9
–29.5
–28.1
–26.7
–25.3
–23.9
–22.5
–21.1
–19.7
–18.3
–16.9
–15.5
–14.1
–12.7
–11.3
–9.8
+0.0
+22.5
+23.9
+25.3
+26.7
+28.1
+29.5
+30.9
+32.3
+33.8
+35.2
+36.6
+38.0
+39.4
+40.8
+42.2
+43.6
+45.0
+46.4
+47.8
+49.2
+50.6
+52.0
+53.4
+54.8
+56.3
+57.7
+59.1
+60.5
+61.9
+63.3
+64.7
+66.1
+67.5
+68.9
+70.3
+71.7
+73.1
+74.5
+75.9
+77.3
+90.0 +112.5 +135.0 +157.5
+91.4 +113.9 +136.4 +158.9
+92.8 +115.3 +137.8 +160.3
+94.2 +116.7 +139.2 +161.7
+95.6 +118.1 +140.6 +163.1
+97.0 +119.5 +142.0 +164.5
+98.4 +120.9 +143.4 +165.9
+99.8 +122.3 +144.8 +167.3
+1.4
+2.8
+4.2
+5.6
+7.0
+8.4
LSB
+9.8
[3 : 0]
+11.3
+12.7
+14.1
+15.5
+16.9
+18.3
+19.7
+21.1
+78.8 +101.3 +123.8 +146.3 +168.8
+80.2 +102.7 +125.2 +147.7 +170.2
+81.6 +104.1 +126.6 +149.1 +171.6
+83.0 +105.5 +128.0 +150.5 +173.0
+84.4 +106.9 +129.4 +151.9 +174.4
+85.8 +108.3 +130.8 +153.3 +175.8
+87.2 +109.7 +132.2 +154.7 +177.2
+88.6 +111.1 +133.6 +156.1 +178.6
–167.3 –144.8 –122.3 –99.8
–165.9 –143.4 –120.9 –98.4
–164.5 –142.0 –119.5 –97.0
–163.1 –140.6 –118.1 –95.6
–161.7. –139.2 –116.7 –94.2
–160.3 –137.8 –115.3 –92.8
–158.9 –136.4 –113.9 –91.4
–77.3
–75.9
–74.5
–73.1
–71.7
–70.3
–68.9
–8.4
–7.0
–5.6
–4.2
–2.8
–1.4
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¡ Semiconductor
MSM7661B
Filter Characteristics
Band Pass Filter (NTSC ITU-R601)
0
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
Frequency [MHz]
Band Pass Filter (PAL ITU-R601)
0
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
Frequency [MHz]
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¡ Semiconductor
MSM7661B
Trap Filter (NTSC ITU-R601)
0
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
Frequency [MHz]
Trap Filter (PAL ITU-R601)
0
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
Frequency [MHz]
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¡ Semiconductor
MSM7661B
Pre Filter
0
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
Frequency [MHz]
Sharp Filter
0
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
Frequency [MHz]
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¡ Semiconductor
MSM7661B
Decimation Filter
0
–20
–40
–60
–80
–100
0
2
4
6
8
10
12
Frequency [MHz]
*
The characteristics of the various filters shown above are based on design data.
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¡ Semiconductor
MSM7661B
BASIC APPLICATION CIRCUIT EXAMPLE
Application 1
Mode setting
Video signal: NTSC-composite
CLKX2: 27 MHz
3.3 V
I2C
Controller
Video in
8
8
8
CVBS0
CVBS7
LPF1
A/D C
Frame
memory
or
8
Input circuit
CD0
CD7
MSM7661B
image LSI
CLKXO2
SYNC
HVALID
VVALID
ODD
VC0_CP
CLKXO
CLKX2
OSC
L L L L
Dip SW
3.3 V
A/D C: CXD1179Q (SONY)
LPF1: 628LJN-1471 (TOKO)
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¡ Semiconductor
MSM7661B
Application 2
Mode setting
Video signal: NTSC-composite
CLKX2: 13.5 MHz
3.3 V
I2C
Controller
Video in
8
8
8
CVBS0
CVBS7
LPF1
A/D C
Frame
memory
or
8
Input circuit
CD0
CD7
MSM7661B
image LSI
CLKXO2
SYNC
HVALID
VVALID
ODD
VC0_CP
CLKXO
CLKX2
OSC
L L L L
Dip SW
3.3 V
A/D C: upc659 (NEC)
LPF1: 628LJN-1471 (TOKO)
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¡ Semiconductor
MSM7661B
PACKAGE OUTLINES AND DIMENSIONS
(Unit : mm)
64-Pin Plastic QFP
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相关型号：
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