MSM7702-02GS-K [OKI]
PCM Codec, MU-Law, 1-Func, CMOS, PDSO24, PLASTIC, SOP-24;
| 型号： | MSM7702-02GS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | PCM Codec, MU-Law, 1-Func, CMOS, PDSO24, PLASTIC, SOP-24 PC 光电二极管 |
| 文件： | 总17页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0018-28-81
This version: Aug. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7702-01/02/03
Single Rail CODEC
GENERAL DESCRIPTION
The MSM7702 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for telephone terminals in digital wireless systems or ISDN systems.
The MSM7702 utilizes low-voltage operational amplifiers (Op-amps) to provide low-power
consumption.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal can directly drive a piezoelectric type handset receiver.
FEATURES
• Single power supply: +2.7 V to +3.8 V
• Low power consumption
Operating mode:
Power save mode:
Power down mode:
• ITU-T Companding law
15 mW Typ.
3.6 mW Typ.
0.05 mW Typ.
V
DD
V
DD
V
DD
= 3 V
= 3 V
= 3 V
MSM7702-01: m/A-law pin selectable
MSM7702-02: m-law
MSM7702-03: A-law
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
• Adjustable transmit gain
• Built-in reference voltage supply
• Analog output can directly drive a load equivalent to 1.2 kW
• Pin-for-pin compatible with the MSM7578 and MSM7579
• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name : MSM7702-01GS-K)
(Product name : MSM7702-02GS-K)
(Product name : MSM7702-03GS-K)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7702-01MS-K)
(Product name : MSM7702-02MS-K)
(Product name : MSM7702-03MS-K)
1/17
¡ Semiconductor
MSM7702-01/02/03
BLOCK DIAGRAM
PCMOUT
–
+
AIN–
AIN+
RC
8th
AD
TCONT
PLL
LPF
BPF
CONV.
GSX
XSYNC
BCLK
AUTO
ZERO
SGC
SG
SG
GEN
VR
GEN
RTIM
RSYNC
(ALAW)
5th
LPF
DA
CONV.
–
+
RCONT
AOUT
PCMIN
PDN
SG
PWD
Logic
PWD
VDD
AG
DG
2/17
¡ Semiconductor
MSM7702-01/02/03
PIN CONFIGURATION (TOP VIEW)
SGC 1
NC 2
24 AIN+
23 AIN–
22 NC
SGC 1
SG 2
20 AIN+
19 AIN–
18 GSX
SG 3
AOUT 3
NC 4
21 GSX
20 NC
V
DD
4
17 (ALAW)*
16 NC
AOUT 5
NC 5
NC 6
V
DD
6
19 (ALAW)*
18 AG
15 NC
DG 7
NC 8
DG 7
14 AG
17 NC
PDN 8
13 BCLK
12 XSYNC
11 PCMOUT
NC 9
16 BCLK
15 NC
RSYNC 9
PCMIN 10
PDN 10
RSYNC 11
PCMIN 12
14 XSYNC
13 PCMOUT
NC : No connect pin
20-Pin Plastic SSOP
NC : No connect pin
24-Pin Plastic SOP
* The ALAW pin is only applied to the MSM7702-01GS-K/MSM7702-01MS-K.
3/17
¡ Semiconductor
MSM7702-01/02/03
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.
1) Inverting input type
R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)
GSX
AIN–
AIN+
SG
C1
R2
–
+
Analog input
R1
Gain = R2/R1 £ 10
2) Non inverting input type
C2
R3 > 20 kW
AIN+
AIN–
GSX
+
–
Analog input
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)
R5
R4
R3
SG
Gain = 1 + R4 / R3 £ 10
AG
Analog signal ground.
AOUT
Analog output.
The output signal has a maximum amplitude of 2.0 V above and below the signal ground
PP
voltage (V /2).
DD
The output load resistance is a minimum of 1.2 kW.
During power saving or power down mode, the output of AOUT is at the voltage level of the
signal ground.
4/17
¡ Semiconductor
MSM7702-01/02/03
V
DD
Power supply for +2.7 V to +3.8 V. (Typically 3.0 V)
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
ThePCMsignalisshiftedatafallingedgeoftheBCLKsignalandlatchedintotheinternalregister
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the
AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.
5/17
¡ Semiconductor
MSM7702-01/02/03
DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.
PDN
Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.
PCMOUT
PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down.
Apull-upresistormustbeconnectedtothispinbecauseitsoutputisconfiguredasanopendrain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7702-03 (A-law) outputs the character signal, inverting the even bits.
PCMIN/PCMOUT
Input/Output Level
MSM7702-02 (m-law)
MSM7702-03 (A-law)
MSD
MSD
+Full scale
+0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
–0
–Full scale
6/17
¡ Semiconductor
MSM7702-01/02/03
SG
Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is ±200 mA.
This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down mode.
SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
ALAW
Control signal input for the companding law selection.
Provides only for the MSM7702-01GS-K/7702-01MS-K. The CODEC will operate in the m-law
when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at
alogic"1"level. TheCODECoperatesinthem-lawifthepinisleftopen, sincethispinisinternally
pulled down.
7/17
¡ Semiconductor
MSM7702-01/02/03
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
Rating
0 to 7
Unit
V
—
—
—
—
VAIN
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–55 to +150
V
VDIN
TSTG
V
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Analog Input Voltage
Symbol
VDD Voltage must be fixed
Ta
Condition
Min.
Typ.
3.0
Max.
Unit
V
2.7
–30
—
3.8
+85
1.4
—
+25
—
°C
VAIN Connect AIN– and GSX
VPP
Input High Voltage
Input Low Voltage
VIH
0.45 ¥ VDD
—
—
VDD
V
V
XSYNC, RSYNC, BCLK,
PCMIN, PDN, ALAW
VIL
0
0.16 ¥ VDD
64, 128, 256, 512, 1024,
2048, 96, 192, 384, 768,
1536, 1544, 200
Clock Frequency
FC
BCLK
kHz
Sync Pulse Frequency
Clock Duty Ratio
FS
DC
tIr
XSYNC, RSYNC
6.0
40
8.0
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10.0
60
kHz
%
BCLK
Digital Input Rise Time
Digital Input Fall Time
XSYNC, RSYNC, BCLK,
PCMIN, PDN, ALAW
—
50
ns
tIf
—
50
ns
tXS
tSX
tRS
tSR
BCLKÆXSYNC, See Timing Diagram
XSYNCÆBCLK, See Timing Diagram
BCLKÆRSYNC, See Timing Diagram
RSYNCÆBCLK, See Timing Diagram
100
100
100
100
1 BCLK
100
100
0.5
—
ns
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
—
ns
—
ns
—
ns
Sync Pulse Width
PCMIN Set-up Time
PCMIN Hold Time
tWS XSYNC, RSYNC
100
—
ms
ns
tDS
tDH
—
—
—
ns
RDL Pull-up resistor
—
kW
pF
Digital Output Load
CDL
Voff
—
—
—
100
+100
+10
1
Transmit gain stage, Gain = 1
Transmit gain stage, Gain = 10
XSYNC, RSYNC, BCLK
–100
–10
—
mV
mV
ms
Analog Input Allowable DC Offset
Allowable Jitter Width
8/17
¡ Semiconductor
MSM7702-01/02/03
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Symbol
Condition
Min.
—
Typ.
5
Max.
9
Unit
mA
IDD1 Operating mode, No signal
IDD2 Power-down mode, PDN = 0
—
0.01
0.05
mA
Power Supply Current
Power-save mode, PDN = 1,
IDD3
—
1.2
—
—
3.0
mA
V
XSYNC Æ OFF
0.45 ¥
Input High Voltage
Input Low Voltage
VIH
VIL
—
—
VDD
VDD
0.16 ¥
VDD
2.0
0.5
0.4
10
0.0
V
High Level Input Leakage Current
Low Level Input Leakage Current
Digital Output Low Voltage
Digital Output Leakage Current
Input Capacitance
IIH
IIL
—
—
—
—
0.0
—
—
—
—
—
0.2
—
5
mA
mA
V
VOL Pull-up resistance > 500 W
IO
PCMOUT
mA
pF
CIN
—
—
Analog Input Resistance
RIN AIN+, AIN–
10
—
MW
Transmit Analog Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Input Resistance
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
MW
kW
pF
RINX AIN+, AIN–
Output Load Resistance
Output Load Capacitance
Output Amplitude
RLGX GSX with respect to SG
20
—
—
CLGX
VOGX
—
—
30
–0.7
–20
—
+0.7
+20
V
Offset Voltage
VOSGX
Gain = 1
—
mV
Receive Analog Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Output Load Resistance
Output Load Capacitance
Output Amplitude
Symbol
Condition
Min.
1.2
Typ.
—
Max.
—
Unit
kW
pF
RLAO AOUT with respect to SG
CLAO AOUT with respect to SG
VOAO AOUT with respect to SG
VOSAO AOUT with respect to SG
—
—
50
–1.0
–100
—
+1.0
+100
V
Offset Voltage
—
mV
9/17
¡ Semiconductor
AC Characteristics
Parameter
MSM7702-01/02/03
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Freq.
(Hz)
Level
(dBm0)
Symbol
Condition Min.
Typ.
Max.
Unit
Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
LossR1
LossR2
LossR3
LossR4
LossR5
SD T1
SD T2
SD T3
60
300
20
26
+0.1
Reference
–0.04
+0.13
0.5
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
–0.15
+0.20
1020
2020
3000
3400
300
Transmit Frequency Response
Receive Frequency Response
0
0
–0.15
–0.15
0
+0.20
+0.20
0.80
–0.15
–0.04
Reference
+0.02
+0.10
0.47
43
+0.20
1020
2020
3000
3400
–0.15
–0.15
0.0
+0.20
+0.20
0.80
—
3
0
35
35
41
—
–30
*1
35
37
—
Transmit Signal to Distortion Ratio
1020
29.5
29
dB
SD T4
SD T5
–40
–45
*2
*2
28
—
—
25
23
24
SD R1
SD R2
SD R3
3
0
36
36
43
—
—
—
41
–30
*1
36
40
Receive Signal to Distortion Ratio
1020
dB
30
33.5
32
SD R4
SD R5
–40
–45
*2
*2
—
29
25
30
—
24
27
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
3
–0.3
0
+0.3
–10
–40
–50
–55
3
Reference
+0.1
–0.03
0
Transmit Gain Tracking
1020
1020
–0.3
–0.5
–1.2
–0.3
+0.3
+0.6
+1.2
+0.3
dB
dB
0.0
–10
–40
–50
–55
Reference
+0.11
+0.22
+0.15
Receive Gain Tracking
–0.3
–0.6
–1.2
+0.3
+0.6
+1.2
*1 Psophometric filter is used
*2 Upper is specified for the m-law, lower for the A-law
10/17
¡ Semiconductor
MSM7702-01/02/03
AC Characteristics (Continued)
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
Unit
AIN = SG
—
Nidle T
—
—
—
—
–70.5
–68
Idle Channel Noise
*1
dBmOp
NidleR
AV T
*1 *3
VDD = 3.0 V
Ta = 25°C
—
–78
–74
0.338
0.35
0.362
Absolute Level (Initial Difference)
Vrms
AV R
AV Tt
0.483
–0.2
0.50
—
0.518
+0.2
1020
1020
0
VDD = +2.7
dB
dB
Absolute Level
to 3.8 V
Ta = –30
to 85°C
A to A
BCLK
(Deviation of Temperature and Power)
AV Rt
Td
–0.2
—
—
—
+0.2
0.60
Absolute Delay
0
0
ms
ms
= 64 kHz
tgd T1
tgd T2
tgd T3
tgd T4
tgd T5
tgdR1
tgdR2
tgdR3
tgdR4
tgdR5
CR T
500
600
*4
—
—
—
—
—
—
—
—
—
—
75
70
0.19
0.11
0.02
0.05
0.07
0.00
0.00
0.00
0.09
0.12
85
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
—
Transmit Group Delay
1000
2600
2800
500
*4
600
Receive Group Delay
1000
2600
2800
0
0
ms
dB
TRANS Æ RECV
RECV Æ TRANS
Crosstalk Attenuation
1020
CR R
80
—
*1 Psophometric filter is used
*2 Upper is specified for the m-law, lower for the A-law
*3 m-law: All "1", A-law: "11010101"
*4 Minimum value of the group delay distortion
11/17
¡ Semiconductor
MSM7702-01/02/03
AC Characteristics (Continued)
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Freq.
(Hz)
4.6 kHz to
72 kHz
300 to
3400
Level
(dBm0)
Parameter
Discrimination
Symbol
Condition Min.
Typ.
32
Max.
—
Unit
dB
0 to
DIS
S
0
0
30
4000 Hz
4.6 kHz to
—
Out-of-band Spurious
–37.5
–52
30
–35
–35
—
dBmO
dBmO
dB
100 kHz
fa = 470
fb = 320
0 to
Intermodulation Distortion
Power Supply Noise Rejection Ratio
IMD
–4
2fa – fb
*5
—
—
PSR T
50 mVPP
PSR R 50 kHz
t
20
20
20
20
—
—
—
—
200
200
200
200
SD
t
XD1
XD2
XD3
Digital Output Delay Time
CL = 100 pF
ns
t
t
*5 The measurement under idle channel noise
12/17
¡ Semiconductor
MSM7702-01/02/03
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing
BCLK
XSYNC
1
2
3
4
5
6
7
8
9
10
11
tXS
tSX
tWS
tXD1
tSD
MSD
tXD2
D3
tXD3
D8
PCMOUT
D2
D4
D5
D6
D7
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1
When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD
.
.
Receive Timing
BCLK
1
2
3
4
5
6
7
8
9
10
11
tRS
tSR
tWS
RSYNC
PCMIN
tDS
tDH
MSD
D2
D3
D4
D5
D6
D7
D8
13/17
¡ Semiconductor
MSM7702-01/02/03
APPLICATION CIRCUIT
Analog interface
Digital interface
1 kW
MSM7702
+3 V
Analog input
AIN–
PCMOUT
PCM signal output
GSX
AOUT
PCMIN
BCLK
Analog output
PCM data input
AIN+
SG
PCM shift clock input
0.1 mF
XSYNC
RSYNC
PDN
8 kHz SYNC signal input
Power Down control input
SGC
AG
DG
0 V
–
+
10 mF 1 mF
"1" = Operation
"0" = Power down
+3 V
VDD
0 to 10 W
Theanalogoutputsignalhasamaximumamplitudeof±1.0Vaboveandbelowtheoffsetvoltage
level of V /2.
DD
14/17
¡ Semiconductor
MSM7702-01/02/03
RECOMMENDATIONS FOR ACTUAL DESIGN
• Toassureproperelectricalcharacteristics,usebypasscapacitorswithexcellenthighfrequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.
• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-
DD
up phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
powersupplytoavoiderroneousoperationandthedegradationofthecharacteristicsofthese
devices.
15/17
¡ Semiconductor
PACKAGE DIMENSIONS
SOP24-P-430-1.27-K
MSM7702-01/02/03
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/17
¡ Semiconductor
MSM7702-01/02/03
(Unit : mm)
SSOP20-P-250-0.95-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.18 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/17
相关型号：
MSM7704-01GS-K
PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24
OKI
MSM7704-03GS-K
PCM Codec, A-Law, 1-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24
OKI
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