MSM7717-01MS-K [OKI]
PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO20, 0.250 INCH, 0.95 MM PITCH, PLASTIC, SSOP-20;
| 型号： | MSM7717-01MS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO20, 0.250 INCH, 0.95 MM PITCH, PLASTIC, SSOP-20 PC 电信 光电二极管 电信集成电路 |
| 文件： | 总19页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0041-28-81
This version: Aug. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7717-01/02/03
Single Rail CODEC
GENERAL DESCRIPTION
The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for ISDN terminals and telephone terminals in digital wireless systems.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output, which can drive a 1.2 kW load, can directly drive a handset receiver
differentially.
FEATURES
• Single power supply: 2.7 V to 3.8 V
• Low power consumption
Operating mode:
Power-down mode:
20 mW Typ.
0.03 mW Typ.
V
DD
V
DD
= 3 V
= 3 V
• Conforms to ITU-T Companding law
MSM7717-01: m/A-law pin selectable
MSM7717-02: m-law
MSM7717-03: A-law
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024 kHz
96/192/384/768/1536/1544/2048/200 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name: MSM7717-01GS-K)
(Product name: MSM7717-02GS-K)
(Product name: MSM7717-03GS-K)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K)
(Product name: MSM7717-02MS-K)
(Product name: MSM7717-03MS-K)
1/19
¡ Semiconductor
MSM7717-01/02/03
BLOCK DIAGRAM
PCMOUT
–
+
AIN–
AIN+
RC
LPF
8th
AD
TCONT
PLL
BPF
CONV.
GSX
XSYNC
BCLK
AUTO
ZERO
SGC
SG
SG
VR
GEN
GEN
RTIM
RSYNC
(ALAW)
5th
LPF
DA
–
+
CONV.
VFRO
SG
RCONT
PCMIN
PWI
–
+
AOUT–
SG
SG
PWD
PDN
VDD
AG
PWD
Logic
–
+
AOUT+
DG
2/19
¡ Semiconductor
MSM7717-01/02/03
PIN CONFIGURATION (TOP VIEW)
SG 1
AOUT+ 2
AOUT– 3
NC 4
24 SGC
23 AIN+
22 AIN–
21 GSX
20 NC
SG 1
AOUT+ 2
AOUT– 3
PWI 4
20 SGC
19 AIN+
18 AIN–
17 GSX
PWI 5
VFRO 5
16 NC
VDD
VFRO 6
NC 7
19 NC
6
15 (ALAW)*
14 AG
18 (ALAW)*
17 NC
DG 7
PDN 8
V
DD
8
13 BCLK
12 XSYNC
11 PCMOUT
DG 9
PDN 10
16 AG
RSYNC 9
PCMIN 10
15 BCLK
14 XSYNC
13 PCMOUT
RSYNC 11
PCMIN 12
NC : No connect pin
20-Pin Plastic SSOP
NC : No connect pin
24-Pin Plastic SOP
* The ALAW pin is only supported by the MSM7717-01GS-K/MSM7717-01MS-K.
3/19
¡ Semiconductor
MSM7717-01/02/03
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp.
The level adjustment should be performed in any method shown below. When not using AIN–
and AIN+, connect AIN– to GSX and AIN+ to SG. During power-saving and power-down
modes, the GSX output is at AG voltage.
1) Inverting input type
R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F)
GSX
AIN–
AIN+
SG
C1
R2
–
+
Analog input
R1
Gain = R2/R1 < 10
2) Noninverting input type
C2
R3 > 20 kW
AIN+
AIN–
GSX
+
–
Analog input
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) (F)
R5
R4
R3
SG
Gain = 1 + R4 / R3 £ 10
AG
Analog signal ground.
VFRO
Receive filter output.
The output signal has an amplitude of 2.0 V above and below the signal ground voltage (SG)
PP
when the digital signal of +3 dBm0 is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
During power-saving mode this output is in a high impedance state, and during power-down
mode, the VFRO output is at an SG level.
Whenadjustingthereceivesignalonthebasisoffrequencycharacteristics, refertotheFrequency
Characteristics Adjustment Circuit.
4/19
¡ Semiconductor
MSM7717-01/02/03
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to
the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted
with respect to the output of AOUT–. Since these outputs provide differential drive of an
impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a
piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being
activated during the power-saving mode, the amplifiers can output other external signals from
AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during
the power-down mode.
VI
External Signal Input
R6
R6 > 20 kW
VFRO
PWI
Receive filter
R7
Gain = VO/VI = R7/R6 £ 1
–
+
AOUT–
Analog output
SG
VO
ZL ZL > 1.2 kW
–
+
AOUT+
Analog inverted output
SG
V
DD
Power supply for 2.7 V to 3.8 V. (Typically 3.0 V)
PCMIN
PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive
driveramplifiersare intheoperatingmodeandtheothercircuitsareinthenon-operatingmode.
5/19
¡ Semiconductor
MSM7717-01/02/03
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the
AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
XSYNC
Transmit synchronizing signal input.
ThePCMoutputsignalfromthePCMOUTpinisoutputinsynchronizationwiththis signal. This
synchronizingsignaltriggersthePLLandsynchronizesalltimingsignalsofthetransmitsection.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
operates in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.
6/19
¡ Semiconductor
MSM7717-01/02/03
DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground AG. The DG pin must be connected to the
AG pin on the printed circuit board to make a common analog ground AG.
PDN
Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.
PCMOUT
PCM signal output.
Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from
MSD in a sequential order.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
Apull-upresistormustbeconnectedtothispinbecauseitsoutputisconfiguredasanopendrain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7717-03 (A-law) outputs the character signal, inverting the even bits.
PCMIN/PCMOUT
Input/Output Level
MSM7717-02 (m-law)
MSM7717-03 (A-law)
MSD
MSD
+Full scale
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
+0
–0
–Full scale
7/19
¡ Semiconductor
MSM7717-01/02/03
SG
Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is ±200 mA.
This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power-saving or power-down mode.
SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
ALAW
Control signal input of the companding law selection.
Only the MSM7717-01GS-K/7717-01MS-K has this pin. The CODEC will operate in the m-law
when this pin is at a logic "0" level and the CODEC will has this pin operate in the A-law when
this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the
pin is internally pulled down.
8/19
¡ Semiconductor
MSM7717-01/02/03
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
Rating
Unit
V
—
—
—
—
–0.3 to +7
VAIN
–0.3 to V + 0.3
DD
–0.3 to V + 0.3
DD
V
VDIN
TSTG
V
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Analog Input Voltage
Symbol
Condition
VDD Voltage must be fixed
Ta
Min.
Typ.
3.0
+25
—
Max.
Unit
V
2.7
–30
3.8
+85
—
°C
VPP
V
VAIN Connect AIN– and GSX
VIH XSYNC, RSYNC, BCLK,
—
1.4
High Level Input Voltage
Low Level Input Voltage
0.45¥VDD
0
—
VDD
PCMIN, PDN, ALAW
VIL
—
0.16¥VDD
V
64, 128, 256, 512, 1024,
2048, 96, 192, 384, 768,
1536, 1544, 200
Clock Frequency
FC BCLK
kHz
Sync Pulse Frequency
Clock Duty Ratio
FS XSYNC, RSYNC
DC BCLK
6.0
40
8.0
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
60
kHz
%
Digital Input Rise Time
Digital Input Fall Time
tlr
tlf
XSYNC, RSYNC, BCLK,
PCMIN, PDN, ALAW
—
50
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
kW
pF
mV
mV
ns
—
50
tXS BCLKÆXSYNC, See Fig. 1
tSX XSYNCÆBCLK, See Fig. 1
tRS BCLKÆRSYNC, See Fig. 1
tSR RSYNCÆBCLK, See Fig. 1
tWSH XSYNC, RSYNC, See Fig. 1
tWSL XSYNC, RSYNC, See Fig. 1
tDS See Timing Diagram
100
100
100
100
1 BCLK
1 BCLK
100
100
0.5
—
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
—
—
—
High Level Sync Pulse Width
Low Level Sync Pulse Width
PCMIN Setup Time
—
—
—
PCMIN Hold Time
tDH See Timing Diagram
—
RDL Pull-up resistor
—
Digital Output Load
CDL
Voff
—
—
—
100
+100
+10
1000
Transmit gain stage, Gain = 1
Transmit gain stage, Gain = 10
XSYNC, RSYNC, BCLK
–100
–10
—
Analog Input Allowable DC Offset
Allowable Jitter Width
9/19
¡ Semiconductor
MSM7717-01/02/03
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Symbol
Condition
Min.
—
Typ.
10
Max.
14
Unit
Operating mode
No signal
VDD = 3.8 V
VDD = 3.0 V
IDD1
mA
—
6.5
10.0
Power-saving mode, PDN = 1,
BCLK or XSYNC Æ OFF
Power-down mode, PDN = 0,
BCLK OFF
Power Supply Current
IDD2
IDD3
VIH
—
—
2.0
0.005
—
8.0
0.05
mA
mA
V
XSYNC, RSYNC, BCLK,
PCMIN, PDN, ALAW
XSYNC, RSYNC, BCLK,
PCMIN, PDN, ALAW
—
High Level Input Voltage
Low Level Input Voltage
0.45¥VDD
0.0
VDD
VIL
—
0.16¥VDD
V
High Level Input Leakage Current
Low Level Input Leakage Current
Digital Output Low Voltage
Digital Output Leakage Current
Input Capacitance
IIH
IIL
—
—
0.0
—
—
—
—
0.2
—
5
2.0
0.5
0.4
10
mA
mA
V
—
VOL Pull-up resistor > 500 W
IO
—
—
mA
pF
CIN
—
10/19
¡ Semiconductor
MSM7717-01/02/03
Transmit Analog Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Input Resistance
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
MW
kW
pF
RINX AIN+, AIN–
Output Load Resistance
Output Load Capacitance
Output Amplitude
RLGX GSX with respect to SG
20
—
—
CLGX
VOGX
—
—
30
–0.7
–20
—
+0.7
+20
V
Offset Voltage
VOSGX
Gain = 1
—
mV
Receive Analog Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Input Resistance
Symbol
Condition
Min.
10
Typ.
—
Max.
—
Unit
MW
kW
RINPW PWI
RLVF VFRO with respect to SG
20
—
—
Output Load Resistance
Output Load Capacitance
AOUT+, AOUT– (each) with
RLAO
0.6
—
—
kW
respect to SG
CLVF VFRO
—
—
—
—
30
50
pF
pF
CLAO AOUT+, AOUT–
VFRO, RL = 20 kW with
VOVF
–1.0
—
+1.0
V
respect to SG
Output Amplitude
Offset Voltage
AOUT+, AOUT–, RL = 0.6 kW
VOAO
–1.0
–100
–100
—
—
—
+1.0
+100
+100
V
with respect to SG
VOSVF VFRO with respect to SG
mV
mV
AOUT+, AOUT–, Gain = 1 with
VOSAO
respect to SG
11/19
¡ Semiconductor
MSM7717-01/02/03
AC Characteristics
(FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
Unit
Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
LossR1
LossR2
LossR3
LossR4
LossR5
SD T1
SD T2
SD T3
60
300
20
26
+0.07
Reference
–0.01
+0.15
0.4
—
–0.15
+0.2
1020
2020
3000
3400
300
Transmit Frequency Response
Receive Frequency Response
0
0
dB
–0.15
–0.15
0
+0.2
+0.2
0.8
–0.15
–0.03
Reference
–0.02
+0.15
0.56
+0.2
1020
2020
3000
3400
–0.15
–0.15
0
+0.2
+0.25
0.8
dB
dB
3
0
35
43
—
35
41
—
–30
35
38
—
Transmit Signal to Distortion Ratio
1020
*1
28
SD T4
SD T5
–40
–45
30
25
—
—
23
SD R1
SD R2
SD R3
3
0
36
36
36
43
41
—
—
—
–30
40
Receive Signal to Distortion Ratio
1020
dB
*1
30
29
33.5
SD R4
SD R5
–40
–45
*2
*2
—
32
25
30
—
24
27
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
3
–0.3
+0.01
Reference
0
+0.3
–10
–40
–50
–55
3
Transmit Gain Tracking
Receive Gain Tracking
1020
1020
–0.3
–0.6
–1.2
–0.3
+0.3
+0.6
+1.2
+0.3
dB
dB
–0.03
+0.15
–0.06
Reference
–0.02
–0.02
–0.27
–10
–40
–50
–55
–0.3
–0.6
–1.2
+0.3
+0.6
+1.2
*1 Psophometric filter is used.
*2 Upper columns are specified for the m-law, lower for the A-law.
12/19
¡ Semiconductor
MSM7717-01/02/03
AC Characteristics (Continued)
(FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Freq.
(Hz)
Level
(dBm0)
Parameter
Symbol
Condition Min.
Typ.
Max.
Unit
AIN = SG
–72.5
–70.5
–76.5
Nidle T
—
—
—
—
— *2
–68
Idle Channel Noise
*1
*1 *3
VDD = 3.0 V
Ta = 25°C
*4
dBm0p
NidleR
AV T
—
–74
0.338
0.35
0.5
0.362
Absolute Level (Initial Difference)
Vrms
AV R
AV Tt
0.483
–0.2
0.518
+0.2
1020
1020
0
VDD = 2.7 V
—
—
dB
dB
Absolute Level
to 3.8 V
Ta = –30
to 85°C *4
A to A
BCLK
(Deviation of Temperature and Power)
AV Rt
Td
–0.2
—
+0.2
0.6
Absolute Delay
0
0
—
ms
ms
= 64 kHz
tGD T1
tGD T2
tGD T3
tGD T4
tGD T5
tGD R1
500
600
—
—
—
—
—
—
—
—
—
—
75
70
0.19
0.11
0.02
0.05
0.07
0.00
0.00
0.00
0.09
0.12
80
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
—
Transmit Group Delay
1000
2600
2800
500
*5
*5
tGD R2
600
Receive Group Delay
tGD R3
tGD R4
1000
2600
2800
0
0
ms
dB
tGD R5
CR T
CR R
TRANS Æ RECV
RECV Æ TRANS
Crosstalk Attenuation
1020
76
—
*1 Psophometric filter is used.
*2 Upper column is specified for the m-law, lower for the A-law.
*3 Input "0" code to PCMIN.
*4 AVR is defined at VFRO output.
*5 With respect to minimum value of the group delay distortion
13/19
¡ Semiconductor
MSM7717-01/02/03
AC Characteristics (Continued)
(FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Freq.
(Hz)
4.6 kHz to
72 kHz
300 to
3400
Level
(dBm0)
Parameter
Discrimination
Symbol
Condition Min.
Typ.
32
Max.
—
Unit
dB
0 to
DIS
S
0
0
30
4000 Hz
4.6 kHz to
—
Out-of-band Spurious
–37.5
–52
30
–35
–35
—
dBm0
dBm0
dB
100 kHz
fa = 470
fd = 320
0 to
Intermodulation Distortion
Power Supply Noise Rejection Ratio
IMD
–4
2fa – fd
*6
—
—
PSR T
50 mVPP
PSR R 50 kHz
t
20
20
20
20
—
—
—
—
200
200
200
200
SD
t
XD1
XD2
XD3
Digital Output Delay Time
CL = 100 pF + 1 LSTTL
ns
t
t
*6 Measured under idle channel noise.
14/19
¡ Semiconductor
MSM7717-01/02/03
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing
BCLK
XSYNC
1
2
3
4
5
6
7
8
9
10
tXS
tSX
tWSL
tWSH
tXD1
tSD tXD2
MSD D2
tXD3
D8
PCMOUT
D3
D4
D5
D6
D7
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1
.
When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD
.
Receive Timing
BCLK
1
2
3
4
5
6
7
8
9
10
tRS
tSR
tWSH
tWSL
RSYNC
PCMIN
tDS
MSD D2
tDH
D4
D3
D5
D6
D7
D8
Figure 1 Basic Timing
15/19
¡ Semiconductor
MSM7717-01/02/03
APPLICATION CIRCUIT
+3 V
MSM7717-01
51 kW
0.1 mF
Analog input
AIN–
PCMOUT
PCM signal output
XSYNC
8 kHz SYNC signal input
GSX
RSYNC
BCLK
AIN+
SG
PCM shift clock input
PCM data
PCMIN
AOUT+
Analog inverted output*
Analog output*
ALAW
Control of companding law
1: A-law
0: m-law
AOUT–
PWI
VFRO
SGC
AG
51 kW
0.1 mF
PDN
DG
Power down control input
1: Normal operation
0: Power down
10 mF
0 V
1 mF
+
+3 V
VDD
0 to 10 W
*
These output signals have amplitudes above and below the offset level of V /2.
DD
FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT
MSM7717-XX
Microphone amp
C1
Transmit frequency
characteristic
Adjustment determined by
C1, C2, R1 and R2
R1
M
AIN–
C2
R2
GSX
AIN+
SG
Receive frequency
characteristic
Adjustment determined by
C3, C4, R3 and R4
AOUT+
AOUT–
R5
R4
C4
PWI
VFRO
R3 C3
16/19
¡ Semiconductor
MSM7717-01/02/03
NOTES ON USE
• Toensureproperelectricalcharacteristics,usebypasscapacitorswithexcellenthighfrequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin as close as possible. Connect to the system ground with
low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the
use of IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
sources such as power supply transformers surround the device.
• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-
DD
up that may otherwise occur when power is turned on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
powersupplytoavoiderroneousoperationandthedegradationofthecharacteristicsofthese
devices.
17/19
¡ Semiconductor
PACKAGE DIMENSIONS
SOP24-P-430-1.27-K
MSM7717-01/02/03
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/19
¡ Semiconductor
MSM7717-01/02/03
(Unit : mm)
SSOP20-P-250-0.95-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.18 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
19/19
相关型号：
MSM7717-02GS-K
PCM Codec, MU-Law, 1-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24
OKI
MSM7717-03MS-K
PCM Codec, A-Law, 1-Func, CMOS, PDSO20, 0.250 INCH, 0.95 MM PITCH, PLASTIC, SSOP-20
OKI
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