MSM80C51F [OKI]
CMOS 8-Bit Microcontroller; 8位CMOS微控制器
| 型号： | MSM80C51F |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | CMOS 8-Bit Microcontroller |
| 文件： | 总39页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2E1037-19-41
This version: Mar. 1995
¡ Semiconductor
MSM80C31F/MSM80C51F
CMOS 8-Bit Microcontroller
GENERAL DESCRIPTION
The OKI MSM80C31F/MSM80C51F microcontroller is a low-power, 8-bit device implemented
in OKI's silicon-gate complementary metal-oxide semiconductor process technology. The
device includes 4K bytes of mask programmable ROM (MSM80C51F only), 128 bytes of
data RAM, 32 I/O lines, two 16-bit timer/counters, a five-source two-level interrupt
structure, a full duplex serial port, and an oscillator and clock circuitry. In addition, the device
has two software selectable modes for further power reduction — Idle and Power Down. Idle
modefreezestheCPU'sin-structionexecutionwhilemaintainingRAMandallowingthetimers,
serial port and interrupt system to continue functions. Power Down mode saves the RAM
contents but freezes the oscillator causing all other device functions to be inoperative.
FEATURES
• Low power consumption by 2 mm silicon gate CMOS process technology
• Fully static circuit
• Internal program memory
• External program memory space
• Internal data memory (RAM)
• External data memory (RAM) space
• I/O ports
:
:
:
:
:
4K bytes (MSM80C51F)
64K bytes
128 bytes
64K bytes
8-bit ¥ 4 ports
• Two 16-bit timer/counters
• Multifunctional serial port (UART)
• Five interrupt sources (Priority can be set)
• Four sets of working registers (R0-7 ¥ 4)
• Stack
:
Internal data memory (RAM)
128-byte area can be used arbitrarily (by SP specified)
• Two CPU power-down modes
(1) Idle mode
:
CPU stopped while oscillation continued.
(Software setting)
(2) PD mode
:
CPU and oscillation all stopped.
(Software setting)
(Setting I/O ports to floating status possible)
• Operating temperature
:
:
:
–40 to +85°C (@ 12 MHz, V = 5 V ±20%)
CC
–20 to +70°C (@ 16 MHz, V = 5 V ±5%)
CC
• 2-byte 1-machine cycle instructions
• Multiplication/division instructions
1 msec. @ 12 MHz
0.75 msec. @ 16 MHz
4 msec. @ 12 MHz
3 msec. @ 16 MHz
• Instruction code addressing method
Byte specification
:
:
Data addressing (direct)
Bit addressing
Bit specification
1/38
¡ Semiconductor
MSM80C31F/80C51F
• Package options
40-pin plastic DIP (DIP40-P-600-2.54)
44-pin plastic QFP (QFP44-P-910-0.80-2K)
44-pin plastic QFJ (PLCC) (QFJ44-P-S650-1.27)
:
:
:
(MSM80C31F-¥¥¥RS) (MSM80C51F-¥¥¥RS)
(MSM80C31F-¥¥¥GS) (MSM80C51F-¥¥¥GS)
(MSM80C31F-¥¥¥JS) (MSM80C51F-¥¥¥JS)
¥¥¥ indicates the code number.
DIFFERENCESBETWEENMSM80C31F/MSM80C51FANDMSM80C31/MSM80C51
• Operating frequency
0.5 to 16 MHz ..................... MSM80C31F-1/MSM80C51F-1
0.5 to 12 MHz ..................... MSM80C31/MSM80C51/MSM80C31F/MSM80C51F
• External clock input terminal
XTAL1 ................................. MSM80C31F(-1)/MSM80C51F(-1)
XTAL2 ................................. MSM80C31/MSM80C51
• Emulation mode
Output impedance of ALE and PSEN pins becomes about 20 kW while CPU is being reset in
MSM80C31F/MSM80C51F.
Any other functions and electrical characteristics of MSM80C31F/MSM80C51F except for
above three differences are the same as those of MSM80C31/MSM80C51.
2/38
CONTROL
SIGNALS
R/W
SIGNALS
P2.0 to P2.7
SPECIAL
FUNCTION
REGISTER
ADDRESS
DECODER
ROM
PLA
4096 WORDS
¥ 8 BITS
PCHL
PCLL
P0.0 to P0.7
XTAL1
PCH
PCL
IR
AIR
SENSE AMP
C-ROM
XTAL2
ALE
PSEN
R/W AMP
TR1
DPH
DPL
ACC
TR2
EA
RESET
128 WORDS
¥ 8 BITS
RAMDP
BR
SP
PSW
ALU
P1.0 to P1.7
P3.0 to P3.7
TH1
TL1
TH0
TIMER/COUNTER
TL0
TMOD
TCON
IE
INTERRUPT
IP
SBUF(T)
SBUF(R)
SCON
SERIAL IO
CYCLE
M1
M1
M2
M1
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
STEP
1
0
1
0
XTAL1
ALE
1
0
1
0
PSEN
RD/WR
DPL&Rr
1
0
PCL
PCL
PCL
ACC & RAM
PCL
PCL
PCL
PORT-0
1
0
PCH
PCH
PCH
PCH
DPH & PORT DATA
PCH
PCH
PCH
DATA STABLE
PORT-2
DATA STABLE
1
0
1
0
¨
CPU PORT
¨
PORT OLD DATA
PORT CPU
PORT NEW DATA
Instruction decoding
Instruction execution
PC+1
Instruction decoding
PC+1
Instruction decoding
Instruction execution
Instruction execution
PC+1
PC+1
PC+1
TM+1
TM+1
TM+1
TM+1
External data memory instruction
execution
Port output/input
Port output/input
Instruction execution
Instruction execution
¡ Semiconductor
MSM80C31F/80C51F
PIN CONFIGURATION (TOP VIEW)
P1.0
P1.1
1
2
3
4
5
6
7
8
9
40 VCC
39 P0.0
38 P0.1
37 P0.2
36 P0.3
P1.2
P1.3
P1.4
P1.5
35 P0.4
34 P0.5
33 P0.6
32 P0.7
31 EA
30 ALE
29 PSEN
28 P2.7
27 P2.6
26 P2.5
25 P2.4
24 P2.3
23 P2.2
22 P2.1
21 P2.0
P1.6
P1.7
RESET
RXD/P3.0 10
TXD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
VSS 20
40-Pin Plastic DIP
5/38
¡ Semiconductor
MSM80C31F/80C51F
PIN CONFIGURATION (TOP VIEW) (continued)
P1.5
P1.6
1
2
3
4
5
6
7
8
9
33 P0.4
32 P0.5
31 P0.6
30 P0.7
29 EA
P1.7
RESET
P3.0/RXD
NC
28 NC
P3.1/TXD
P3.2/INT0
P3.3/INT1
27 ALE
26 PSEN
25 P2.7
24 P2.6
23 P2.5
P3.4/T0 10
P3.5/T1/HPDI 11
44-Pin Plastic QFP
6/38
¡ Semiconductor
MSM80C31F/80C51F
PIN CONFIGURATION (TOP VIEW) (continued)
P0.3 40
P0.2 41
P0.1 42
P0.0 43
VCC 44
28 P2.4
27
26
25
24
23
22
21
20
19
18
P2.3
P2.2
P2.1
P2.0
NC
P1.0
P1.1
P1.2
P1.3
P1.4
1
2
3
4
5
6
NC
VSS
XTAL1
XTAL2
P3.7/RD
P3.6/WR
44-Pin Plastic QFJ (PLCC)
7/38
¡ Semiconductor
MSM80C31F/80C51F
PIN DESCRIPTION
Symbol
Description
VSS
VCC
Ground potential
Supply voltage during Normal, Idle and Power Down operation
Port 0.0
- 0.7
Port 0 is an 8-bit open-drain bidirectional I/O port. It is also the mutiplexed low-order address
and data bus during accesses to external memory.
Port 1.0
- 1.7
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. It can drive CMOS inputs without
external pull-ups.
Port 2.0
- 2.7
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. It outputs the high-order address
byte during accesses to external memory. It can drive CMOS inputs without external pull-ups.
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. It also provides various special
Port 3.0
- 3.7
features, as shown below:
Port Pin
P3.0
Alternate Function
(serial input port)
RXD
TXD
INT0
INT1
T0
(serial output port)
P3.1
(external interrupt)
P3.2
(external interrupt)
P3.3
(Timer 0 external input)
(Timer 1 external input)
(external data memory write strobe)
(external data memory read strobe)
P3.4
P3.5
T1
P3.6
WR
P3.7
RD
Port 3 can drive CMOS inputs without external pull-ups.
RESET
ALE
Reset input pin. A reset is accomplished by holding the RESET pin high for at least 1ms.
even if the oscillator has been stopped. The CPU responds by executing an internal reset. An
internal pull-down resistor permits Power-On reset using only a capacitor connected to VCC
This pin does not receive the power down voltage since the function has been transferred to the
VCC pin.
.
Address Latch Enable. This output latches for latching the low byte of the address during
accesses to external memory. For this purpose, ALE is activated twice every machine cycle or
at a constant rate of 1/6th the oscillator frequency, except during an external memory access at
which time one ALE pulse is skipped. ALE can drive CMOS inputs without an external pull-up.
PSEN
EA
Program Store Enable output. This output is the read strobe to external program memory.
For this purpose, PSEN is activated twice every machine cycle. (However, when executing out
of external program memory, two activations of PSEN are skipped during each access to
external data memory.) PSEN is not activated during fetches from internal program memory.
It can drive CMOS inputs without an external pull-up.
External Access input pin. When EA is held high, the CPU executes out of internal program
memory (unless the program counter exceeds 0FFFH).
When EA is held low, the CPU executes only out of external program memory.
EA must not be floated.
Crystal 1 pin. It is an input to the inverting amplifier which forms the internal oscillator.
Crystal 2 pin. It is an output of the inverting amplifier that forms the internal oscillator.
XTAL1
XTAL2
8/38
¡ Semiconductor
MSM80C31F/80C51F
DATA MEMORY AND SPECIAL FUNCTION REGISTER LAYOUT DIAGRAM
0F0H
0E0H
0D0H
0B8H
0B0H
0A8H
0A0H
99H
B
ACC
PSW
IP
P3
IE
P2
SBUF
SCON
P1
98H
90H
8DH
8CH
8BH
8AH
89H
88H
87H
83H
82H
TH1
TH0
TL1
TL0
TMOD
TCON
PCON
DPH
DPL
SP
81H
80H
P0
7F
USER RAM
80W ¥ 8 bits
30
2F 7F
78
BIT ADDRESSABLE
RAM
1F R7
20
7
0
BIT ADDRESSING
BANK 3
BANK 2
BANK 1
BANK 0
18 R0
17 R7
10 R0
0F R7
08 R0
07 R7
DATA ADDRESSING
00 R0
9/38
¡ Semiconductor
MSM80C31F/80C51F
DETAILED DIAGRAM OF DATA MEMORY (RAM)
7FH
127
48
USER DATA RAM
30H
2FH
2EH
2DH
2CH
2BH
2AH
29H
28H
27H
26H
25H
24H
23H
22H
21H
7F
77
6F
67
5F
57
4F
47
3F
37
2F
27
1F
17
0F
07
7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06
7D
75
6D
65
5D
55
4D
45
3D
35
2D
25
1D
15
0D
05
7C
74
6C
64
5C
54
4C
44
3C
34
2C
24
1C
14
0C
04
7B
73
6B
63
5B
53
4B
43
3B
33
2B
23
1B
13
0B
03
7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02
79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20H
1FH
32
31
Bank 3
18H
17H
24
23
Bank 2
Bank 1
Bank 0
10H
0FH
16
15
08H
07H
8
7
00H
0
10/38
¡ Semiconductor
MSM80C31F/80C51F
DETAILED DIAGRAM OF SPECIAL FUNCITON REGISTERS
Special
Function
Register
Symbol
(LSB)
Data
Address
(MSB)
F7
Bit Address
0F0H
0E0H
0D0H
0B8H
0B0H
0A8H
0A0H
99H
F6
F5
F4
F3
F2
F1
F0
B
E7
CY
D7
E6
AC
D6
E5
F0
D5
E4
E3
E2
OV
D2
PX1
BA
E1
F1
D1
PT0
B9
E0
P
ACC
RS1 RS0
D4
PS
BC
D3
PT1
BB
D0 PSW
PX0
—
—
B6
—
A6
—
B5
—
A5
B8
IP
B7
EA
AF
B4
ES
AC
B3
ET1
AB
B2
EX1
AA
B1
ET0
A9
B0
EX0
A8
P3
IE
A7
A4
A3
A2
A1
A0
P2
Not Bit Addressable
SBUF
SCON
P1
SM0 SM1 SM2 REN
9F
TB8
9B
RB8
9A
TI
99
RI
98
98H
9E
9D
9C
94
90H
97
96
95
93
92
91
90
8DH
8CH
8BH
8AH
89H
TH1
TH0
TL1
Not Bit Addressable
Not Bit Addressable
Not Bit Addressable
Not Bit Addressable
Not Bit Addressable
TL0
TMOD
TF1
8F
TR1
8E
TF0
8D
TR0
8C
IE1
8B
IT1
8A
IE0
89
IT0
88
88H
87H
TCON
PCON
Not Bit Addressable
83H
82H
81H
80H
Not Bit Addressable
Not Bit Addressable
Not Bit Addressable
DPH
DPL
SP
87
86
85
84
83
82
81
80
P0
11/38
¡ Semiconductor
MSM80C31F/80C51F
INSTRUCTION LIST
List of Instruction Symbols
A
AB
: Accumulator
: Register pair
AC
B
C
: Auxiliary carry flag
: Arithmetic operation register
: Carry flag
DPTR
: Data pointer
PC
Rr
SP
: Program counter
: Register indicator (r = 0 to 7)
: Stack pointer
AND
OR
: Logical product
: Logical sum
XOR
: Exclusive-OR
+
–
: Addition
: Subtraction
X
/
: Multiplication
: Division
(X)
: Denotes the contents of X
((X))
: Denotes the contents of address determined by the contents of X
#
@
=
: Denotes the immediate data
: Denotes the indirect address
: Equality
Þ
: Non-equality
¨
: Substitution
: Substitution
: Negation
Æ
—
<
: Smaller than
>
: Larger than
bit address
: RAM and the special function register bit specifier address (b to b )
0 7
code address : Absolute address (A to A )
0
15
data
: Immediate data (I to I )
0 7
relative offset : Relative jump address offset value (R to R )
0
7
direct address : RAM and the special function register byte specifier address (a to a )
0
7
12/38
¡ Semiconductor
MSM80C31F/80C51F
MSM80C31F/MSM80C51F Instruction Codes
L
0
0000
1
2
3
0011
4
0100
5
0101
6
0110
7
0111
0001
0010
H
AJMP
address 11
(Page 0)
ACALL
0
LJMP
INC
NOP
RR A
RRC A
RL A
INC A
DEC A
INC @R0 INC @R1
DEC @R0 DEC @R1
0000
address 16
direct
1
0001
JBC bit,
rel
LCALL
adress 16
DEC
direct
address 11
(Page 0)
AJMP
2
0010
JB bit,
rel
ADD A,
#data
ADD A,
direct
ADD A,
@R0
ADD A,
@R1
address 11
(Page 1)
ACALL
RET
3
0011
JNB bit,
rel
ADDC A,
#data
ADDC A,
direct
ADDC A,
@R0
ADDC A,
@R1
address 11
(Page 1)
AJMP
RETI
RLC A
ORL
direct,
#data
ANL
direct,
#data
XRL
direct,
#data
4
0100
JC
rel
ORL
direct, A
ORL A,
#data
ORL A,
direct
ORL A,
@R0
ORL A,
@R1
address 11
(Page 2)
ACALL
5
0101
ANL
direct, A
ANL A,
#data
ANL A,
direct
ANL A,
@R0
ANL A,
@R1
JNC rel
JZ rel
address 11
(Page 2)
AJMP
6
0110
XRL
direct, A
XRL A,
#data
XRL A,
direct
XRL A,
@R0
XRL A,
@R1
address 11
(Page 3)
ACALL
MOV
direct
#data
MOV
direct1,
direct2
7
0111
ORL C,
bit
JMP
@A+DPTR
MOV A,
#data
MOV @R0, MOV @R1,
JNZ rel
address 11
(Page 3)
AJMP
#data
#data
MOV
direct,
@R0
MOV
direct,
@R1
8
1000
ANL C,
bit
MOVC A,
@A+PC
SJMP rel address 11
DIV AB
(Page 4)
ACALL
MOV DPTR,
address 11
9
1001
MOV bit,
C
MOVC A,
@A+DPTR
SUBB A,
#data
SUBB A,
direct
SUBB A,
@R0
SUBB A,
direct
#data 16
(Page 4)
AJMP
ORL C, /bit address 11
(Page 5)
A
MOV C,
bit
MOV @R0, MOV @R1,
INC DPTR MUL AB
CJNE A,
1010
direct
direct
ACALL
CJNE A, CJNE @R0
B
1011
CJNE @R1,
#data, rel
ANL C, /bit address 11
(Page 5)
CPL bit
CLR bit
SETB bit
CPL C
CLR C
SETB C
#data
rel
direct,
rel
#data,
rel
AJMP
C
1100
PUSH
XCH A,
direct
XCH A,
@R0
XCH A,
@R1
address 11
direct
SWAP A
(Page 6)
ACALL
DJNZ
direct,
rel
D
1101
POP
XCHD A,
@R0
XCHD A,
@R1
address 11
direct
DA A
(Page 6)
AJMP
E
1110
MOVX A,
MOVX A, MOVX A,
@R0
MOV A,
direct
MOV A,
@R0
MOV A,
@R1
address 11
@DPTR
CLR A
CPL A
@R1
(Page 7)
ACALL
F
MOVX
MOVX
@R0, A
MOVX
@R1, A
MOV
direct, A
MOV
@R0, A
MOV
@R1, A
address 11
@DPTR, A
1111
(Page 7)
2BYTES
3BYTES
4CYCLES
MNEMONIC
2CYCLES
13/38
¡ Semiconductor
MSM80C31F/80C51F
MSM80C31F/MSM80C51F Instruction Codes (continued)
L
8
1000
9
A
1010
B
1011
C
1100
D
1101
E
F
1001
1110
1111
H
0
INC R0
DEC R0
INC R1
DEC R1
INC R2
DEC R2
INC R3
DEC R3
INC R4
DEC R4
INC R5
DEC R5
INC R6
DEC R6
INC R7
DEC R7
0000
1
0001
2
ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7
ADDC A, R0 ADDC A, R1 ADDC A, R2 ADDC A, R3 ADDC A, R4 ADDC A, R5 ADDC A, R6 ADDC A, R7
ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4 ORL A, R5 ORL A, R6 ORL A, R7
ANL A, R0 ANL A, R1 ANL A, R2 ANL A, R3 ANL A, R4 ANL A, R5 ANL A, R6 ANL A, R7
XRL A, R0 XRL A, R1 XRL A, R2 XRL A, R3 XRL A, R4 XRL A, R5 XRL A, R6 XRL A, R7
0010
3
0011
4
0100
5
0101
6
0110
7
0111
MOV R0,
#data
MOV R1,
#data
MOV R2,
#data
MOV R3,
#data
MOV R4,
#data
MOV R5,
#data
MOV R6,
#data
MOV R7,
#data
MOV
direct,
R0
MOV
direct,
R1
MOV
direct,
R2
MOV
direct,
R3
MOV
direct,
R4
MOV
direct,
R5
MOV
direct,
R6
MOV
direct,
R7
8
1000
9
1001
SUBB A,
R0
SUBB A,
R1
SUBB A,
R2
SUBB A,
R3
SUBB A,
R4
SUBB A,
R5
SUBB A,
R6
SUBB A,
R7
A
1010
MOV R0,
direct
MOV R1,
direct
MOV R2,
direct
MOV R3,
direct
MOV R4,
direct
MOV R5,
direct
MOV R6,
direct
MOV R7,
direct
CJNE R0, CJNE R1, CJNE R2, CJNE R3, CJNE R4, CJNE R5, CJNE R6, CJNE R7,
B
1011
#data
rel
#data
rel
#data
rel
#data
rel
#data
rel
#data
rel
#data
rel
#data
rel
C
1100
XCH A,
R0
XCH A,
R1
XCH A,
R2
XCH A,
R3
XCH A,
R4
XCH A,
R5
XCH A,
R6
XCH A,
R7
D
1101
DJNZ R0, DJNZ R1, DJNZ R2, DJNZ R3, DJNZ R4, DJNE R5, DJNE R6, DJNE R7,
rel rel rel rel rel rel rel rel
E
MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7
MOV R0, A MOV R1, A MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6, A MOV R7, A
1110
F
1111
14/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details
Instruction code
Type
Mnemonic
Bytes Cycles
Description
D7 D6 D5 D4 D3 D2 D1 D0
ADD A, Rr
1
2
1
1
(AC), (0V), (C), (A) ¨ (A)+(Rr)
0
0
0
0
1
1
0
0
1
0
r2 r1 r0
ADD A, direct
(AC), (0V), (C), (A) ¨ (A)+(direct
address)
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
ADD A, @Rr
ADD A, #data
1
2
1
1
(AC), (0V), (C), (A) ¨ (A)+((Rr))
(AC), (0V), (C), (A) ¨ (A)+#data
0
0
0
0
1
1
0
0
0
0
1
1
1
0
r0
0
I7 I6 I5 I4 I3 I2 I1 I0
ADDC A, Rr
1
2
1
1
(AC), (0V), (C), (A) ¨ (A)+(C)+(Rr)
0
0
0
0
1
1
1
1
1
0
r2 r1 r0
ADDC A, direct
(AC), (0V), (C), (A) ¨ (A)+(C)+
(direct address)
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
ADDC A, @Rr
ADDC A, #data
1
2
1
1
(AC), (0V), (C), (A) ¨ (A)+(C)+((Rr))
(AC), (0V), (C), (A) ¨ (A)+(C)+#data
0
0
0
0
1
1
1
1
0
0
1
1
1
0
r0
0
I7 I6 I5 I4 I3 I2 I1 I0
SUBB A, Rr
1
2
1
1
(AC), (0V), (C), (A) ¨ (A)–((C))+((Rr))
1
1
0
0
0
0
1
1
1
0
r2 r1 r0
SUBB A, direct
(AC), (0V), (C), (A) ¨ (A)–((C)+
(direct address))
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
SUBB A, @Rr
SUBB A, #data
1
2
1
1
(AC), (0V), (C), (A) ¨ (A)–((C)+((Rr))
1
1
0
0
0
0
1
1
0
0
1
1
1
0
r0
0
(AC), (0V), (C), (A) ¨ (A)–((C)+
#data)
I7 I6 I5 I4 I3 I2 I1 I0
MUL AB
DIV AB
1
1
4
4
(AB) ¨ (A) x (B)
1
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
(A)quotient,
¨ (A)/(B)
(B) remainder
DA A
1
1
When the contents of accumulator bits
0 thru 3 are greater than 9, or when
auxiliary carry (AC) is 1, 6 is added to
bits 0 thru 3. Bits 4 thru 7 are then
examined, and when bits 4thru 7
follwoing compensation of lower bits 0
thru 3 is greater than 9, or when carry
(C) is 1, 6 is added to bits 4 thru 7. As
a result, the cary flag can be set, but
cannot be cleared.
1
1
0
1
0
1
0
0
1
1
0
1
1
0
1
1
1
0
1
0
0
0
0
1
1
0
0
0
1
0
0
1
(A) ¨ 0
(A) ¨ (A)
Accumulator
CLR A
CPL A
PL A
1
1
1
1
1
1
C
¨¨¨¨¨¨¨¨
7
0
0
0
1
1
0
0
1
1
Accumulator
¨¨¨¨¨¨¨¨
PL C
1
1
C
7
0
15/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Instruction code
Type
Mnemonic
Bytes Cycles
Description
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
1
Accumulator
RR A
1
1
C
ÆÆÆÆÆÆÆÆ
7
0
0
0
0
1
0
0
1
1
Accumulator
ÆÆÆÆÆÆÆÆ
RRC A
1
1
C
7
0
SWAP A
INC A
1
1
1
2
1
1
1
1
(A4 -7) ´ (A0 -3)
(A) ¨ (A)+1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
INC Rr
(Rr) ¨ (Rr)+1
r2 r1 r0
INC direct
(direct address) ¨ (direct address)+1
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
INC @Rr
INC DPTR
DEC A
1
1
1
1
2
1
2
1
1
1
((Rr)) ¨ ((Rr))+1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
1
0
1
0
1
1
1
0
r0
1
(DPTR) ¨ (DPTR)+1
(A) ¨ (A)–1
0
DEC Rr
(Rr) ¨ (Rr)–1
r2 r1 r0
DEC direct
(direct address) ¨ (direct address)–1
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
DEC @Rr
1
1
2
1
1
1
((Rr)) ¨ ((Rr))–1
0
0
0
0
1
1
0
0
0
1
1
1
0
1
0
1
1
r0
ANL A, Rr
ANL A, direct
(A) ¨ (A) AND (Rr)
r2 r1 r0
(A) ¨ (A) AND (direct address)
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
ANL A, @Rr
ANL A, #data
1
2
1
1
(A) ¨ (A) AND ((Rr))
(A) ¨ (A) AND #data
0
0
1
1
0
0
1
1
0
0
1
1
1
0
r0
0
I7 I6 I5 I4 I3 I2 I1 I0
ANL direct, A
2
3
1
2
(direct address) ¨ (direct address)
0
1
0
1
0
0
1
0
AND (A)
a7 a6 a5 a4 a3 a2 a1 a0
ANL direct,
#data
(direct address) ¨ (direct address)
AND #data
0
1
0
1
0
0
1
1
a7 a6 a5 a4 a3 a2 a1 a0
I7 I6 I5 I4 I3 I2 I1 I0
ORL A, Rr
1
2
1
1
(A) ¨ (A) OR (Rr)
0
0
1
1
0
0
0
0
1
0
r2 r1 r0
ORL A, direct
(A) ¨ (A) OR (direct address)
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
ORL A, @Rr
ORL A, #data
1
2
1
1
(A) ¨ (A) OR ((Rr))
(A) ¨ (A) OR #data
0
0
1
1
0
0
0
0
0
0
1
1
1
0
r0
0
I7 I6 I5 I4 I3 I2 I1 I0
ORL direct, A
2
1
(direct address) ¨ (direct address)
OR (A)
0
1
0
0
0
0
1
0
a7 a6 a5 a4 a3 a2 a1 a0
16/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Instruction code
Type
Mnemonic
Bytes Cycles
Description
D7 D6 D5 D4 D3 D2 D1 D0
ORL direct,
#data
3
2
(direct address) ¨ (direct address)
OR #data
0
1
0
0
0
0
1
1
a7 a6 a5 a4 a3 a2 a1 a0
I7 I6 I5 I4 I3 I2 I1 I0
XRL A, Rr
1
2
1
1
(A) ¨ (A) XOR (Rr)
0
0
1
1
1
1
0
0
1
0
r2 r1 r0
XRL A, direct
(A) ¨ (A) XOR (direct address)
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
XRL A, @Rr
XRL A, #data
1
2
1
1
(A) ¨ (A) XOR ((Rr))
(A) ¨ (A) XOR #data
0
0
1
1
1
1
0
0
0
0
1
1
1
0
r0
0
I7 I6 I5 I4 I3 I2 I1 I0
XRL direct, A
2
3
1
2
(direct address) ¨ (direct address)
0
1
1
0
0
0
1
0
XOR (A)
a7 a6 a5 a4 a3 a2 a1 a0
XRL direct,
#data
(direct address) ¨ (direct address)
XOR #data
0
1
1
0
0
0
1
1
a7 a6 a5 a4 a3 a2 a1 a0
I7 I6 I5 I4 I3 I2 I1 I0
MOV A, #data
MOV Rr, #data
2
2
3
1
1
2
(A) ¨ #data
0
1
1
1
0
1
0
0
I7 I6 I5 I4 I3 I2 I1 I0
r2 r1 r0
I7 I6 I5 I4 I3 I2 I1 I0
(Rr) ¨ #data
0
1
1
1
1
MOV direct,
#data
(direct address) ¨ #data
0
1
1
1
0
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
I7 I6 I5 I4 I3 I2 I1 I0
r0
I7 I6 I5 I4 I3 I2 I1 I0
MOV @Rr,
#data
2
3
1
2
(Rr)) ¨ #data
0
1
1
1
0
1
1
MOV DPTR,
#data 16
(DPTR) ¨ #data 16
1
0
0
1
0
0
0
0
I15 I14 I13 I12 I11 I10 I9 I8
I7 I6 I5 I4 I3 I2 I1 I0
CLR C
1
1
1
2
1
1
1
2
(C) ¨ 0
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
SETB C
CPL C
(C) ¨ 1
(C) ¨ (C)
ANL C, bit
(C) ¨ (C) AND (bit address)
b7 b6 b5 b4 b3 b2 b1 b0
ANL C,/bit
ORL C, bit
ORL C,/bit
2
2
2
2
2
2
(C) ¨ (C) AND (bit address)
(C) ¨ (C) OR (bit address)
(C) ¨ (C) OR (bit address)
1
0
1
1
0
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
0
1
1
1
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
1
0
1
0
0
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
17/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Instruction code
Type
Mnemonic
Bytes Cycles
Description
D7 D6 D5 D4 D3 D2 D1 D0
MOV C, bit
2
2
2
2
2
1
2
1
1
1
(C) ¨ (bit address)
1
0
1
0
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
MOV bit, C
SETB bit
CLR bit
(bit address) ¨ (C)
(bit address) ¨ 1
1
0
0
1
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
1
1
0
1
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
(bit address) ¨ 0
1
1
0
0
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
CPL bit
(bit address) ¨ (bit address)
1
0
1
1
0
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
MOV A, Rr
1
2
1
1
(A) ¨ (Rr)
1
1
1
1
1
1
0
0
1
0
r2 r1 r0
MOV A, direct
(A) ¨ (direct address)
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
MOV A, @Rr
MOV Rr, A
1
1
2
1
1
2
(A) ¨ ((Rr))
1
1
1
1
1
0
1
1
1
0
1
0
0
1
1
1
1
r0
(Rr) ¨ (A)
r2 r1 r0
r2 r1 r0
MOV Rr,
direct
(Rr) ¨ (direct address)
a7 a6 a5 a4 a3 a2 a1 a0
MOV direct, A
2
2
3
1
2
2
(direct address) ¨ (A)
1
1
1
1
0
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
r2 r1 r0
a7 a6 a5 a4 a3 a2 a1 a0
r0
a27 a26 a25 a24 a23 a22 a21 a20
a17 a16 a15 a14 a13 a12 a11 a10
MOV direct,
Rr
(direct address) ¨ (Rr)
1
0
0
0
1
MOV direct 1,
direct 2
(direct address 1) ¨ (direct address 2)
1
0
0
0
0
1
1
MOV @Rr, A
1
2
1
2
((Rr)) ¨ (A)
1
1
1
0
1
1
1
0
0
0
1
1
1
1
r0
r0
MOV @Rr,
direct
((Rr)) ¨ (direct address)
a7 a6 a5 a4 a3 a2 a1 a0
MOVC A,
@A+DPTR
1
1
2
2
(A) ¨ ((A)+(DPTR))
1
1
0
0
0
0
1
0
0
0
0
0
1
1
1
1
MOVC A,
@A+PC
(PC) ¨ (PC+1)
(A) ¨ ((A)+(PC))
XCH A, Rr
1
2
1
2
(A) ´ (Rr)
1
1
1
1
0
0
0
0
1
0
r2 r1 r0
XCH A, direct
(A) ´ (direct address)
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
XCH A, @Rr
1
1
1
1
(A) ´ ((Rr))
1
1
1
1
0
0
0
1
0
0
1
1
1
1
r0
r0
XCHD A, @Rr
(A0 - 3) ´ ((Rr0 - 3))
18/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Instruction code
Type
Mnemonic
Bytes Cycles
Description
D7 D6 D5 D4 D3 D2 D1 D0
PUSH direct
2
2
2
2
2
2
(SP) ¨ (SP)+1
1
1
0
0
0
0
0
0
((SP)) ¨ (direct address)
a7 a6 a5 a4 a3 a2 a1 a0
POP direct
(direct address) ¨ ((SP))
(SP) ¨ (SP)–1
1
1
0
1
0
0
0
0
a7 a6 a5 a4 a3 a2 a1 a0
A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
ACALL addr
11
(PC) ¨ (PC)+2
(SP) ¨ (SP)+1
((SP)) ¨ (PC0 - 7)
(SP) ¨ (SP)+1
((SP)) ¨ (PC8 - 15
(PC0 - 10) ¨ A0 - 10
1
0
0
0
1
)
LCALL addr
16
3
2
(PC) ¨ (PC)+3
(SP) ¨ (SP)+1
((SP)) ¨ (PC0 - 7)
(SP) ¨ (SP)+1
0
0
0
1
0
0
1
0
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
((SP)) ¨ (PC8 - 15
)
(PC0 - 10) ¨ A0 - 10
RET
1
1
2
2
(PC8 - 15) ¨ ((SP))
(SP) ¨ (SP)–1
(PC0 - 7) ¨ ((SP))
(SP) ¨ (SP)–1
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
0
0
1
RETI
(PC8 - 15) ¨ ((SP))
(SP) ¨ (SP)–1
(PC0 - 7) ¨ ((SP))
(SP) ¨ (SP)–1
AJMP addr 11
LJMP addr 16
2
3
2
2
(PC) ¨ (PC)+2
(PC0 - 10) ¨ A0 - 10
A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
(PC0 - 15) ¨ A0 - 15
0
0
0
0
0
0
1
0
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
SJMP rel
2
1
2
2
(PC) ¨ (PC)+3
(SP) ¨ (SP)+1
1
0
0
0
0
0
0
0
R7 R6 R5 R4 R3 R2 R1 R0
JMP @A+
DPTR
(PC) ¨ (A)+(DPTR)
0
1
1
1
0
0
1
1
19/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Instruction code
Type
Mnemonic
Bytes Cycles
Description
D7 D6 D5 D4 D3 D2 D1 D0
CJNE A, direct,
rel
3
3
3
3
2
2
2
2
(PC) ¨ (PC)+3
1
0
1
1
0
1
0
1
IF
(A)π(direct address)
a7 a6 a5 a4 a3 a2 a1 a0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
IF
(A)<(direct address)
THEN
(C) ¨ 1
(C) ¨ 0
ELSE
CJNE A, #data,
rel
(PC) ¨ (PC)+3
1
0
1
1
0
1
0
0
IF
(A)π #data
I7 I6 I5 I4 I3 I2 I1 I0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
IF
(A)< #data
THEN
(C) ¨ 1
(C) ¨ 0
ELSE
CJNE Rr,
#data, rel
(PC) ¨ (PC)+3
1
0
1
1
1
r2 r1 r0
IF
((Rr))π #data
I7 I6 I5 I4 I3 I2 I1 I0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
IF
(Rr))< #data
THEN
(C) ¨ 1
(C) ¨ 0
ELSE
CJNE @Rr,
#data, rel
(PC) ¨ (PC)+3
1
0
1
1
0
1
1
r0
IF
((Rr))π #data
I7 I6 I5 I4 I3 I2 I1 I0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
IF
((Rr))< #data
THEN
(C) ¨ 1
(C) ¨ 0
ELSE
DJNZ Rr, rel
2
3
2
2
(PC) ¨ (PC)+2
(Rr) ¨ (Rr)–1
1
1
0
1
1
r2 r1 r0
R7 R6 R5 R4 R3 R2 R1 R0
IF
(Rr)< 0
THEN
(PC) ¨ (PC)+relative offset
DJNZ direct,
rel
(PC) ¨ (PC)+3
1
1
0
1
0
1
0
1
(direct address) ¨ (direct address)–1
a7 a6 a5 a4 a3 a2 a1 a0
R7 R6 R5 R4 R3 R2 R1 R0
IF
THEN
(direct address)π 0
(PC) ¨ (PC)+relative offset
20/38
¡ Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Instruction code
Type
Mnemonic
Bytes Cycles
Description
D7 D6 D5 D4 D3 D2 D1 D0
JZ rel
2
2
2
2
3
3
3
2
2
2
2
2
2
2
(PC) ¨ (PC)+2
0
1
1
0
0
0
0
0
IF
(A) = 0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
JNZ rel
(PC) ¨ (PC)+2
0
1
1
1
0
0
0
0
IF
(A) π 0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
JC rel
(PC) ¨ (PC)+2
0
1
0
0
0
0
0
0
IF
(C) = 1
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
JNC rel
(PC) ¨ (PC)+2
0
1
0
1
0
0
0
0
IF
(C) = 0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
JB bit, rel
JNB bit, rel
JBC bit, rel
(PC) ¨ (PC)+3
0
0
1
0
0
0
0
0
IF
(bit address) = 1
b7 b6 b5 b4 b3 b2 b1 b0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
(PC) ¨ (PC)+3
0
0
1
1
0
0
0
0
IF
(bit address) = 0
b7 b6 b5 b4 b3 b2 b1 b0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(PC) ¨ (PC)+relative offset
(PC) ¨ (PC)+3
0
0
0
1
0
0
0
0
IF
(bit address) = 1
b7 b6 b5 b4 b3 b2 b1 b0
R7 R6 R5 R4 R3 R2 R1 R0
THEN
(bit address) ¨ 0
(PC) ¨ (PC)+relative offset
MOVX A, @Rr
1
1
2
2
(A) ¨ ((Rr)) EXTERNAL RAM
1
1
1
1
1
1
0
0
0
0
0
0
0
0
r0
0
MOVX A,
@DPTR
(A) ¨ ((DPTR)) EXTERNAL RAM
MOVX @Rr, A
1
1
2
2
(Rr) ¨ (A) EXTERNAL RAM
1
1
1
1
1
1
1
1
0
0
0
0
1
0
r0
0
MOVX
@DPTR, A
((DPTP)) ¨ (A) EXTERNAL RAM
NOP
1
1
(PC) ¨ (PC)+1
0
0
0
0
0
0
0
0
21/38
¡ Semiconductor
MSM80C31F/80C51F
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
VCC
Condition
Ta = 25°C
Ta = 25°C
—
Rating
–0.5 to +7.0
–0.5 to VCC +7.0
–55 to +150
Unit
V
Voltage from Any Pin to VSS
Storage Temperature
VI
V
TSTG
°C
OPERATING RANGE
Parameter
Supply Voltage
Symbol
VCC
Condition
See figure below
fOSC = Oscillation stop
See figure below
MSM80C31F/51F
MSM80C31F-1
Range
2.5 to 6
Unit
V
*1
*2
Memory Retention Voltage
Oscillation Frequency
VCC
2 to 6
V
fOSC
DC to 16
–40 to +85
–20 to +70
MHz
Ambient Temperature
Ta
°C
*1 DC & AC characteristics in the range of 2.5 V £ V < 4 V will be specified by DC & AC
CC
Characteristics 2.
*2 Specify MSM80C31F-1 when using MSM80C31F at 12 MHz to 16 MHz.
GUARANTEED OPERATING RANGE
Ta = –40 to +85°C (MSM80C31F/80C51F)
Ta = –20 to +70°C (MSM80C31F-1)
[ms]
10
1.2
5
4
3
6
Operating Range
3
2
MSM80C31/51
MSM80C31F/51F
1
12
16
0.75
MSM80C31F-1
5
2
3
4
6
[V]
Supply Voltage (VCC
)
22/38
¡ Semiconductor
MSM80C31F/80C51F
ELECTRICAL CHARACTERISTICS
DC Characteristics 1
MSM80C31F/51F
VCC = 5 V 20ꢀ, VSS = 0 V, Ta = –40°C to +85°C
MSM80C31F-1/51F-1 VCC = 5 V 5ꢀ, VSS = 0 V, Ta = –20°C to +70°C
Meas-
uring
Parameter
Low Input Voltage
Symbol
VIL
Condition
Min.
–0.5
Typ.
—
Max.
Unit
circuit
—
V
V
V
V
0.2 VCC – 0.1
Except XTAL1, RESET
and EA
High Input Voltage
VIH
0.2 VCC + 0.9
0.7 VCC
—
—
V
CC + 0.5
CC + 0.5
0.45
High Input Voltage
Low Output Voltage
(Port 1, 2 and 3)
VIH1
XTAL1, RESET and EA
—
V
VOL
IOL = 1.6 mA
—
Low Output Voltage
(Port 0, ALE and PSEN)
VOL1
IOL = 3.2 mA
—
—
—
V
V
0.45
—
1
IOH = –60 mA
2.4
High Output Voltage
(Port 1, 2 and 3)
V
CC = 5 V 10ꢀ
OH = –30 mA
IOH = –10 mA
IOH = –400 mA
CC = 5 V 10ꢀ
OH = –150 mA
OH = –40 mA
VI = 0.45 V
VO = 0.45 V
VOH
I
0.75 VCC
0.9 VCC
—
—
V
V
—
—
2.4
—
V
—
High Output Voltage
V
VOH1
(Port 0, ALE and PSEN)
I
0.75 VCC
0.9 VCC
—
—
V
V
—
—
I
Output Current at Low Input/
High Output Power Supply
I
IL / IOH
ITL
–10
—
—
—
mA
mA
–200
–500
2
Output Current (Port 1, 2
and 3) at transition from
H to L
VIL = 2.0 V
Input Leakage Current
(Floating Port 0 and EA)
RESET Pull-down Resistor
ILI
RRST
CIO
VSS < VI < VCC
—
20
—
—
—
40
—
1
mA
kW
pF
3
2
10
125
10
—
Ta = 25°C, f = 1 MHz
5 V (except XTAL1)
VCC = 2 V
Input Pin Capacitor
Power Down Current
—
4
IPD
mA
50
23/38
¡ Semiconductor
MSM80C31F/80C51F
DC Characteristics 2
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –40 to +85°C)
Meas-
uring
Parameter
Low Input Voltage
High Input Voltage
Symbol
VIL
Condition
Min.
–0.5
Typ.
—
Max.
0.25VCC – 0.1
VCC + 0.5
VCC + 0.5
0.1
Unit
circuit
—
V
V
V
V
Except XTAL1, RESET
and EA
VIH
0.25VCC + 0.9
—
High Input Voltage
VIH1
XTAL1, RESET and EA 0.6VCC + 0.6
—
Low Output Voltage
(Port 1, 2 and 3)
VOL
IOL = 10 mA
IOL = 20 mA
—
—
—
1
Low Output Voltage
(Port 0, ALE and PSEN)
High Output Voltage
(Port 1, 2 and 3)
VOL1
VOH
—
—
—
—
—
V
V
0.1
—
IOH = –5 mA
0.75 VCC
0.75 VCC
—
High Output Voltage
(Port 0, ALE and PSEN)
Output Current at Low Input/
High Output Power Supply
VOH1
IIL / IOH
ITL
IOH = –20 mA
V
—
VI = 0.1 V
VO = 0.1 V
mA
mA
–100
–300
2
Output Current (Port 1, 2
and 3) at transition from
H to L
VIL = 1.9 V
—
Input Leakage Current
(Floating Port 0 and EA)
RESET Pull-down Resistor
ILI
RRST
CIO
VSS < VI < VCC
—
20
—
—
—
40
—
1
mA
kW
pF
3
2
10
125
10
—
Ta = 25°C, f = 1 MHz
5 V (except XTAL1)
—
Input Pin Capacitor
Power Down Current
—
4
IPD
mA
10
24/38
¡ Semiconductor
MSM80C31F/80C51F
Maximum operating power supply I [mA]
CC
VCC
Freq
2.5 V
3.0 V
4.0 V
0.5 MHz
3.0 MHz
8 MHz
12 MHz
0.7
1.9
—
0.9
2.4
—
1.6
4.3
8.3
—
—
12.0
Maximum IDLE power supply I [mA]
CC
VCC
Freq
2.5 V
3.0 V
4.0 V
0.5 MHz
3.0 MHz
8 MHz
12 MHz
0.3
0.6
—
0.4
0.8
—
0.6
1.2
2.2
3.1
—
—
25/38
¡ Semiconductor
MSM80C31F/80C51F
Measuring Circuit
1
2
VCC
VSS
3
(*2)
V
(*1)
VCC
VSS
4
VIH
(*3)
IO
A
V A
VIL
A
VCC
(*2)
V
VCC
VIH
VIH
VIL
(*3)
(*3)
A
VIL
VSS
VSS
*1 Repeated for specified input pin.
*2 Repeated for specified output pin.
*3 Logic input for specified condition.
26/38
¡ Semiconductor
MSM80C31F/80C51F
External Program Memory Access AC Characteristics 1
(V = 5 V ±20%, V = 0 V, Ta = –40°C to +85°C; Load Capacitance for Port 0, ALE, and PSEN =
CC
SS
100 pF ; Load Capacitance for all other outputs = 80 pF)
Variable Clock
12 MHz Clock
See Guaranteed
Operating Range
Parameter
Symbol
Unit
Min.
—
Max.
—
Min.
Max.
XTAL1, XTAL2 Oscillation Cycle
ALE Signal Width
tCLCL
tLHLL
tAVLL
83.3
—
—
—
ns
ns
ns
126
43
—
2tCLCL – 40
1tCLCL – 40
Adderss Setup Time
—
(to ALE Falling Edge)
Adderss Hold Time
tLLAX
tLLIV
tLLPL
48
—
58
—
233
—
1tCLCL – 35
—
—
4tCLCL – 100
—
ns
ns
ns
(from ALE Falling Edge)
Instruction Data Read Time
(from ALE Falling Edge)
From ALE Falling Edge to
PSEN Falling Edge
1tCLCL – 25
PSEN Signal Width
tPLPH
tPLIV
215
—
—
3tCLCL – 35
—
—
ns
ns
Instruction Data Read Time
(from PSEN Falling Edge)
Instruction Data Hold Time
(from PSEN Rising Edge)
Bus Floating Time after Instruction
Data Read (from PSEN Rising Edge)
Address Output Time from
PSEN Rising Edge
145
3tCLCL – 105
tPXIX
tPXIZ
tPXAV
tAVIV
tPLAZ
0
—
63
—
312
0
0
—
—
1tCLCL – 20
—
ns
ns
ns
ns
ns
—
75
—
—
1tCLCL – 8
—
Instruction Data Read Time
(from Address Output)
Bus Floating Time (Address
Float from PSEN Falling Edge)
5tCLCL – 105
0
—
27/38
¡ Semiconductor
MSM80C31F/80C51F
External Program Memory Access AC Characteristics 2
(V = 2.5 to 4.0 V, V = 0 V, Ta = –40°C to +85°C; Load Capacitance for Port 0, ALE, and PSEN
CC
SS
= 100 pF ; Load Capacitance for all other outputs = 80 pF)
Variable Clock
12 MHz Clock
See Guaranteed
Operating Range
Parameter
Symbol
Unit
Min.
—
Max.
—
Min.
Max.
XTAL1, XTAL2 Oscillation Cycle
ALE Signal Width
tCLCL
tLHLL
tAVLL
83.3
—
—
—
ns
ns
ns
126
43
—
2tCLCL – 40
1tCLCL – 40
Adderss Setup Time
—
(to ALE Falling Edge)
Adderss Hold Time
tLLAX
tLLIV
tLLPL
48
—
58
—
233
—
1tCLCL – 35
—
—
4tCLCL – 100
—
ns
ns
ns
(from ALE Falling Edge)
Instruction Data Read Time
(from ALE Falling Edge)
From ALE Falling Edge to
PSEN Falling Edge
1tCLCL – 25
PSEN Signal Width
tPLPH
tPLIV
215
—
—
3tCLCL – 35
—
—
ns
ns
Instruction Data Read Time
(from PSEN Falling Edge)
Instruction Data Hold Time
(from PSEN Rising Edge)
Bus Floating Time after Instruction
Data Read (from PSEN Rising Edge)
Address Output Time from
PSEN Rising Edge
145
3tCLCL – 105
tPXIX
tPXIZ
tPXAV
tAVIV
tPLAZ
0
—
63
—
312
0
0
—
—
1tCLCL – 20
—
ns
ns
ns
ns
ns
—
75
—
—
1tCLCL – 8
—
Instruction Data Read Time
(from Address Output)
Bus Floating Time (Address
Float from PSEN Falling Edge)
5tCLCL – 105
0
—
28/38
¡ Semiconductor
MSM80C31F/80C51F
External Program Memory Read Cycle
tLHLL
ALE
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN
tPXAV
tPXIZ
tLLAX
tPLAZ
tPXIX
INSTR
IN
PORT0
A0~A7
A0~A7
tAVIV
A8~A15
A8~A15
A8~A15
PORT2
29/38
¡ Semiconductor
MSM80C31F/80C51F
External Data Memory Access AC Characteristics 1
(V = 5 V ±20%, V = 0 V, Ta = –40°C to +85°C; load capacitance for Port 0, ALE, and PSEN =
CC
SS
100 pF ; load capacitance for all other outputs = 80 pF)
Variable Clock
See Guaranteed
Operating Range
12 MHz Clock
Parameter
Symbol
Unit
Min.
—
Max.
—
Min.
Max.
XTAL1, XTAL2 Oscillation Cycle
ALE Single Width
tCLCL
tLHLL
tAVLL
62.5
—
—
—
ns
ns
ns
126
43
—
2tCLCL – 40
1tCLCL – 40
Adderss Setup Time
—
(to ALE Falling Edge)
Adderss Hold Time
tLLAX
48
—
1tCLCL – 35
—
ns
(from ALE Falling Edge)
RD Single Width
tRLRH
tWLWH
tRLDV
400
400
—
—
—
6tCLCL – 100
6tCLCL – 100
—
—
—
ns
ns
ns
WR Single Width
RAM Data Read Time
(from RD Single Falling Edge)
RAM Data Read Hold Time
(from RD Single Rising Edge)
Data Bus Floating Time
(from RD Single Rising Edge)
RAM Data Read Time
(from ALE Single Falling Edge)
RAM Data Read Time
(from Address Output)
RD/WR Output Time from
ALE Falling Edge
251
5tCLCL – 165
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
0
—
96
0
—
ns
ns
ns
ns
ns
ns
—
—
—
2tCLCL – 70
8tCLCL – 150
9tCLCL – 165
3tCLCL + 50
—
—
516
585
300
—
—
—
200
203
3tCLCL – 50
4tCLCL – 130
RD/WR Output Time from
Address Output
RD Output Time from Data Output
Time from Data Output to
WR Rising Edge
tQVWX
tQVWH
23
—
—
1tCLCL – 60
—
—
ns
ns
433
7tCLCL – 150
Data Hold Time (WR Rising Edge)
Time from RD Output to
Address Float
tWHQX
tRLAZ
33
—
—
0
1tCLCL – 50
—
—
0
ns
ns
Time from RD/WR Rising
Edge to ALE Rising Edge
tWHLH
43
133
1tCLCL – 40
1tCLCL + 50
ns
30/38
¡ Semiconductor
MSM80C31F/80C51F
External Data Memory Access AC Characteristics 2
(V = 2.5 to 4.0 V, V = 0 V, Ta = –40°C to +85°C; load capacitance for Port 0, ALE, and PSEN =
CC
SS
100 pF ; load capacitance for all other outputs = 80 pF)
Variable Clock
12 MHz Clock
See Guaranteed
Operating Range
Parameter
Symbol
Unit
Min.
—
Max.
—
Min.
Max.
XTAL1, XTAL2 Oscillation Cycle
ALE Single Width
tCLCL
tLHLL
tAVLL
62.5
—
—
—
ns
ns
ns
126
43
—
2tCLCL – 40
1tCLCL – 40
Adderss Setup Time
—
(to ALE Falling Edge)
Adderss Hold Time
tLLAX
48
—
1tCLCL – 35
—
ns
(from ALE Falling Edge)
RD Single Width
tRLRH
tWLWH
tRLDV
400
400
—
—
—
6tCLCL – 100
6tCLCL – 100
—
—
—
ns
ns
ns
WR Single Width
RAM Data Read Time
(from RD Single Falling Edge)
RAM Data Read Hold Time
(from RD Single Rising Edge)
Data Bus Floating Time
(from RD Single Rising Edge)
RAM Data Read Time
(from ALE Single Falling Edge)
RAM Data Read Time
(from Address Output)
RD/WR Output Time from
ALE Falling Edge
251
5tCLCL – 165
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
0
—
96
0
—
ns
ns
ns
ns
ns
ns
—
—
—
—
2tCLCL – 70
8tCLCL – 150
9tCLCL – 165
—
516
585
300
—
—
150
203
3tCLCL – 100 3tCLCL + 50
RD/WR Output Time from
Address Output
4tCLCL – 130
—
RD Output Time from Data Output
Time from Data Output to
WR Rising Edge
tQVWX
tQVWH
23
—
—
1tCLCL – 60
—
—
ns
ns
433
7tCLCL – 150
Data Hold Time (WR Rising Edge)
Time from RD Output to
Address Float
tWHQX
tRLAZ
33
—
—
0
1tCLCL – 50
—
—
0
ns
ns
Time from RD/WR Rising
Edge to ALE Rising Edge
tWHLH
43
183
1tCLCL – 40 1tCLCL + 100
ns
31/38
¡ Semiconductor
MSM80C31F/80C51F
External Data Memory Read Cycle
tWHLH
tLHLL
ALE
PSEN
tLLDV
tLLWL
tRLRH
RD
tRHDZ
tAVLL
tLLAX tRLAZ
tRLDV
tRHDX
A0~A7
PCL
A0~A7
A0~A7
PCL
INSTR
IN
PORT 0
PORT 2
Rr or DPL
tAVWL
tAVDV
PCH
A8~A15 PCH
P2.0~P2.7 DATA or A8~A15 DPH
A8~A15 PCH
External Data Memory Write Cycle
tWHLH
tLHLL
ALE
PSEN
tLLWL
tWLWH
WR
tQVWH
tAVLL
tWHQX
tLLAX
tQVWX
A0~A7
PCL
A0~A7
Rr or DPL
A0~A7
PCL
INSTR
IN
PORT 0
PORT 2
DATA (ACC)
tAVWL
A8~A15
PCH
A8~A15 PCH
P2.0~P2.7 DATA or A8~A15 DPH
A8~A15 PCH
32/38
¡ Semiconductor
MSM80C31F/80C51F
Serial Port Timing (I/O Expansion Mode) AC Characteristics 1
(Ta = –40°C to +85°C ; VCC = 5 V 20ꢀ ; VSS = 0 V)
Symbol
tXLXL
Max.
Parameter
Serial port clock cycle time
Min.
12tCLCL
10tCLCL – 133
2tCLCL – 117
0
Unit
ns
—
tQVXH
—
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
ns
tXHQX
—
—
ns
tXHDX
ns
tXHDV
10tCLCL – 133
—
ns
MACHINE
CYCLE
0
1
2
3
4
5
6
7
8
ALE
tXLXL
SHIFT
CLOCK
tXHQX
tQVXH
OUTPUT
DATA
0
1
2
3
4
5
6
7
tXHDV
tXHDX
INPUT
DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
33/38
¡ Semiconductor
MSM80C31F/80C51F
Serial Port Timing (I/O Expansion Mode) AC Characteristics 2
(Ta = –40°C to +85°C ; VC C =2.5 to 4.0 V ; VSS = 0 V)
Symbol
tXLXL
Max.
Parameter
Serial port clock cycle time
Min.
12tCLCL
10tCLCL – 133
2tCLCL – 117
0
Unit
ns
—
tQVXH
—
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
ns
tXHQX
—
—
ns
tXHDX
ns
tXHDV
10tCLCL – 133
—
ns
MACHINE
CYCLE
0
1
2
3
4
5
6
7
8
ALE
tXLXL
SHIFT
CLOCK
tXHQX
tQVXH
OUTPUT
DATA
0
1
2
3
4
5
6
7
tXHDV
tXHDX
INPUT
DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
34/38
¡ Semiconductor
MSM80C31F/80C51F
AC Characteristics Measuring Conditions
Input/output signal
VOH
VOH
VIH
VIL
VIH
VIL
TEST POINT
VOL
VOL
*
The input signals in AC test mode are either V
(logic "1") or V (logic "0") input signals
OH OL
where logic "1" corresponds to a CPU output signal waveform measuring point in excess of
, and logic "0" to a point below V .
V
IH
IL
Floating
Floating
VOH
VOH
VIH
VIL
VIH
VIL
VOL
VOL
*
The port 0 floating interval is measured from the time the port 0 pin voltage drops below V
IH
after sinking to GND at 2.4 mA when switching to floating status from a "1" output, and from
the time the port 0 pin voltage exceeds V after connecting to a 400 mA source when
IL
switching to floating status from a "0" output.
XTAL1 External Clock Input Waveform Conditions
Variable Clock
Parameter
Symbol
See Guaranteed Operating Range
Min.
Max.
16
Unit
MHz
ns
External Clock Frequency
High Time
1/tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
DC
20
20
—
—
—
Low Time
—
ns
Rise Time
20
ns
Fall Time
20
ns
External clock waveform
VCC – 0.5
0.7VCC
0.2VCC – 0.1
tCHCX
0.45 V
tCHCL
tCLCH
tCLCX
tCLCL
35/38
¡ Semiconductor
MSM80C31F/80C51F
PACKAGE DIMENSIONS
(Unit : mm)
DIP40-P-600-2.54
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
6.10 TYP.
36/38
¡ Semiconductor
MSM80C31F/80C51F
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.41 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
37/38
¡ Semiconductor
MSM80C31F/80C51F
(Unit : mm)
QFJ44-P-S650-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
2.00 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
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E2Y0002-29-11
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1995 Oki Electric Industry Co., Ltd.
Printed in Japan
相关型号：
MSM80C51F-XXXGS
Microcontroller, 8-Bit, MROM, 12MHz, CMOS, PQFP44, 0.80 MM PITCH, PLASTIC, QFP-44
OKI
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