MSM98P05 [OKI]

Voice Synthesis IC with Built-in 2-Mbit OTP ROM; 语音合成芯片,内置的2 - Mbit的OTP ROM
MSM98P05
型号: MSM98P05
厂家: OKI ELECTRONIC COMPONETS    OKI ELECTRONIC COMPONETS
描述:

Voice Synthesis IC with Built-in 2-Mbit OTP ROM
语音合成芯片,内置的2 - Mbit的OTP ROM

语音合成 OTP只读存储器
文件: 总14页 (文件大小:151K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
E2D0019-39-92  
Preliminary  
This version: Sep. 1999  
Previous version: May. 1997  
¡ Semiconductor  
MSM98P05  
Voice Synthesis IC with Built-in 2-Mbit OTP ROM  
GENERAL DESCRIPTION  
The MSM98P05 is a PCM-based voice synthesis IC with built-in 2-Mbit OTP (One Time PROM).  
This IC employs OKI nonlinear PCM algorithm and straight PCM algorithm for playback and  
contains a current mode 10-bit D/A converter and a low-pass filter.  
External control can be made easily by the built-in edit ROM that can form sentences by linking  
phrases. With OKI Voice Analyzing/Editing Tool, the built-in edit ROM can be set up and also  
the built-in ROM data can be created and evaluated easily.  
With the stand-alone mode/microcontroller interface mode switching pin, the MSM98P05 can  
support various applications.  
The products with build-in OTP are suited to applications to be produced in small quantities in  
awidevarietyorinshortdeliverytime. Demandlikethese, thatis, productioninsmallquantities  
in a wide variety and delivery with an early deadline is what the MSM9800 family of products  
with built-in mask ROM cannot meet.  
FEATURES  
• 8-bit OKI nonlinear PCM algorithm and 8-bit straight PCM algorithm  
• Built-in edit ROM  
• Random playback function  
• Sampling frequency  
: 4.0 kHz/5.3 kHz/6.4 kHz/8.0 kHz/10.6 kHz/12.8 kHz/  
16.0 kHz  
Note: IfRCoscillationisselected, 10.6kHz, 12.8kHz, and  
16.0 kHz cannot be selected.  
• Maximum number of phrases  
: 63 (Microcontroller interface mode)  
56 (Stand-alone mode)  
• Built-in current mode 10-bit D/A converter  
• Built-in low-pass filter (LPF)  
• Standby function  
• RC oscillation (256 kHz)/ceramic oscillation (4.096 MHz) selectable  
• Package options:  
20-pin plastic DIP (DIP20-P-300-2.54-W1) (Product name : MSM98P05RS)  
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM98P05GS-K)  
1/13  
VPP  
PGM  
Program Circuit  
A2  
A1  
2-Mbit OTP ROM  
(Including 11 Kbits of  
Edit ROM & Address ROM)  
A0  
Address &  
Switching  
Controller  
18-Bit  
Multiplexer  
6
SW2  
SW1  
SW0  
8
CPU/STD  
Random  
Circuit  
DATA  
Controller  
RND  
18-Bit  
Address Counter  
PCM  
Synthesizer  
I/O  
Interface  
BUSY  
10  
10-Bit  
DAC  
&
OSC1  
OSC2  
OSC  
XT/RC  
LPF  
Timing Controller  
OSC3/TEST  
XT/CR  
VDD  
GND  
RESET  
AOUT  
VREF  
¡ Semiconductor  
MSM98P05  
PIN CONFIGURATION (TOP VIEW)  
VPP  
A0  
1
2
3
4
5
6
7
8
9
20 PGM  
19 SW2  
A1  
18 SW1  
A2  
17 SW0  
RESET  
XT/CR  
BUSY  
GND  
VREF  
16 RND  
15 CPU/STD  
14 OSC3/TEST  
13 OSC2  
12 OSC1  
11 VDD  
AOUT 10  
20-Pin Plastic DIP  
Note: Applies to MSM98P05RS  
VDD  
OSC1  
1
2
3
4
5
6
7
8
9
24 AOUT  
23 VREF  
22 GND  
21 NC  
OSC2  
NC  
OSC3/TEST  
NC  
20 BUSY  
19 NC  
CPU/STD  
RND  
18 XT/CR  
17 RESET  
16 VPP  
15 A2  
PGM  
SW0 10  
SW1 11  
SW2 12  
14 A1  
13 A0  
NC: No connection  
24-Pin Plastic SOP  
Note: Applies to MSM98P05GS-K  
3/13  
¡ Semiconductor  
MSM98P05  
PIN DESCRIPTIONS  
Pin  
Symbol Type  
Description  
DIP SOP  
The IC enters the standby state if this pin is set to "L" level. At this time,  
oscillation stops and AOUT drives a current of 0mA and becomes GND level,  
then the IC returns to the initial state. Apply a "L" pulse during power-on.  
This pin has an internal pull-up resistor.  
5
17  
RESET  
I
Outputs "L" level while voice is being played back.  
In "H" level when power is turned ON.  
7
6
20  
18  
7
BUSY  
XT/CR  
O
I
XT/RC switching pin. Set to "H" level if ceramic oscillation is used. Set to "L"  
level if RC oscillation is used.  
Microcontroller interface/stand-alone mode switching pin. Set to "L" level if  
the IC is used in stand-alone mode.  
15  
CPU/STD  
I
Volume setting pin. If this pin is set to GND level, the maximum amplitude is  
delivered. If this pin is set to VDD level, the minimum amplitude is delivered.  
This pin is internally connected to a pull-down resistor of approx. 10 kW  
during IC operation.  
9
23  
VREF  
I
Voice output pin.  
The voice signals are output as current changes. A logic "L" is output from  
this pin in standby state.  
10  
24  
AOUT  
O
8
22  
1
GND  
VDD  
Ground pin.  
Power supply pin. Insert a bypass capacitor of 0.1 mF or more between VDD  
and GND pins.  
11  
Ceramic oscillator connection pin when ceramic oscillation is selected.  
RC connection pin when RC oscillation is selected.  
Input from this pin if external clock is used.  
12  
13  
14  
16  
2
3
5
8
OSC1  
OSC2  
I
O
O
I
Ceramic oscillator connection pin when ceramic oscillation is selected.  
RC connection pin when RC oscillation is selected.  
Leave this pin open if external clock is used.  
Outputs "L" level in standby state.  
Leave this pin open when ceramic oscillation is used.  
RC connection pin when RC oscillation is selected.  
Outputs "H" level in standby state when RC oscillation is selected.  
Random playback starts if RND pin is set to "L" level.  
Fetches addresses from random address generation circuit in the IC at the  
falling edge of RND. Set to "H" level when the random playback function is  
not used. This pin has internal pull-up resistor.  
OSC3/TEST  
RND  
4/13  
¡ Semiconductor  
MSM98P05  
Pin  
Symbol Type  
Description  
DIP SOP  
Phrase input pins corresponding to playback sound.  
If input changes, SW0 to SW2 pins fetch addresses after 16 ms and start voice  
synthesis. Each of these pins has internal pull-down resistor.  
Phrase input pins corresponding to playback sound.  
17-19 10-12 SW0 - SW2  
I
2-4 13-15  
A0 - A2  
VPP  
I
I
Logic input to A0 pin becomes invalid if the random playback function is used.  
Power supply pin for writing to the built-in OTP. This pin should be set to "H"  
level or be open during playback.  
1
16  
9
Interface pin for writing to the built-in OTP. This pin should be set to "L"  
level or be open during playback.  
20  
PGM  
5/13  
¡ Semiconductor  
MSM98P05  
APPLICATION CIRCUITS  
VDD  
S3  
S2  
S1  
SW0  
SW1  
AOUT  
VPP  
SW2  
PGM  
VREF  
RND  
BUSY  
A0  
A1  
RESET  
S4  
A2  
OSC3  
OSC2  
OSC1  
XT/CR  
CPU/STD  
GND  
A2  
0
A1  
A0  
0
SW2  
SW1  
SW0  
Address [HEX]  
S1  
S2  
S3  
S1  
S2  
S3  
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
01  
02  
04  
09  
0A  
0C  
S4="L"  
S4="H"  
0
0
0
0
0
1
0
1
0
1
Application Circuit for Playing Six Phrases Using Four Switches  
6/13  
1
2
3
4
5
6
7
VDD  
SW0  
SW1  
AOUT  
SW2  
VREF  
VPP  
PGM  
XT/CR  
BUSY  
CPU/STD  
RND  
RESET  
A0  
OSC3  
OSC2  
OSC1  
A1  
A2  
GND  
VPP  
PGM  
Program Circuit  
I5  
I4  
I3  
I2  
I1  
I0  
2-Mbit OTP ROM  
(Including 11 Kbits of  
Edit ROM & Address ROM)  
18-Bit  
Multiplexer  
6
Address  
Controller  
8
DATA  
Controller  
18-Bit  
Address Counter  
PCM  
Synthesizer  
CPU/STD  
I/O  
Interface  
ST  
NAR  
10  
10-Bit  
DAC  
&
OSC1  
OSC2  
OSC  
XT/RC  
LPF  
Timing Controller  
OSC3/TEST  
XT/CR  
VDD  
GND  
RESET  
AOUT  
VREF  
¡ Semiconductor  
MSM98P05  
PIN CONFIGURATION (TOP VIEW)  
VPP  
I3  
1
2
3
4
5
6
7
8
9
20 PGM  
19 I2  
I4  
18 I1  
I5  
17 I0  
RESET  
XT/CR  
NAR  
GND  
VREF  
16 ST  
15 CPU/STD  
14 OSC3/TEST  
13 OSC2  
12 OSC1  
11 VDD  
AOUT 10  
20-Pin Plastic DIP  
Note: Applies to MSM98P05RS  
VDD  
OSC1  
1
2
3
4
5
6
7
8
9
24 AOUT  
23 VREF  
22 GND  
21 NC  
OSC2  
NC  
OSC3/TEST  
NC  
20 NAR  
19 NC  
CPU/STD  
ST  
18 XT/CR  
17 RESET  
16 VPP  
15 I5  
PGM  
I0 10  
I1 11  
I2 12  
14 I4  
13 I3  
NC: No connection  
24-Pin Plastic SOP  
Note: Applies to MSM98P05GS-K  
9/13  
¡ Semiconductor  
MSM98P05  
PIN DESCRIPTIONS  
Pin  
Symbol Type  
Description  
DIP SOP  
The IC enters the standby state if this pin is set to "L" level. At this time,  
oscillation stops and AOUT drives a current of 0mA and becomes GND level,  
then the IC returns to the initial state. If the power cannot be applied within 1ms,  
apply an "L" pulse during power-on. This pin has an internal pull-up resistor.  
Signal output pin that indicates whether the register in the address controller  
to latch the 10-15 addresses (see Block Diagram) is idle. NAR at "H" level  
indicates that the LATCH is empty and ST input is enabled.  
5
7
17  
20  
RESET  
I
NAR  
O
XT/RC switching pin. Set to "H" level if ceramic oscillation is used. Set to "L"  
level if RC oscillation is used.  
6
18  
7
XT/CR  
I
I
Microcontroller interface/stand-alone mode switching pin. Set to "H" level if  
the IC is used in microcontroller interface mode.  
Volume setting pin. If this pin is set to GND level, the maximum amplitude is  
delivered. If this pin is set to VDD level, the minimum amplitude is delivered.  
This pin is internally connected to a pull-down resistor of approx. 10 kW  
during IC operation.  
15  
CPU/STD  
9
23  
VREF  
I
Voice output pin.  
The voice signals are output as current changes. A logic "L" is output from  
this pin in standby state.  
10  
24  
AOUT  
O
8
22  
1
GND  
VDD  
Ground pin.  
Power supply pin. Insert a bypass capacitor of 0.1 mF or more between this  
pin and the GND pin.  
11  
Ceramic oscillator connection pin when ceramic oscillation is selected.  
RC connection pin when RC oscillation is selected.  
Input from this pin if external clock is used.  
12  
13  
2
3
OSC1  
OSC2  
I
Ceramic oscillator connection pin when ceramic oscillation is selected.  
RC connection pin when RC oscillation is selected.  
Leave this pin open if external clock is used.  
O
Outputs "L" level in standby state.  
Leave this pin open when ceramic oscillation is used.  
RC connection pin when RC oscillation is selected.  
Outputs "H" level in standby state when RC oscillation is selected.  
Voice synthesis starts at fall of ST, and addresses I0 to I5 are fetched at rise  
of ST. Input ST when NAR, the status signal, is at "H" level.  
This pin has internal pull-up resistor.  
14  
16  
5
8
OSC3/TEST  
O
I
ST  
17-19  
2-4  
Phrase input pins corresponding to vocalized sound.  
10-15  
16  
I0 - I5  
VPP  
I
I
Power supply pin for writing to the built-in OTP. This pin should be set to "H"  
1
level or be open.  
Interface pin for writing to the built-in OTP. This pin should be set to "L" level  
or be open.  
20  
9
PGM  
10/13  
¡ Semiconductor  
MSM98P05  
APPLICATION CIRCUIT  
+
VDD  
VCC  
P1.5  
P1.4  
P1.3  
P1.2  
P1.1  
P1.0  
I5  
I4  
I3  
I2  
I1  
I0  
VREF  
SP  
AIN  
AOUT  
SP  
P2.2  
P2.1  
ST  
RESET  
P3.0  
NAR  
VPP  
CPU/STD  
XT/CR  
OSC2  
RESET  
PGM  
OSC3  
STBY  
VR  
OSC1  
XTAL1 XTAL2  
GND  
GND  
SEL  
+
Application Circuit when Used as Microcontroller Interface  
11/13  
¡ Semiconductor  
PACKAGE DIMENSIONS  
DIP20-P-300-2.54-W1  
MSM98P05  
(Unit : mm)  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
42 alloy  
Solder plating  
5 mm or more  
1.50 TYP.  
12/13  
¡ Semiconductor  
MSM98P05  
(Unit : mm)  
SOP24-P-430-1.27-K  
Mirror finish  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
42 alloy  
Solder plating  
5 mm or more  
0.58 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
13/13  
E2Y0002-29-62  
NOTICE  
1.  
The information contained herein can change without notice owing to product and/or  
technical improvements. Before using the product, please make sure that the information  
being referred to is up-to-date.  
2.  
The outline of action and examples for application circuits described herein have been  
chosen as an explanation for the standard action and performance of the product. When  
planning to use the product, please ensure that the external conditions are reflected in the  
actual circuit, assembly, and program designs.  
3.  
4.  
When designing your product, please use our product below the specified maximum  
ratings and within the specified operating ranges including, but not limited to, operating  
voltage, power dissipation, and operating temperature.  
Oki assumes no responsibility or liability whatsoever for any failure or unusual or  
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration  
or accident, improper handling, or unusual physical or electrical stress including, but not  
limited to, exposure to parameters beyond the specified maximum ratings or operation  
outside the specified operating range.  
5.  
6.  
Neither indemnity against nor license of a third party’s industrial and intellectual property  
right, etc. is granted by us in connection with the use of the product and/or the information  
and drawings contained herein. No responsibility is assumed by us for any infringement  
of a third party’s right which may result from the use thereof.  
The products listed in this document are intended for use in general electronics equipment  
for commercial applications (e.g., office automation, communication equipment,  
measurement equipment, consumer electronics, etc.). These products are not authorized  
for use in any system or application that requires special or enhanced quality and reliability  
characteristics nor in any system or application where the failure of such system or  
application may result in the loss or damage of property, or death or injury to humans.  
Such applications include, but are not limited to, traffic and automotive equipment, safety  
devices, aerospace equipment, nuclear power control, medical equipment, and life-support  
systems.  
7.  
Certain products in this document may need government approval before they can be  
exported to particular countries. The purchaser assumes the responsibility of determining  
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir  
own expense for these.  
8.  
9.  
No part of the contents contained herein may be reprinted or reproduced without our prior  
permission.  
MS-DOS is a registered trademark of Microsoft Corporation.  
Copyright 1999 Oki Electric Industry Co., Ltd.  
Printed in Japan  

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