MSMP587 [OKI]
Built-in 16 bit PWM and 8 bit A/D Converter, High-speed High-preformance 16 bit Microcontroller; 内建16位PWM和8位A / D转换器，高速高性能与16位微控制器
| 型号： | MSMP587 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Built-in 16 bit PWM and 8 bit A/D Converter, High-speed High-preformance 16 bit Microcontroller |
| 文件： | 总24页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2E1033 -27-Y6
Preliminary
This version: Jan. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM66585/586/587/P587/Q587
Built-in 16 bit PWM and 8 bit A/D Converter, High-speed High-preformance 16 bit
Microcontroller
GENERAL DESCRIPTION
MSM66585/586/587 are high-performance CMOS 16-bit microcontrollers that integrate a 16-
bit CPU, ROM, RAM, 8-bit A/D converter, serial port, timers, and PWM. They also allow ROM
and RAM to be expanded externally.
TheMSM66P587isofOTP(One-TimePROM)versionandtheMSM66Q587isofFlashEEPROM
version.
FEATURES
• Powerful instruction set
Instruction set superior in orthogonal matrics
8/16-bit arithmetic instructions
Multiply/divide instructions
Bit manipulation instructions
Bit logical operation instructions
ROM table reference instructions
• Abandant addressing modes
Register addressing
Page addressing
Pointer register indirect addressing
Stack addressing
Immediate addressing
• Minimum instruction cycle
100 ns at 20 MHz (4.5V-5.5V)
200 ns at 10 MHz (2.7V-5.5V)
• Program memory (ROM)
Internal: 64 KB (M66587/M66P587/M66Q587), 48 KB (M66585/586)
External: 1 MB, EA pin active
• Data memory (RAM)
Internal: 2 KB
External: 1022 KB
• I/O ports
Analog input-only port: 4 lines (test pins for M66585)
Input/output port:
• Timers
Maximum 80 lines (40 lines with programmable pull-up)
Free-running counter:
Realtime output:
General autoreload timer: 8-bit ¥ 1
• 16-bit PWM
16-bit ¥ 1
16-bit ¥ 2
Input clock divider:
• 8-bit serial port
1 divider
Synchronous with BRG: 1 port
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¡ Semiconductor
MSM66585/586/587/P587/Q587
• A/D converter
8-bit resolution:
• Interrupts
Non-maskable:
Maskable:
4 channels
1 interrupt
9 internal, 4 external (12 vectors)
3-level priority
• ROM window function
• Standby modes
Halt mode
Stop mode
• Package
100-pin TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM66585TS-K)
(Product name : MSM66586TS-K)
(Product name : MSM66587TS-K)
(Product name : MSM66P587TS-K)
(Product name : MSM66Q587TS-K)
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EA
ALE/P5_5
PSEN/P5_4
RD/P7_1
WR/P7_0
WAIT/P7_2
CPU Core
16-bit RTO/PWM
Timer
P2_4/RT08
P2_5/RTO9
Control
RAM
2 KB
Registers
SSP
LRB
PSW
PC
CSR
AD0/P0_0
AD7/P0_7
A8/P1_0
Memory Control
Pointing R
Local R.
*1
DSR TSR
ROM
P6_2/RXD1
P6_3/TXD1
P6_4/RXC1
P6_5/TXC1
64 KB
Serial Port
A15/P1_7
A16/P9_0
ALU
Instruction
Decoder
PWM
*2
P7_4/PWM0
A19/P9_3
ALU Control
ACC
VREF
AGND
AI0
A to D
Converter
AI3
P4_0/ETMCK
Event Timer
Interrupt
P6_0/INTO
P6_1/INT1
P12_2/INT2
P12_3/INT3
NMI
System Control
Port Control
P7_3/CLKOUT
Peripheral
¡ Semiconductor
MSM66585/586/587/P587/Q587
PIN CONFIGURATION (TOP VIEW)
12_0
P12_1
1
2
P9_6
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9_5
P9_4
INT2/P12_2
INT3/P12_3
P12_4
3
P9_3/A19
P9_2/A18
P9_1/A17
P9_0/A16
GND
4
5
P12_5
6
P12_6
7
P12_7
8
V
V
9
DD
DD
P1_7/A15
P1_6/A14
P1_5/A13
P1_4/A12
P1_3/A11
P1_2/A10
P1_1/A9
*(V ) V
DD REF
10
(GND) AGND 11
(TEST0) AI0 12
(TEST1) AI1 13
(TEST2) AI2 14
(TEST3) AI3 15
GND 16
P1_0/A8
V
17
DD
ETMCK/P4_0 18
P4_1 19
P0_7/AD7
P0_6/AD6
P0_5/AD5
P0_4/AD4
P0_3/AD3
P0_2/AD2
P0_1/AD1
P0_0/AD0
P4_2 20
P4_3 21
P4_4 22
P4_5 23
P4_6 24
P4_7 25
*
For MSM66585, pin name is in parentheses ( ).
4/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS
Symbol
Type
Description
Port 0 is 8 input/output pins. Input or output can be specified for each bit with the
Port 0 Mode Register (P0IO). Pull-up resistors can be specified for each bit with the
Port 0 Pull-Up Register (P0PUP).
These pins also function as time-multiplexed address outputs and data input/output
pins (AD0-AD7) when accessing memory that has been expanded externally
(program or data memory).
P0_0-P0_7/
AD0-AD7
I/O
After reset (by RES signal input, BRK instruction execution, or op code trap), P0 will
be high-impedance inputs.
Port 1 is 8 input/output pins. Input or output can be specified for each bit with the
Port 1 Mode Register (P1IO). Pull-up resistors can be specified for each bit with the
Port 1 Pull-Up Register (P1PUP).
P1_0-P1_7 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 1 Secondary Function
Control Register (P1SF). The input/output settings by P1IO will be ignored for pins
that have been set to the secondary function by P1SF.
These pins function as output pins for address A8-A15 when accessing program
memory or data memory that has been expanded externally. When the EA pin is low,
A8-A15 will be output regardless of P1SF settings.
P1_0-P1_7/
A8-A15
I/O
After reset (by RES signal input, BRK instruction execution, or op code trap), P1 will
be high-impedance inputs.
P2_4 and P2_5 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 2 Secondary Function
Control Register (P2SF). The input/output settings of P2IO will be ignored for pins
that have been set to the secondary function by P2SF.
These pins output a previously set level when the value of Timer Registers 8 and 9
match a selected counter value.
P2_0-P2_3
P2_4-P2_5/
RT08-RT09
P2_6-P2_7
I/O
I/O
After reset (by RES signal input, BRK instruction execution, or op code trap), P2 will
be high-impedance inputs.
Port 4 is 8 input/output pins. Input or output can be specified for each bit with the
Port 4 Mode Register (P4IO). Pull-up resistors can be specified for each bit with the
Port 4 Pull-Up Register (P4PUP).
P4_0 also has a secondary function as an input pin for internal operation. Its secondary
function can be set for the bit with the Port 4 Secondary Function Control Register (P4SF).
The input/output settings by P4IO will be ignored for pins that have been set to the
secondary function by P4SF.
P4_0/ETMCK
P4_1-P4_7
This is the external clock input pin for the counter of a general 8-bit timer.
After reset (by RES signal input, BRK instruction execution, or op code trap), P4 will
be high-impedance inputs.
Port 5 is 2 input/output pins. Input or output can be specified for each bit with the
Port 5 Mode Register (P5IO).
P5_4 and P5_5 also have a secondary function as output pins for internal operation.
Their secondary function can be set for each bit with the Port 5 Secondary Function
Control Register (P5SF). The input/output settings of P5IO will be ignored for pins
that have been set to the secondary function by P5SF.
PSEN (P5_4):
This pin outputs the strobe signal for read operations when external program memory
is accessed. Operation will automatically switch to the secondary function when the
EA pin is low. This pin will be pulled up when both the EA pin and RESET pin are low.
ALE (P5_5):
P5_4/PSEN
P5_5/ALE
I/O
This pin outputs the strobe for externally latching the lower 8 address bits output from
P0 when external memory is accessed. Operation will automatically switch to the
secondary function when the EA pin is low. This pin will be pulled up when both the
EA pin and RESET pin are low.
After reset (by RES signal input, BRK instruction execution, or op code trap), P5 will
be high-impedance inputs.
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¡ Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS (Continued)
Symbol
Type
Description
Port 6 is 6 input/output pins. Input or output can be specified for each bit with the
Port 6 Mode Register (P6IO).
P6_0-P6_5 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 6 Secondary Function
Control Register (P6SF). The input/output settings of P6IO will be ignored for pins
that have been set to the secondary function by P6SF.
INT0 (P5_0), INT1 (P6_1):
P6_0/INT0
P6_1/INT1
P6_2/RXD1
P6_3/TXD1
P6_4/RXC1
P6_5/TXC1
These pins input external interrupts 0 and 1.
RXD1 (P6_2):
This pin inputs receive data to the Serial Port 1 receive circuit.
TXD1 (P6_3):
I/O
This pin outputs transmit data to the Serial Port 1 transmit circuit.
RXC1 (P6_4):
This pin outputs the shift clock when the Serial Port 1 receive circuit is in master mode.
It inputs the shift clock when the receive circuit is in slave mode.
TXC1 (P6_4):
This pin outputs the shift clock when the Serial Port 1 transmit circuit is in master mode.
It inputs the shift clock when the transmit circuit is in slave mode.
After reset (by RES signal input, BRK instruction execution, or op code trap), P6 will be
high-impedance inputs.
Port 7 is 8 input/output pins. Input or output can be specified for each bit with the
Port 7 Mode Register (P7IO).
P7_0-P7_4 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 7 Secondary Function
Control Register (P7SF). The input/output settings of P7IO will be ignored for pins
that have been set to the secondary function by P7SF.
WR (P7_0):
This pin outputs the strobe signal for write operations when external data memory
is accessed.
P7_0/WR
P7_1/RD
P7_2/WAIT
P7_3/CLKOUT
P7_4/PWM0
P7_5-P7_7
RD (P7_1):
This pin outputs the strobe signal for read operations when external data memory
is accessed.
WAIT (P7_2):
This pin inputs a wait to the internal CPU when external data memory with a slow
access time is accessed. CPU is driven to "WAIT" state during WAIT pin high.
CLKOUT (P7_3):
I/O
This pin outputs the clock pulses set by the Peripheral Control Register (PRPHF).
PWM0 (P7_4):
This pin outputs PWM0.
After reset (by RES signal input, BRK instruction execution, or op code trap), P7 will
be high-impedance inputs.
When P7_0 and P7_1 are used as their secondary functions (WR, RD), they need to
be connected externally to pull-up resistors.
Port 8 is 8 input/output pins. Input or output can be specified for each bit with the
Port 8 Mode Register (P8IO).
I/O
P8_0-P8_7
After reset (by RES signal input, BRK instruction execution, or op code trap), P8 will
be high-impedance inputs.
6/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS (Continued)
Symbol
Type
Description
Port 9 is 8 input/output pins. Input or output can be specified for each bit with the
Port 9 Mode Register (P9IO). Pull-up resistors can be specified for each bit with the
Port 9 Pull-Up Register (P9PUP).
P9_0-P9_3 also have a secondary function as output pins for internal operation.
Their secondary function can be set for each bit with the Port 9 Secondary Function
Control Register (P9SF). The input/output settings of P9IO will be ignored for pins
that have been set to the secondary function by P9SF.
P9_0P9_3/
A16-A19
P9_4-P9_7
A16-A19 (P9_0-P9_3):
I/O
These pins function as output pins for address A16-A19 when accessing program
memory or data memory that has been expanded externally. Note that program
memory address A16-A19 will be output even when accessing data memory that has
been expanded externally. When the EA pin is low and program memory that has
been expanded externally is accessed, A16-A19 will be output regardless of P9SF
settings.
After reset (by RES signal input, BRK instruction execution, or op code trap), P9 will
be high-impedance inputs.
Port 10 is 8 input/output pins. Input or output can be specified for each bit with the
Port 10 Mode Register (P10IO). Pull-up resistors can be specified for each bit with
the Port 10 Pull-Up Register (P10PUP).
I/O
I/O
P10_0-P10_7
After reset (by RES signal input, BRK instruction execution, or op code trap), P10 will
be high-impedance inputs.
Port 12 is 8 input/output pins. Input or output can be specified for each bit with the
Port 12 Mode Register (P12IO).
P12_2 and P12_3 also have a secondary function as input pins for internal operation.
Their secondary function can be set for each bit with the Port 12 Secondary Function
Control Register (P12SF). The input/output settings of P12IO will be ignored for pins
that have been set to the secondary function by P12SF.
INT2 (P12_2), INT3 (P12_3):
These pins input external interrupts 2 and 3.
After reset (by RES signal input, BRK instruction execution, or op code trap), P12 will
be high-impedance inputs.
P12_0-P12_1
P12_2-P12_3/
INT2-INT3
P12_4-P12_7
These are analog input pins for the A/D converter (test pins for MSM66585).
This is the reference voltage pin for the A/D converter (VDD for MSM66585).
This is the ground input pin for the A/D converter (GND for MSM66585).
AI0-AI3
VREF
I
I
I
AGND
This pins connect to a crystal oscillator, ceramic oscillator, or capacitors for base clock
oscillation. When the base clock is to be supplied externally, it should be input on the
OSC0 pin with the OSC1 pin left open.
I
OSC0
O
OSC1
I
I
NMI
This input pin requests a non-maskable interrupt.
This is an active-low reset input pin.
RES
When this pin is high, program addresses 0H-FFFFH will access internal program
memory and program addresses 10000H-FFFFFH will access external program memory.
To access external program memory, P1, P5, and P9 must be set with their secondary
function control registers.
I
EA
When this pin is low, all program addresses will access external program memory.
These are voltage pins. All VDD pins (9, 17, 37, 67, 93) should be connected to the
supply voltage (for MSM66585 connect pins 9, 10, 17, 37, 67, 93).
VDD
I
I
These are ground pins. All GND pins (16, 40, 68, 94) should be connected to ground
(for MSM66585 connect pins 11, 16, 40, 68, 94).
GND
7/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
MEMORY MAP
Program Area
Segment 0
0000H
Segment 1 to 15
0000H
Vector table area
74 bytes
0049H
004AH
VCAL table area
Internal ROM area
External ROM area
32 bytes
0069H
006AH
Vector table area
8 bytes
0071H
0072H
0FFFH
1000H
0FFFH
1000H
ACAL area
2 KB
ACAL area
2 KB
17FFH
1800H
17FFH
1800H
FFFFH
FFFFH
* For M66585 and M66586 addresses 0C000H to 0FFFFH of segment 0 are external ROM area.
8/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
Data Area
9/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
Area For Setting Local Registers
0000H
SFR area
0100H
0200H
0300H
Expanded SFR area
FIX area
R0
R1
R2
R3
R4
R5
R6
R7
R0
R1
0200H
ER0
ER1
ER2
ER3
ER0
Area for setting local registers:
Internal RAM
area
LRBL=
00H
Specify 8-byte block with 8-bits of
LRBL
0A00H
0208H
LRBL=
01H
External RAM
area
LRBL=
FFH
FFFFFH
R6
R7
ER3
0A00H
10/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
ABSOLUTE MAXIMUM RATINGS
Parameter
Digital power supply voltage
Input voltage
Symbol
VDD
Conditions
Rating
Units
V
–0.3 to +7.0
VI
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to AVDD+0.3
–0.3 to VREF
V
VO
GND=AGND=0V
Ta=25°C
V
Output voltage
Analog power supply voltage
Analog reference voltage
Analog input voltage
AVDD
VREF
VAI
V
V
V
mW
mW
°C
Per package
Per output
—
650
8
Power dissipation
Ta=70°C
PD
Storage temperature
TSTG
–50 to +150
RECOMMENDED OPERATING CONDITIONS
Parameter
Digital power supply
voltage
Symbol
Conditions
Range
Units
fOSC£20MHz
4.5 to 5.5
VDD
V
fOSC£10MHz
—
2.7 to 5.5
AVDD–0.3 to AVDD
AGND to VREF
2.0 to 5.5
Analog reference voltage
Analog input voltage
Memory hold voltage
VREF
VAI
V
V
—
VDDH
fOSC=0Hz
V
VDD=5V 10ꢀ
VDD=2.7 to 5.5V
2 to 20
MHz
MHz
fOSC
Ta
Operating frequency
Temperature range
2 to 10
—
–30 to +70
20
°C
—
MOS loads
P0, P5_4, P5_5,
P7_0, P7_1
2
—
Fan-out
N
TTL loads
P1, P2, P4, P6,
P7_2-P7_7,
1
—
P8-P10, P12
ALLOWABLE OUTPUT CURRENT
(VDD=2.7 to 5.5V, Ta=–30 to +70°C)
Parameter
"H" output pin (1 pin)
"H" output pin (total)
"L" output pin (1 pin)
Pin
All output pins
Symbol
IOH
Min.
—
Typ.
—
Max.
–2
Units
Total of all output pins
All output pins
SIOH
IOL
—
—
–40
5
—
—
Total of P0, P1, P5 and P7
Total of P2, P9 and P10
Total of P4 and P8
mA
50
"L" output pin (total)
SIOL
—
—
Total of P6 and P12
Total of all output pins
100
Note: Power and ground connections must be made to all external V
and GND pins.
DD
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¡ Semiconductor
MSM66585/586/587/P587/Q587
ELECTRICAL CHARACTERISTICS
DC Characteristics (V =5V±10%)
DD
(Ta=–30 to +70°C)
Parameter
Input high voltage
Input high voltage 2, 4, 5, 6, 7
Input low voltage
Input low voltage 2, 4, 5, 6, 7
Symbol
Conditions
Min
0.44VDD
0.80VDD
–0.3
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
5
Max
VDD+0.3
VDD+0.3
0.16VDD
0.2VDD
—
Units
1
—
VIH
1
—
VIL
–0.3
IO=–400mA
IO=–2.0 mA
VDD–0.4
VDD–0.6
VDD–0.4
Output high voltage
Output high voltage
Output low voltage
Output low voltage
1, 4
2
—
VOH
V
—
IO=–200mA
IO=–2.0 mA
V
DD–0.6
—
—
—
—
—
—
—
—
25
—
—
—
—
—
—
—
—
—
1, 4
2
IO=3.2mA
IO=5.0mA
IO=1.6mA
IO=5.0mA
0.4
0.8
VOL
0.4
0.8
Input leakage current
Input current
3, 6
1/–1
1/–250
15/–15
10
mA
5
IIH/IIL
VI=VDD/0V
Input current
7
1, 2, 4
2
ILO
Rpull
VO=VDD/0V
VI=0V
mA
kW
Output leakage current
Pull-up resistor
100
—
CI
Input capacitance
Output capacitance
pF
f=1MHz, Ta=25°C
7
—
CO
A/D conversion operating
A/D conversion stopped
VDD=2V, Ta=25°C*
*
Analog reference power supply
current
—
—
0.2
1
4
mA
IREF
mA
10
Supply current
10
mA
IDDS
(stop mode)
100
25
IDDH
IDD
10
Supply Current (halt mode)
Supply Current
fOSC=20MHz,
No Load
mA
45
70
1. Applies to P0.
2. Applies to P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12.
3. Applies to Ain.
4. Applies to P5_4, P5_5, P7_0, P7_1.
5. Applies to RES.
6. Applies to EA, NMI.
7. Applies to OSC0.
*
For input ports, V or 0 V. For other cases, unloaded.
DD
12/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
DC Characteristics (2.7V £ V £ 5.5V)
DD
(Ta=–30 to +70°C)
Parameter
Input high voltage
Input high voltage 2, 4, 5, 6, 7
Input low voltage
Input low voltage 2, 4, 5, 6, 7
Symbol
Conditions
Min
0.44VDD
0.80VDD
–0.3
Typ
—
—
—
—
—
—
—
—
—
—
Max Units
VDD+0.3
VDD+0.3
0.16VDD
0.2VDD
1
—
VIH
1
—
VIL
–0.3
VDD–0.4
IO=–400mA
IO=–2.0 mA
IO=–200mA
—
Output high voltage
Output high voltage
Output low voltage
Output low voltage
1, 4
2
V
V
DD–0.6
—
VOH
VDD–0.4
—
—
VDD–0.8
IO=–2.0 mA
IO=3.2mA
IO=5.0mA
IO=1.6mA
—
0.5
0.9
1, 4
2
—
VOL
—
—
—
—
—
—
25
40
—
—
—
—
—
—
0.5
IO=5.0mA
1.2
Input leakage current
Input current
3, 6
1/–1
IIH/IIL
VI=VDD/0V
1/–250
15/–15
10
mA
5
7
Input current
ILO
VO=VDD/0V
mA
kW
1, 2, 4
Output leakage current
VI=0V,VDD=5V 10ꢀ
VI=0V, VDD=3V 10ꢀ
50
100
100
Rpull
Pull-up resistor
200
—
—
CI
5
7
—
—
Input capacitance
Output capacitance
pF
f=1MHz, Ta=25°C
CO
VDD=5.5V
DD=3.3V
VDD=5.5V
DD=3.3V
—
—
—
—
4
2
A/D conversion
mA
operating
V
Analog reference power
supply current
IREF
—
—
—
—
—
—
—
—
0.2
1
10
5
A/D conversion
stopped
mA
V
VDD=2V, Ta=25°C*
*
10
100
15
10
50
25
Supply current (stop mode)
mA
IDDS
VDD=5V 10ꢀ
DD=3V 10ꢀ
DD=5V 10ꢀ
DD=3V 10ꢀ
5
IDDH
IDD
Supply current (halt mode)
Supply current
V
V
3
fOSC=10MHz,
No Load
mA
—
—
30
13
V
1. Applies to P0.
2. Applies to P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12.
3. Applies to Ain.
4. Applies to P5_4, P5_5, P7_0, P7_1.
5. Applies to RES.
6. Applies to EA, NMI.
7. Applies to OSC0.
*
For input ports, V or 0 V. For other cases, unloaded.
DD
13/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
AC Characteristics (V =5V±10%)
DD
• External Program Memory Control
(Ta=–30 to +70°C)
Parameter
Clock (OSC) pulse width
ALE pulse width
Symbol
tfW
Conditions
Min
25
Max
—
Units
—
tAW
2tfW–2
2tfW–5
tfW–3
2tfW–3
tfW–3
4tfW–3
0
—
tPW
—
PSEN pulse width
tPAD
tALS
tALH
tAHS
tAPH
tIS
tfW+3
2tfW+3
tfW+3
4tfW+3
tfW+3
—
PSEN pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Instruction setup time
Instruction hold time
ns
CL=50pF
15
tIH
0
tfW–3
CLK
ALE
tfW
tfW
tAW
PSEN
tPAD
tPW
AD 0-AD7
A 8-A19
PC 0-7
tALS
INST 0-7
tIS tIH
tALH
PC 8-19
tAHS
tAPH
14/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
• External Data Memory Control
(Ta=–30 to +70°C)
Parameter
Clock (OSC) pulse width
ALE pulse width
Symbol
tfW
tAW
Conditions
Min
25
Max
—
Units
—
2tfW–2
2tfW–5
2tfW–5
tfW–3
tfW–3
2tfW–3
tfW–3
3tfW–3
tfW–3
15
—
tRW
tWW
tRAD
tWAD
tALS
tALH
tAHS
tAHH
tMS
—
RD pulse width
—
WR pulse width
tfW+3
tfW+3
2tfW+3
tfW+3
3tfW+3
tfW+3
—
RD pulse delay time
WR pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Memory data setup time
Memory data hold time
Data delay time
CL=50pF
ns
tMH
0
tfW–3
tALH+5
tfW+3
tDD
tALH–0
tfW–3
tDH
Data hold time
CLK
ALE
RD
tfW
tfW
tAW
tRAD
tRW
AD 0-AD7
A 8-A19
RAP 0-7
DIN 0-7
tALS
tALH
tMS
tMH
RAP 8-19
tAHS
tAHH
WR
tWAD
tWW
DOUT 0-7
AD 0-AD7
RAP 0-7
tALS
tALH
tDD
tDH
A 8-A19
RAP 8-19
tAHS
tAHH
15/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
• Serial Port Contorl
Master mode
(Ta=–30 to +70°C)
Parameter
Clock (OSC) pulse width
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Symbol
tfW
Conditions
Min.
25
Typ.
—
Max.
—
Units
—
tSCKC
8tfW
4tfW–5
3tfW–10
20
—
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
—
ns
CL=50pF
—
—
—
—
0
—
—
SCK
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
Valid
Valid
tSRMXS
tSRMXH
16/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
Slave mode
(Ta=–30 to +70°C)
Parameter
Clock (OSC) pulse width
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Symbol
tfW
Conditions
Min.
25
Typ.
—
Max.
—
Units
—
tSCKC
8tfW
2tfW–15
4tfW–10
20
—
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
—
ns
CL=50pF
—
—
—
—
0
—
—
SCK
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
Valid
Valid
tSRMXS
tSRMXH
AC timing mesurement point
V
DD
0.8VDD
0.2VDD
0.8VDD
0.2VDD
0V
17/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
AC Characteristics (2.7V £ V £ 5.5V)
DD
• External Program Memory Control
(Ta= –30 to +70°C)
Parameter
Clock (OSC) pulse width
ALE pulse width
Symbol
tfW
Conditions
Min
50
Max
—
Units
—
tAW
2tfW–4
2tfW–10
tfW–6
2tfW–6
tfW–6
4tfW–6
0
—
tPW
—
PSEN pulse width
tPAD
tALS
tALH
tAHS
tAPH
tIS
tfW+6
2tfW+6
tfW+6
4tfW+6
tfW+6
—
PSEN pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Instruction setup time
Instruction hold time
ns
CL=50pF
30
tIH
0
tfW–6
CLK
ALE
tfW
tfW
tAW
PSEN
tPAD
tPW
AD 0-AD7
A 8-A19
PC 0-7
tALS
INST 0-7
tALH
tIS
tIH
PC 8-19
tAHS
tAPH
18/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
• External Data Memory Control
(Ta= –30 to +70°C)
Parameter
Clock (OSC) pulse width
ALE pulse width
Symbol
tfW
tAW
Conditions
Min
50
Max
—
Units
—
2tfW–4
2tfW–10
2tfW–10
tfW–6
tfW–6
2tfW–6
tfW–6
3tfW–6
tfW–6
30
—
tRW
tWW
tRAD
tWAD
tALS
tALH
tAHS
tAHH
tMS
—
RD pulse width
—
WR pulse width
tfW+6
tfW+6
2tfW+6
tfW+6
3tfW+6
tfW+6
—
RD pulse delay time
WR pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Memory data setup time
Memory data hold time
Data delay time
CL=50pF
ns
tMH
0
tfW–6
tALH+10
tfW+6
tDD
tALH–0
tfW–6
tDH
Data hold time
CLK
ALE
RD
tfW
tfW
tAW
tRAD
tRW
AD 0-AD7
A 8-A19
RAP 0-7
DIN 0-7
tMS tMH
tALS
tALH
RAP 8-19
tAHS
tAHH
WR
tWAD
tWW
DOUT 0-7
AD 0-AD7
RAP 0-7
tALS
tALH
tDD
tDH
A 8-A19
RAP 8-19
tAHS
tAHH
19/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
• Serial Port Control
Master mode
(Ta=–30 to +70°C)
Parameter
Clock (OSC) pulse width
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Symbol
tfW
Conditions
Min.
50
Typ.
—
Max.
—
Units
—
tSCKC
8tfW
4tfW–10
3tfW–20
30
—
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
—
ns
CL=50pF
—
—
—
—
0
—
—
SCK
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
Valid
Valid
tSRMXS
tSRMXH
20/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
Slave mode
(Ta= –30 to +70°C)
Parameter
Clock (OSC) pulse width
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Symbol
tfW
Conditions
Min.
50
Typ.
—
Max.
—
Units
—
tSCKC
8tfW
—
—
tSTMXS
tSTMXH
tSRMXS
tSRMXH
2tfW–30
4tfW–20
30
—
—
ns
CL=50pF
—
—
—
—
10
—
—
SCK
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
Valid
Valid
tSRMXS
tSRMXH
AC timing mesurement point
V
DD
0.8VDD
0.2VDD
0.8VDD
0.2VDD
0V
21/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
A/D Converter Characteristics
(Ta=–30 to +70°C, VDD=VREF=5V 10ꢀ, AGND=GND=0V, fOSC=20MHz)
Item
Symbol
n
Conditions
Min
—
Typ
8
Max
—
Units
Refer to the recommended
circuit
Analog input source
impedance
Resolution
Bit
—
Linearity error
EL
—
—
—
—
—
2
ED
—
Differential linearity error
Zero scale error
Full scale error
1
LSB
RI£5kW
EZS
—
+2
tCONV=19.2msec
by ADTM set data
—
EFS
–2
tCONV
6.4
ms/CH
Conversion time
19.2
A/D Converter Characteristics
(Ta=–30 to +70°C, VDD=VREF=3V 10ꢀ, AGND=GND=0V, fOSC=10MHz)
Item
Symbol
n
Conditions
Min
—
Typ
8
Max
—
Units
Refer to the recommended
circuit
Analog input source
impedance
Resolution
Bit
—
Linearity error
EL
—
1
ED
—
Differential linearity error
Zero scale error
Full scale error
—
0.5
+1
LSB
RI£5kW
—
EZS
—
tCONV=38.4msec
—
EFS
—
–1
tCONV
—
ms/CH
Conversion time
38.4
—
ADTM=00b (384CLK selection)
Reference
Voltage
VDD
+5V
VREF
0.1
mF
47
mF
+
+
0.1
mF
47
mF
RI
–
+
AI0~
AI3
AGND
GND
0V
Analog Voltage
CI
0.1
mF
RI (analog input source impedance) £ 5kW
Cl = 0.1 mF
Recommended Circuit
22/24
¡ Semiconductor
MSM66585/586/587/P587/Q587
Definition of terms
• Resolution
8
Resolution is the minimum input analog value that can be resolved. With 8 bits, 2 =256 so
resolution can be to (V -AGND) ÷ 256.
REF
• Linearity error
Linearity error is the difference between actual conversion characteristics and ideal
conversion characteristics of an 8-bit A/D converter (so this does not include quantization
error).
Ideal conversion characteristics would be to divide the voltage between V
into 256 equal steps.
and AGND
REF
• Differential linearity error
Differential linearity error indicates slope of conversion characteristics. The change in
analog input voltage value that would change the digital output by one bit is ideally 1 LSB
= (V -AGND) ÷ 256, so differential linearity error is the difference between this ideal bit
REF
size and the actual bit size anywhere in the conversion range.
• Zero scale error
Zero scale error is the difference between actual conversion characteristics and ideal
conversion characteristics at the point where digital output switches from 00H to 01H.
• Full scale error
Full scale error is the difference between actual conversion characteristics and ideal
conversion characteristics at the point where digital output switches from FEH to FFH.
23/24
¡ Semiconductor
PACKAGE DIMENSIONS
TQFP100-P-1414-0.50-K
MSM66585/586/587/P587/Q587
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
24/24
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