74AC04MTC [ONSEMI]
六路逆变器;
| 型号： | 74AC04MTC |
| 厂家： | 
ONSEMI |
| 描述： | 六路逆变器 PC 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总11页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Hex Inverter
SOIC−14 NB
CASE 751A−03
14
14
74AC04, 74ACT04
1
General Description
SOIC14
CASE 751EF
The AC/ACT04 contains six inverters.
1
Features
• I Reduced by 50% On 74AC Only
CC
TSSOP−14 WB
CASE 948G
• Outputs Source/Sink 24 mA
• ACT04 has TTL−Compatible Inputs
• These are Pb−Free Devices
14
1
TSSOP−14 WB
CASE 948G−01
ABSOLUTE MAXIMUM RATINGS
14
Parameter
Supply Voltage
DC Input Diode Current
Symbol
Value
Unit
V
V
CC
IK
−0.5 to +7.0
1
I
mA
V = −0.5 V
−20
+20
I
MARKING DIAGRAM
V = V + 0.5 V
I
CC
14
DC Input Voltage
V
I
−0.5 to
CC
V
V
+ 0.5
AC(T)04
AWLYWW
DC Output Diode Current
I
mA
OK
V
O
V
O
= −0.5 V
−20
+20
= V + 0.5 V
1
CC
DC Output Voltage
V
−0.5 to
+ 0.5
V
O
AC04, ACT04 = Specific Device Code
V
CC
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
DC Output Source or Sink Current
I
O
50
50
mA
mA
DC V or Ground Current
I
or I
CC GND
CC
WW
= Work Week
per Output Pin
Storage Temperature
T
−65 to +150
°C
°C
STG
MARKING DIAGRAM
Junction Temperature
PDIP
T
J
140
14
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
AC(T)
04
ALYWG
G
1
AC04, ACT04 = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 2
of this data sheet.
© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
December, 2021 − Rev. 2
74ACT04/D
74AC04, 74ACT04
ORDERING INFORMATION
Order Number
74AC04SC
Package Number
Package Description
M14A
MTC14
M14A
14−Lead Small Outline Integrated Circuit (SOIC), JEDEC MS−012, 0.150” Narrow
14−Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO−153, 4.4 mm Wide
14−Lead Small Outline Integrated Circuit (SOIC), JEDEC MS−012, 0.150” Narrow
14−Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO−153, 4.4 mm Wide
74AC04MTC
74ACT04SC
74ACT04MTC
MTC14
NOTES: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. All packages are lead free per
JEDEC: J−STD−020B standard.
IEEE/IEC
Figure 2. Logic Symbol
Figure 1. Connection Diagram
PIN DESCRIPTION
Pin
Description
A
n
Inputs
O
Outputs
n
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage
V
AC
2.0
4.5
6.0
5.5
ACT
V
Input Voltage
0
0
V
V
V
I
CC
CC
V
O
Output Voltage
V
T
A
Operating Temperature
−40
+85
°C
DV / Dt
Minimum Input Edge Rate, AC Devices:
IN
125
125
mV/ns
V
from 30% to 70% of V ,V at 3.3 V, 4.5 V, 5.5 V
CC CC
DV / Dt
Minimum Input Edge Rate, ACT Devices:
from 0.8 V to 2.0 V, V at 4.5 V, 5.5 V
mV/ns
V
IN
CC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
2
74AC04, 74ACT04
DC ELECTRICAL CHARACTERISTICS FOR AC
T
= +255C
T
= −405C to +855C
A
A
Typ
1.5
Guaranteed Limits
Symbol
Parameter
V
CC
(V)
Conditions
Unit
V
Minimum HIGH Level
Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
V
= 0.1 V
CC
2.1
2.1
3.15
3.85
0.9
V
IH
OUT
or V − 0.1 V
2.25
2.75
1.5
3.15
3.85
0.9
V
Maximum LOW Level
Input Voltage
V
OUT
= 0.1 V
CC
V
V
IL
or V − 0.1 V
2.25
2.75
2.99
4.49
5.49
−
1.35
1.65
2.9
1.35
1.65
2.9
V
OH
Minimum HIGH Level
Output Voltage
I
= −50 mA
OUT
4.4
4.4
5.4
5.4
V
IN
= V or V
,
2.56
2.46
IL
IH
I
I
I
I
= −12 mA
OH
4.5
5.5
3.0
4.5
5.5
3.0
= −24 mA
−
3.86
4.86
0.1
3.76
4.76
0.1
OH
= −24 mA (Note 1)
−
OH
V
OL
Maximum LOW Level
Output Voltage
= 50 mA
0.002
0.001
0.001
−
V
OUT
0.1
0.1
0.1
0.1
V
IN
= V or V
,
0.36
0.44
IL
IH
I
I
I
= 12 mA
OL
4.5
5.5
5.5
= 24 mA
−
−
−
0.36
0.36
0.1
0.44
0.44
1.0
OL
OL
= 24 mA (Note 1)
I
IN
Maximum Input
Leakage Current
V = V , GND
I
mA
CC
(Note 3)
I
Minimum Dynamic
5.5
5.5
5.5
V
V
V
= 1.65 V Max.
= 3.85 V Min.
−
−
−
−
−
75
mA
mA
mA
OLD
OLD
Output Current (Note 2)
I
−75
20.0
OHD
OHD
I
Maximum Quiescent
Supply Current
= V or GND
2.0
CC
IN
CC
(Note 3)
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0 ms, one output loaded at a time.
3. I and I at 3.0 V are guaranteed to be less than or equal to the respective limit at 5.5 V V .
IN
CC
CC
www.onsemi.com
3
74AC04, 74ACT04
DC ELECTRICAL CHARACTERISTICS FOR ACT
T
= +255C
T
= −405C to +855C
A
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
−
Guaranteed Limits
Symbol
Parameter
V
CC
(V)
Conditions
Unit
V
Minimum HIGH Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
4.5
V
= 0.1 V
CC
2.0
2.0
2.0
0.8
0.8
4.4
5.4
3.76
V
IH
OUT
or V − 0.1 V
2.0
0.8
0.8
4.4
5.4
3.86
V
Maximum LOW Level
Input Voltage
V
OUT
= 0.1 V
CC
V
V
IL
or V − 0.1 V
V
OH
Minimum HIGH Level
Output Voltage
I
= −50 mA
OUT
V
IN
= V or V
IL
IH
I
I
I
= −24 mA
OH
5.5
4.5
5.5
4.5
= −24 mA (Note 4)
−
4.86
0.1
4.76
0.1
OH
V
OL
Maximum LOW Level
Output Voltage
= 50 mA
0.001
0.001
−
V
OUT
0.1
0.1
V
OL
= V or V
0.36
0.44
IN
IL
IH
I
= 24 mA
5.5
5.5
I
= 24 mA (Note 4)
−
−
0.36
0.1
0.44
1.0
OL
I
IN
Maximum Input
Leakage Current
V = V , GND
mA
I
CC
I
I
Maximum I /Input
5.5
5.5
5.5
5.5
V = V − 2.1 V
0.6
−
−
−
1.5
75
mA
mA
mA
mA
CCT
CC
I
CC
Minimum Dynamic
Output Current (Note 5)
V
V
V
= 1.65 V Max.
OLD
OLD
OHD
I
= 3.85 V Min.
−
−
−75
40.0
OHD
I
Maximum Quiescent
Supply Current
= V or GND
−
4.0
CC
IN
CC
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0 ms, one output loaded at a time.
www.onsemi.com
4
74AC04, 74ACT04
AC ELECTRICAL CHARACTERISTICS FOR AC
T
A
= +25°C, C = 50 pF
T = −40°C to +85°C, C = 50 pF
A L
L
Symbol
Parameter
V
CC
(V) (Note 6)
Min
1.5
1.5
1.5
1.5
Typ
4.5
4.0
4.5
3.5
Max
9.0
7.0
8.5
6.5
Min
1.0
1.0
1.0
1.0
Max
10.0
7.5
Unit
t
Propagation Delay
3.3
5.0
3.3
5.0
ns
PLH
t
Propagation Delay
9.5
ns
PHL
7.0
6. Voltage range 3.3 is 3.3 V + 0.3 V. Voltage range 5.0 is 5.0 V + 0.5 V.
AC ELECTRICAL CHARACTERISTICS FOR ACT
T
A
= +25°C, C = 50 pF
T = −40°C to +85°C, C = 50 pF
A L
L
Symbol
Parameter
Propagation Delay
Propagation Delay
V
CC
(V) (Note 7)
Min
1.0
1.0
Typ
6.0
5.5
Max
8.5
Min
1.0
1.0
Max
9.0
Unit
ns
t
t
5.0
5.0
PLH
PLH
8.0
8.5
ns
7. Voltage range 5.0 is 5.0 V + 0.5 V.
CAPACITANCE
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Conditions
Typ
Unit
C
V
V
= OPEN
4.5
pF
pF
IN
CC
V
CC
= 5.0 V
30.0
CC
FACT is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or
other countries.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC14
CASE 751EF
ISSUE O
DATE 30 SEP 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13739G
SOIC14
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
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