74ACT175 [ONSEMI]

QUAD D FLIP-FLOP WITH MASTER RESET; QUAD D触发器具有硕士RESET
74ACT175
型号: 74ACT175
厂家: ONSEMI    ONSEMI
描述:

QUAD D FLIP-FLOP WITH MASTER RESET
QUAD D触发器具有硕士RESET

触发器
文件: 总6页 (文件大小:182K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
QUAD D FLIP-FLOP  
WITH MASTER RESET  
The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for  
general flip-flop requirements where clock and clear inputs are common. The  
information on the D inputs is transferred to storage during the LOW-to-HIGH clock  
transition. The device has a Master Reset to simultaneously clear all flip-flops, when  
MR is low.  
The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual  
D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common  
to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s  
output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master  
Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock  
or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and  
Master Reset are common to all storage elements.  
N SUFFIX  
CASE 648-08  
PLASTIC  
Outputs Source/Sink 24 mA  
• ′ACT175 Has TTL Compatible Inputs  
Pinout: 16-Lead Packages (Top View)  
V
Q
Q
D
D
Q
Q
2
CP  
9
CC  
3
3
3
2
2
D SUFFIX  
CASE 751B-05  
PLASTIC  
16  
15  
14  
13  
12  
11  
10  
PIN NAMES  
D
CP  
MR  
Q
Q
– D  
Data Inputs  
0
3
Clock Pulse Input  
Master Reset Input  
Outputs  
– Q  
– Q  
0
0
3
3
Outputs  
1
2
3
4
5
6
7
8
MR  
Q
Q
D
D
Q
Q
1
GND  
0
0
0
1
1
LOGIC SYMBOL  
TRUTH TABLE  
Inputs  
Outputs  
D
D
Q
D
D
0
1
2
1
3
1
MR  
CP  
D
Qn  
Qn  
CP  
L
H
H
H
X
X
H
L
L
H
L
H
L
H
MR  
Q
Q
Q
Q
Q
Q
Q
3
0
0
2
2
3
L
X
Qn  
Qn  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
= LOW-to-HIGH Transition of Clock  
FACT DATA  
5-1  
MC74AC175 MC74ACT175  
LOGIC DIAGRAM  
MR  
CP  
D
D
D
D
0
3
2
1
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
CP  
CP  
CP  
CP  
CD  
CD  
CD  
CD  
Q
Q
Q
Q
Q
Q
Q
Q
0
3
3
2
2
1
1
0
Please note that this diagram is provided only for the understanding of logic operations and should not be  
used to estimate propagation delays.  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
Unit  
V
V
V
DC Supply Voltage (Referenced to GND)  
–0.5 to +7.0  
CC  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
–0.5 to V  
+ 0.5  
V
in  
CC  
V
out  
–0.5 to V  
+ 0.5  
V
CC  
I
I
I
± 20  
mA  
mA  
mA  
°C  
in  
DC Output Sink/Source Current, per Pin  
± 50  
± 50  
out  
CC  
DC V  
or GND Current per Output Pin  
Storage Temperature  
CC  
T
stg  
–65 to +150  
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended  
Operating Conditions.  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
2.0  
4.5  
0
Typ  
5.0  
5.0  
Min  
6.0  
5.5  
Unit  
V
AC  
V
Supply Voltage  
CC  
ACT  
V , V  
in out  
DC Input Voltage, Output Voltage (Ref. to GND)  
V
CC  
V
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
@ 3.0 V  
@ 4.5 V  
@ 5.5 V  
@ 4.5 V  
@ 5.5 V  
150  
40  
Input Rise and Fall Time (Note 1)  
AC Devices except Schmitt Inputs  
ns/V  
t , t  
r f  
25  
10  
Input Rise and Fall Time (Note 2)  
ACT Devices except Schmitt Inputs  
t , t  
r f  
ns/V  
8.0  
T
Junction Temperature (PDIP)  
Operating Ambient Temperature Range  
Output Current — HIGH  
140  
85  
°C  
°C  
J
T
A
–40  
25  
I
I
–24  
24  
mA  
mA  
OH  
Output Current — LOW  
OL  
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.  
in  
CC  
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.  
in  
FACT DATA  
5-2  
MC74AC175 MC74ACT175  
DC CHARACTERISTICS  
Symbol  
74AC  
= +25°C  
74AC  
T
A
=
V
(V)  
CC  
Parameter  
Unit  
Conditions  
T
A
–40°C to +85°C  
Typ  
Guaranteed Limits  
V
V
V
3.0  
4.5  
5.5  
1.5  
2.25  
2.75  
2.1  
3.15  
3.85  
2.1  
3.15  
3.85  
V
= 0.1 V  
– 0.1 V  
Minimum High Level  
Input Voltage  
IH  
OUT  
V
V
V
or V  
CC  
= 0.1 V  
OUT  
3.0  
4.5  
5.5  
1.5  
2.25  
2.75  
0.9  
1.35  
1.65  
0.9  
1.35  
1.65  
V
Maximum Low Level  
Input Voltage  
IL  
or V  
– 0.1 V  
CC  
3.0  
4.5  
5.5  
2.99  
4.49  
5.49  
2.9  
4.4  
5.4  
2.9  
4.4  
5.4  
I
= – 50 µA  
Minimum High Level  
Output Voltage  
OH  
OUT  
*V = V or V  
IN IL IH  
3.0  
4.5  
5.5  
2.56  
3.86  
4.86  
2.46  
3.76  
4.76  
– 12 mA  
– 24 mA  
– 24 mA  
V
V
I
OH  
V
OL  
3.0  
4.5  
5.5  
0.002  
0.001  
0.001  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
I = 50 µA  
OUT  
Maximum Low Level  
Output Voltage  
*V = V or V  
IN IL  
IH  
3.0  
4.5  
5.5  
0.36  
0.36  
0.36  
0.44  
0.44  
0.44  
12 mA  
V
I
24 mA  
24 mA  
OH  
I
IN  
Maximum Input  
Leakage Current  
V = V , GND  
I
CC  
5.5  
±0.1  
±1.0  
µA  
I
I
I
5.5  
5.5  
75  
mA  
mA  
V
V
V
= 1.65 V Max  
†Minimum Dynamic  
Output Current  
OLD  
OHD  
CC  
OLD  
OHD  
IN  
–75  
= 3.85 V Min  
Maximum Quiescent  
Supply Current  
= V  
or GND  
CC  
5.5  
8.0  
80  
µA  
* All outputs loaded; thresholds on input associated with output under test.  
Maximum test duration 2.0 ms, one output loaded at a time.  
Note: I and I  
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V .  
IN CC  
CC  
AC CHARACTERISTICS  
Symbol  
74AC  
74AC  
T
= –40°C  
A
T
C
= +25°C  
V
(V)  
*
Fig.  
No.  
A
CC  
Parameter  
to +85°C  
= 50 pF  
Unit  
= 50 pF  
L
C
L
Min  
Typ  
Max  
Min  
Max  
3.3  
5.0  
149  
187  
139  
187  
Maximum Clock  
Frequency  
f
t
t
t
t
MHz  
ns  
3-3  
3-6  
3-6  
3-6  
3-6  
max  
PLH  
PHL  
PLH  
PHL  
3.3  
5.0  
2.0  
1.5  
12.0  
9.0  
2.0  
1.0  
13.5  
9.5  
Propagation Delay  
CP to Q or Q  
n
n
3.3  
5.0  
2.5  
1.5  
13.0  
9.5  
2.0  
1.5  
14.5  
10.5  
Propagation Delay  
CP to Q or Q  
ns  
n
n
3.3  
5.0  
3.0  
2.0  
12.5  
9.0  
2.5  
1.5  
13.5  
10.0  
Propagation Delay  
ns  
MR to Q  
n
3.3  
5.0  
3.0  
2.0  
11.0  
8.5  
2.5  
1.5  
12.5  
9.0  
Propagation Delay  
ns  
MR to Q  
n
FACT DATA  
5-3  
MC74AC175 MC74ACT175  
AC OPERATING REQUIREMENTS  
74AC  
74AC  
T
= –40°C  
A
T
C
= +25°C  
= 50 pF  
V
(V)  
*
Fig.  
No.  
A
L
CC  
Symbol  
Parameter  
to +85°C  
= 50 pF  
Unit  
C
L
Typ  
Guaranteed Minimum  
Set-up Time, HIGH or LOW  
to CP  
3.3  
5.0  
4.5  
3.0  
4.5  
3.0  
t
t
t
t
t
ns  
ns  
ns  
ns  
ns  
3-9  
3-9  
3-6  
3-6  
3-6  
s
D
n
Hold Time, HIGH or LOW  
to CP  
3.3  
5.0  
1.0  
1.0  
1.0  
1.0  
h
D
n
MR Pulse Width Low  
3.3  
5.0  
4.5  
3.5  
4.5  
3.5  
w
w
CP Pulse Width  
3.3  
5.0  
4.5  
3.5  
5.0  
3.5  
Recovery TIme  
MR to CP  
3.3  
5.0  
0
0
0
0
rec  
* Voltage Range 3.3 V is 3.3 V ±0.3 V.  
Voltage Range 5.0 V is 5.0 V ±0.5 V.  
DC CHARACTERISTICS  
74ACT  
= +25°C  
74ACT  
T
A
=
V
(V)  
CC  
Symbol  
Parameter  
Unit  
Conditions  
T
A
–40°C to +85°C  
Typ  
Guaranteed Limits  
V
V
V
4.5  
5.5  
1.5  
1.5  
2.0  
2.0  
2.0  
2.0  
V
= 0.1 V  
– 0.1 V  
Minimum High Level  
Input Voltage  
IH  
OUT  
V
V
V
or V  
CC  
= 0.1 V  
OUT  
4.5  
5.5  
1.5  
1.5  
0.8  
0.8  
0.8  
0.8  
V
Maximum Low Level  
Input Voltage  
IL  
or V  
– 0.1 V  
CC  
4.5  
5.5  
4.49  
5.49  
4.4  
5.4  
4.4  
5.4  
I
= – 50 µA  
Minimum High Level  
Output Voltage  
OH  
OUT  
*V = V or V  
IN IL  
IH  
4.5  
5.5  
3.86  
4.86  
3.76  
4.76  
V
V
– 24 mA  
– 24 mA  
I
OH  
V
OL  
4.5  
5.5  
0.001  
0.001  
0.1  
0.1  
0.1  
0.1  
I = 50 µA  
OUT  
Maximum Low Level  
Output Voltage  
*V = V or V  
IN IL  
IH  
4.5  
5.5  
0.36  
0.36  
0.44  
0.44  
V
24 mA  
I
OH  
24 mA  
I
IN  
Maximum Input  
Leakage Current  
V = V , GND  
I
CC  
5.5  
±0.1  
±1.0  
µA  
I  
Additional Max. I /Input  
CC  
5.5  
5.5  
5.5  
0.6  
1.5  
75  
mA  
mA  
mA  
V = V  
I
– 2.1 V  
CCT  
CC  
I
V
OLD  
= 1.65 V Max  
= 3.85 V Min  
†Minimum Dynamic  
Output Current  
OLD  
I
–75  
V
OHD  
CC  
OHD  
IN  
I
Maximum Quiescent  
Supply Current  
V
= V  
or GND  
CC  
5.5  
8.0  
80  
µA  
* All outputs loaded; thresholds on input associated with output under test.  
Maximum test duration 2.0 ms, one output loaded at a time.  
FACT DATA  
5-4  
MC74AC175 MC74ACT175  
AC CHARACTERISTICS  
Symbol  
74ACT  
74ACT  
= –40°C  
T
A
T
C
= +25°C  
= 50 pF  
V
(V)  
*
Fig.  
No.  
A
CC  
Parameter  
to +85°C  
Unit  
L
C
= 50 pF  
L
Min  
Typ  
Max  
Min  
Max  
Maximum Clock  
Frequency  
f
t
t
t
5.0  
5.0  
5.0  
5.0  
175  
145  
MHz  
ns  
3-3  
3-6  
3-6  
3-6  
max  
PLH  
PHL  
PHL  
Propagation Delay  
2.0  
2.0  
2.0  
10.0  
11.0  
9.5  
1.5  
1.5  
1.5  
11.0  
12.0  
10.5  
CP to Q  
n
Propagation Delay  
CP to Q  
ns  
n
Propagation Delay  
MR to Q or Q  
ns  
n
n
* Voltage Range 5.0 V is 5.0 V ±0.5 V.  
AC OPERATING REQUIREMENTS  
74ACT  
74ACT  
= –40°C  
T
A
T
C
= +25°C  
= 50 pF  
V
CC  
(V)  
*
Fig.  
No.  
A
Symbol  
Parameter  
to +85°C  
= 50 pF  
Unit  
L
C
L
Typ  
Guaranteed Minimum  
t
s
(H)  
(L)  
Set-up Time, HIGH or LOW  
to CP  
2.0  
2.5  
2.0  
2.5  
5.0  
ns  
3-9  
D
n
Hold Time, HIGH or LOW  
to CP  
t
t
t
t
5.0  
5.0  
5.0  
5.0  
1.0  
3.0  
3.0  
0
1.0  
4.0  
3.5  
0
ns  
ns  
ns  
ns  
3-9  
3-6  
3-6  
3-6  
h
D
n
MR Pulse Width, LOW  
w
CP Pulse Width,  
HIGH or LOW  
w
Recovery TIme  
MR to CP  
rec  
* Voltage Range 5.0 V is 5.0 V ±0.5 V.  
CAPACITANCE  
Symbol  
Value  
Typ  
Parameter  
Unit  
Test Conditions  
C
C
Input Capacitance  
Power Dissipation Capacitance  
4.5  
pF  
pF  
V
V
= 5.0 V  
= 5.0 V  
IN  
CC  
45.0  
PD  
CC  
FACT DATA  
5-5  
MC74AC175 MC74ACT175  
OUTLINE DIMENSIONS  
N SUFFIX  
PLASTIC DIP PACKAGE  
NOTES:  
CASE 648–08  
ISSUE R  
–A–  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEADS WHEN  
FORMED PARALLEL.  
16  
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.  
5. ROUNDED CORNERS OPTIONAL.  
INCHES  
MILLIMETERS  
DIM  
A
B
C
D
F
MIN  
MAX  
0.770  
0.270  
0.175  
0.021  
0.70  
MIN  
18.80  
6.35  
3.69  
0.39  
1.02  
MAX  
19.55  
6.85  
4.44  
0.53  
1.77  
F
0.740  
0.250  
0.145  
0.015  
0.040  
C
L
SEATING  
PLANE  
–T–  
G
H
J
K
L
0.100 BSC  
0.050 BSC  
2.54 BSC  
1.27 BSC  
K
M
0.008  
0.015  
0.130  
0.305  
10  
0.21  
0.38  
3.30  
7.74  
10  
H
J
0.110  
0.295  
0
2.80  
7.50  
0
G
D 16 PL  
M
S
0.020  
0.040  
0.51  
1.01  
M
M
0.25 (0.010)  
T
A
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751B–05  
ISSUE J  
–A–  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
16  
1
9
8
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.127 (0.005) TOTAL  
IN EXCESS OF THE D DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
–B–  
P 8 PL  
M
S
0.25 (0.010)  
B
G
MILLIMETERS  
INCHES  
DIM  
A
B
C
D
MIN  
9.80  
3.80  
1.35  
0.35  
0.40  
MAX  
10.00  
4.00  
1.75  
0.49  
1.25  
MIN  
MAX  
0.393  
0.157  
0.068  
0.019  
0.049  
F
0.386  
0.150  
0.054  
0.014  
0.016  
R X 45  
K
C
F
G
J
K
M
P
R
1.27 BSC  
0.050 BSC  
–T–  
SEATING  
PLANE  
0.19  
0.10  
0
0.25  
0.25  
7
0.008  
0.004  
0
0.009  
0.009  
7
J
M
D
16 PL  
5.80  
0.25  
6.20  
0.50  
0.229  
0.010  
0.244  
0.019  
M
S
S
0.25 (0.010)  
T
B
A
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding  
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and  
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different  
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does  
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in  
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of  
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such  
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless  
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.  
Motorola and  
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.  
How to reach us:  
USA/EUROPE: Motorola Literature Distribution;  
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,  
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447  
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315  
MFAX: RMFAX0@email.sps.mot.com –TOUCHTONE (602) 244–6609  
INTERNET: http://Design–NET.com  
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,  
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298  
MC74AC175/D  

相关型号:

74ACT175DC

D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, CDIP16, CERAMIC, DIP-16
ROCHESTER

74ACT175FCQR

ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16
TI

74ACT175FCXR

D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, CDFP16, CERAMIC, FP-16
FAIRCHILD

74ACT175LC

D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD

74ACT175MTC

Quad D-Type Flip-Flop
FAIRCHILD

74ACT175MTCX

Quad D-Type Flip-Flop
FAIRCHILD

74ACT175PC

Quad D-Type Flip-Flop
FAIRCHILD

74ACT175PC

ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, 0.300 INCH, PLASTIC, DIP-16
TI

74ACT175PCQR

ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-16
TI

74ACT175SC

Quad D-Type Flip-Flop
FAIRCHILD

74ACT175SC

ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 0.150 INCH, PLASTIC, SOIC-16
TI

74ACT175SCQR

ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOIC-16
TI