概述
数据手册
替代型号74LCX04MTCX 概述
带有 5 V 容差输入的低电压六通道逆变器
74LCX04MTCX 数据手册
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December 2013
74LCX04
Low Voltage Hex Inverter with 5V Tolerant Inputs
Features
General Description
■ 5V tolerant inputs
The LCX04 contains six inverters. The inputs tolerate
voltages up to 7V allowing the interface of 5V systems to
3V systems.
■ 2.3V–3.6V V specifications provided
CC
■ 5.2ns t max. (V = 3.3V), 10µA I max.
PD
CC
CC
The 74LCX04 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
■ Power down high impedance inputs and outputs
24mA output drive (V = 3.0V)
■
CC
■ Implements proprietary noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
– Human body model > 2000V
– Machine model > 200V
■ Leadless DQFN package
Ordering Information
Package
Order Number
74LCX04M
Number
Package Description
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX04SJ
M14D
(1)
74LCX04BQX
MLP14A
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX04MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX04 Rev. 1.6.1
www.fairchildsemi.com
Connection Diagrams
Logic Symbol
Pin Assignments for SOIC, SOP, and TSSOP
IEEE/IEC
Pad Assignments for DQFN
(Bottom View)
(Top View)
Pin Description
Pin Names
Description
A , B
Inputs
n
n
O
Outputs
No Connect
n
DAP
Note: DAP (Die Attach Pad)
©1995 Fairchild Semiconductor Corporation
74LCX04 Rev. 1.6.1
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
Supply Voltage
–0.5V to +7.0V
–0.5V to +7.0V
CC
V
DC Input Voltage
I
(2)
V
DC Output Voltage, Output in HIGH or LOW State
–0.5V to V + 0.5V
O
IK
CC
I
DC Input Diode Current, V < GND
–50mA
I
I
DC Output Diode Current
OK
V
< GND
–50mA
+50mA
O
V
> V
CC
O
I
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50mA
O
I
100mA
CC
I
100mA
GND
T
–65°C to +150°C
STG
Note:
2. I Absolute Maximum Rating must be observed.
O
(3)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Units
V
Supply Voltage
Operating
CC
2.0
1.5
0
3.6
3.6
5.5
V
Data Retention
Input Voltage
V
V
V
I
V
Output Voltage, HIGH or LOW State
Output Current
0
V
CC
O
I
/ I
OH OL
V
V
V
= 3.0V–3.6V
= 2.7V–3.0V
= 2.3V–2.7V
24
12
8
mA
CC
CC
CC
T
Free-Air Operating Temperature
Input Edge Rate, V = 0.8V–2.0V, V = 3.0V
–40
0
85
10
°C
A
∆t / ∆V
ns/V
IN
CC
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
©1995 Fairchild Semiconductor Corporation
74LCX04 Rev. 1.6.1
www.fairchildsemi.com
3
DC Electrical Characteristics
T = –40°C to +85°C
A
Symbol
Parameter
V
(V)
Conditions
Min.
1.7
Max.
Units
CC
V
HIGH Level Input Voltage
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
V
IH
2.0
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
V
V
IL
V
I
I
I
I
I
I
I
I
I
I
= –100µA
= –8mA
= –12mA
= –18mA
= –24mA
= 100µA
= 8mA
V
– 0.2
CC
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
1.8
2.2
2.4
2.2
2.7
3.0
V
LOW Level Output Voltage
2.3–3.6
2.3
0.2
0.6
0.4
0.4
0.55
5.0
10
V
OL
2.7
= 12mA
= 16mA
= 24mA
3.0
I
Input Leakage Current
2.3–3.6
0
0 ≤ V ≤ 5.5V
µA
µA
µA
I
I
I
Power-Off Leakage Current
Quiescent Supply Current
V or V = 5.5V
I O
OFF
I
2.3–3.6
V = V or GND
10
CC
I
CC
3.6V ≤ V ≤ 5.5V
10
I
∆I
Increase in I per Input
2.3–3.6
V
= V – 0.6V
500
µA
CC
CC
IH
CC
AC Electrical Characteristics
T = –40°C to +85°C, R = 500Ω
A
L
V
= 3.3V 0.3V,
V
= 2.7V,
V = 2.5V 0.2V,
CC
CC
CC
C = 50pF
C = 50pF
C = 30pF
L
L
L
Symbol
Parameter
Propagation Delay
Output to Output Skew
Min.
Max.
5.2
Min.
Max.
Min.
Max.
Units
ns
t
, t
1.5
1.5
6.0
1.5
6.2
PHL PLH
(4)
t
, t
1.0
ns
OSHL OSLH
Note:
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t ) or LOW-to-HIGH (t ).
OSHL
OSLH
©1995 Fairchild Semiconductor Corporation
74LCX04 Rev. 1.6.1
www.fairchildsemi.com
4
Dynamic Switching Characteristics
T = 25°C
A
Symbol
Parameter
V
(V)
Conditions
Typical
0.8
Unit
CC
V
Quiet Output Dynamic Peak V
3.3
C = 50pF, V = 3.3V, V = 0V
V
OLP
OL
L
IH
IL
2.5
3.3
2.5
C = 30pF, V = 2.5V, V = 0V
0.6
L
IH
IL
V
Quiet Output Dynamic Valley V
C = 50 pF, V = 3.3V, V = 0V
–0.8
–0.6
V
OLV
OL
L
IH
IL
C = 30 pF, V = 2.5V, V = 0V
L
IH
IL
Capacitance
Symbol
Parameter
Conditions
Typical
Units
pF
C
Input Capacitance
V
= Open, V = 0V or V
CC
7
8
IN
CC
CC
CC
I
C
Output Capacitance
V
V
= 3.3V, V = 0V or V
CC
pF
OUT
I
C
Power Dissipation Capacitance
= 3.3V, V = 0V or V , f = 10MHz
25
pF
PD
I
CC
©1995 Fairchild Semiconductor Corporation
74LCX04 Rev. 1.6.1
www.fairchildsemi.com
5
AC Loading and Waveforms (Generic for LCX Family)
Test
Switch
t
t
, t
Open
PLH PHL
, t
6V at V = 3.3 0.3V
PZL PLZ
CC
V
x 2 at V = 2.5 0.2V
CC
CC
t
, t
GND
PZH PHZ
Figure 1. AC Test Circuit (C includes probe and jig capacitance)
L
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and t Waveforms
rec
3-STATE Output Low Enable and
Disable Times for Logic
t
and t
fall
rise
V
CC
Symbol
3.3V 0.3V
1.5V
2.7V
1.5V
1.5V
2.5V 0.2V
V
V
V
/ 2
/ 2
mi
CC
CC
V
1.5V
mo
V
V
+ 0.3V
– 0.3V
V
+ 0.3V
V
+ 0.15V
– 0.15V
x
y
OL
OL
OL
V
V
V
– 0.3V
V
OH
OH
OH
Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns)
r
f
©1995 Fairchild Semiconductor Corporation
74LCX04 Rev. 1.6.1
www.fairchildsemi.com
6
Schematic Diagram (Generic for LCX Family)
©1995 Fairchild Semiconductor Corporation
74LCX04 Rev. 1.6.1
www.fairchildsemi.com
7
Tape and Reel Specification
Tape Format for DQFN
Package Designator
Tape Section
Number of Cavities
125 (Typ.)
Cavity Status
Empty
Cover Tape Status
Sealed
BQX
Leader (Start End)
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (Typ.)
Empty
Sealed
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
12mm
13.0 (330.0)
0.059 (1.50)
0.512 (13.00) 0.795 (20.20) 2.165 (55.00)
0.488 (12.4)
0.724 (18.4)
©1995 Fairchild Semiconductor Corporation
74LCX04 Rev. 1.6.1
www.fairchildsemi.com
8
0.65
A
ꢀꢁꢂꢂꢂꢁꢃꢂ
0.43TYP
14
8
B
6.4
ꢄꢁꢄꢂꢂꢁꢃꢂ
6.10
3.2
1.65
0.2 C B A
ALL LEAD TIPS
1
7
PIN#1 IDENT
TOP VIEW
0.45
RECOMMENDED LAND PATTERN
SEE DETAIL A
1.2 MAX
+0.15
-0.10
0.90
0.20
0.09
ꢂꢁꢃꢂꢂꢁꢂꢀ
0.30
0.19
ALL LEAD TIPS
C
0.1 C
0.13
A B
C
0.65
ꢃꢅꢁꢂꢂꢆ723ꢆꢇꢆ%27720
FRONT VIEW
0.09 MIN
NOTES:
GAGE PLANE
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
0.25
0.09 MIN
ꢂꢉꢆꢊ
ꢂꢁꢈꢂꢁꢃ
1.00
SEATING PLANE
DETAIL A
E. LANDPATTERN STANDARD: SOP65P640X110-14M.
F. DRAWING FILE NAME: MKT-MTC14rev7.
8.75
8.50
A
0.65
7.62
14
8
14
8
B
4.00
3.80
5.60
6.00
1.70
1
7
PIN #1
IDENT.
1
7
1.27
0.51
0.35
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
TOP VIEW
1.75 MAX
A
0.25
0.19
C
0.10 C
NOTES:
1.50
1.25
0.25
0.10
SIDE VIEW
FRONT VIEW
A. CONFORMS TO JEDEC MS-012,
VARIATION AB, ISSUE C
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS
0.50
0.25
x 45
R0.10
GAGE
PLANE
D. LAND PATTERN STANDARD:
SOIC127P600X145-14M
R0.10
E. CONFORMS TO ASME Y14.5M, 2009
D. DRAWING FILENAME: MKT-M14Arev14
0.36
8°
0°
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE 16 : 1
4.00 MAX
2.20 MAX
1.40 MAX
B
3.00
0.05 C
A
2X
1.00
MAX
1.70
MAX
2.50
0.50 TYP
3.50
MAX
(0.90)
0.05 C
TOP VIEW
2X
PIN #1 QUADRANT
0.50 TYP
0.24 TYP
ꢀꢁꢈꢀꢀꢁꢀꢃ
RECOMMENDED LAND PATTERN
0.10 C
ꢀꢁꢂꢀꢀꢁꢀꢃ
0.08 C
ꢀꢁꢀꢂꢃꢀꢁꢀꢂꢃ
C
SIDE VIEW
SEATING
PLANE
ꢄꢁꢀꢀꢀꢁꢀꢃ
ꢅꢁꢆꢃꢀꢁꢀꢃ
ꢀꢁꢄꢇꢀꢀꢁꢀꢃ
(14X)
A. CONFORMS TO JEDEC REGISTRATION
MO-241, VARIATION AA
PIN #1 IDENT
0.50
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
ꢅꢁꢅꢃꢀꢁꢀꢃ
ꢂꢁꢃꢀꢀꢁꢀꢃ
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP14Arev2.
ꢀꢁꢂꢃꢀꢁꢀꢃ
(14X)
0.50
0.10
0.05
C A B
C
2.00
BOTTOM VIEW
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regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
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74LCX04MTCX 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| 74LCX04MTCX_NL | FAIRCHILD | Low Voltage Hex Inverter with 5V Tolerant Inputs | 功能相似 |
|
| 74LCX04MTC | ONSEMI | 带有 5 V 容差输入的低电压六通道逆变器 | 功能相似 |
|
74LCX04MTCX 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 74LCX04MTCX_NL | FAIRCHILD | Low Voltage Hex Inverter with 5V Tolerant Inputs | 获取价格 |
|
| 74LCX04MTC_08 | FAIRCHILD | Low Voltage Hex Inverter with 5V Tolerant Inputs | 获取价格 |
|
| 74LCX04MTR | STMICROELECTRONICS | LOW VOLTAGE CMOS HEX INVERTER WITH 5V TOLERANT INPUTS | 获取价格 |
|
| 74LCX04MX | FAIRCHILD | Low Voltage Hex Inverter with 5V Tolerant Inputs | 获取价格 |
|
| 74LCX04MX | ONSEMI | 带有 5 V 容差输入的低电压六通道逆变器 | 获取价格 |
|
| 74LCX04MX_NL | FAIRCHILD | Low Voltage Hex Inverter with 5V Tolerant Inputs | 获取价格 |
|
| 74LCX04M_08 | FAIRCHILD | Low Voltage Hex Inverter with 5V Tolerant Inputs | 获取价格 |
|
| 74LCX04SJ | FAIRCHILD | Low Voltage Hex Inverter with 5V Tolerant Inputs | 获取价格 |
|
| 74LCX04SJX | FAIRCHILD | Low Voltage Hex Inverter with 5V Tolerant Inputs | 获取价格 |
|
| 74LCX04SJX_NL | FAIRCHILD | Inverter, LVC/LCX/Z Series, 6-Func, 1-Input, CMOS, PDSO14, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14 | 获取价格 |
|
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