74LCX162374MTDX [ONSEMI]
低压16位D类触发器,带5V可耐受电压输入和输出,及26 Ohm串联电阻;型号: | 74LCX162374MTDX |
厂家: | ONSEMI |
描述: | 低压16位D类触发器,带5V可耐受电压输入和输出,及26 Ohm串联电阻 驱动 光电二极管 逻辑集成电路 触发器 |
文件: | 总12页 (文件大小:255K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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February 2001
Revised May 2005
74LCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
and 26: Series Resistors
General Description
Features
■ 5V tolerant inputs and outputs
The LCX162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
■ 2.3V–3.6V VCC specifications provided
■ Equivalent 26 series resistor on outputs
■ 7.0 ns tPD max (VCC 3.3V), 20 A ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
The LCX162374 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
■
12 mA output drive (VCC 3.0V)
environment. The 26 series resistor in the output helps
reduce output overshoot and undershoot.
■ Implements proprietary noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The LCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Human body model 2000V
Machine model 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
through a pull-up resistor: the minimum value or the
CC
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
Package Number
Package Description
74LCX162374GX
(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74LCX162374MEA
(Note 3)
MS48A
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX162374MTD
(Note 3)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500442
www.fairchildsemi.com
Connection Diagrams
Pin Descriptions
Pin Assignment for SSOP and TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
CPn
Clock Pulse Input
Inputs
I0–I15
O0–O15
NC
Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
O0
O2
NC
O1
OE1
NC
CP1
NC
NC
I1
I0
I2
O4
O3
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
I3
I4
O6
O5
I5
I6
O8
O7
I7
I8
O10
O12
O14
O9
I9
I10
I12
I14
G
H
O11
O13
I11
I13
J
O15
NC
OE2
CP2
NC
I15
Truth Tables
Pin Assignment for FBGA
Inputs
Outputs
CP1
OE1
I0–I7
O0–O7
L
L
H
L
H
L
L
L
X
X
O0
Z
X
H
Inputs
OE2
Outputs
O8–O15
CP2
I8–I15
L
L
H
L
H
L
(Top Thru View)
L
L
X
X
O0
Z
X
H
H
L
X
Z
O
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Previous O before HIGH-to-LOW of CP
0
0
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2
Functional Description
The LCX162374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte func-
tioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OEn) LOW, the con-
tents of the flip-flops are available at the outputs. When
OEn is HIGH, the outputs go to the high impedance state.
Operation of the OEn input does not affect the state of the
flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 4)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
3-STATE
V
0.5 to VCC 0.5 Output in HIGH or LOW State (Note 5)
IIK
DC Input Diode Current
DC Output Diode Current
50
50
VI GND
VO GND
VO VCC
mA
mA
IOK
50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50
mA
mA
mA
C
ICC
100
IGND
TSTG
100
65 to 150
Recommended Operating Conditions (Note 6)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
5.5
12
Units
VCC
Supply Voltage
Operating
V
V
V
Data Retention
VI
Input Voltage
VO
Output Voltage
HIGH or LOW State
3-STATE
0
0
IOH/IOL
Output Current
VCC 3.0V 3.6V
VCC 2.7V 3.0V
VCC 2.3V 2.7V
8
mA
4
TA
Free-Air Operating Temperature
40
0
85
C
t/ V
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V
10
ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 5: I Absolute Maximum Rating must be observed.
O
Note 6: Floating or unused control inputs must be HIGH or LOW.
DC Electrical Characteristics
V
T
40 C to 85 C
Min Max
CC
A
Symbol
Parameter
Conditions
Units
(V)
2.3 2.7
2.7 3.6
2.3 2.7
2.7 3.6
2.3 3.6
2.3
V
V
V
HIGH Level Input Voltage
1.7
2.0
IH
V
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
IL
0.8
I
100
A
V
CC
0.2
OH
OH
I
4 mA
4 mA
6 mA
8 mA
1.8
2.2
2.4
2.0
2.0
OH
I
2.7
OH
V
V
I
3.0
OH
I
2.7
OH
I
12 mA
100
3.0
OH
V
LOW Level Output Voltage
I
A
2.3 3.6
2.3
0.2
0.6
0.4
0.55
0.6
0.8
5.0
OL
OL
I
4 mA
4 mA
6 mA
8 mA
OL
I
2.7
OL
I
3.0
OL
I
2.7
OL
I
12 mA
3.0
OL
I
I
Input Leakage Current
0
0
V
V
V
5.5V
5.5V
2.3 3.6
A
A
I
I
3-STATE Output Leakage
OZ
O
2.3 3.6
5.0
V
or V
IL
I
IH
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4
DC Electrical Characteristics (Continued)
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Conditions
Units
(V)
Min
Max
10
I
I
Power-Off Leakage Current
Quiescent Supply Current
V or V
5.5V
or GND
0
A
A
A
OFF
CC
I
O
V
V
2.3 3.6
2.3 3.6
2.3 3.6
20
I
CC
3.6V V , V
5.5V (Note 7)
V 0.6V
CC
20
I
O
I
Increase in I per Input
V
500
CC
CC
IH
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
40 to 85 C, R
500
A
L
V
3.3V 0.3V
50 pF
V
2.7V
V
CC
2.5V 0.2V
CC
CC
Symbol
Parameter
Units
C
C
50 pF
C
L
30 pF
Max
L
L
Min
170
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
Max
Min
Max
Min
f
t
t
t
t
t
t
t
t
t
t
t
Maximum Clock Frequency
Propagation Delay
CP to O
MHz
ns
MAX
7.0
7.0
6.9
6.9
6.0
6.0
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
7.3
7.3
7.1
7.1
6.2
6.2
1.5
1.5
1.5
1.5
1.5
1.5
3.0
2.0
3.5
8.4
8.4
9.0
9.0
7.2
7.2
PHL
PLH
PZL
PZH
PLZ
PHZ
S
n
Output Enable time
ns
ns
Output Disable Time
Setup Time
ns
ns
ns
Hold Time
H
Pulse Width
W
Output to Output Skew (Note 8)
1.0
1.0
OSHL
OSLH
ns
Note 8: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
). Parameter guaranteed by design.
OSLH
OSHL
Dynamic Switching Characteristics
V
T
25 C
CC
A
Symbol
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.35
V
V
Quiet Output Dynamic Peak V
C
C
C
C
50 pF, V
30 pF, V
50 pF, V
30 pF, V
3.3V, V
2.5V, V
3.3V, V
2.5V, V
0V
0V
0V
0V
OLP
OL
L
L
L
L
IH
IH
IH
IH
IL
IL
IL
IL
V
V
0.25
Quiet Output Dynamic Valley V
0.35
OLV
OL
0.25
Capacitance
Symbol
Parameter
Conditions
Typical
Units
pF
C
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
V
V
Open, V 0V or V
CC
7
8
IN
CC
CC
CC
I
C
C
3.3V, V 0V or V
CC
pF
OUT
PD
I
3.3V, V 0V or V , f 10 MHz
20
pF
I
CC
5
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AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
PLH, tPHL
PZL, tPLZ
Switch
Open
t
t
6V at VCC 3.3 0.3V, and 2.7V
VCC x 2 at VCC 2.5 0.2V
tPZH, tPHZ
GND
3-STATE Output High Enable and
Disable Times for Logic
Waveform for Inverting and Non-Inverting Functions
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
VCC
Symbol
3.3V 0.3V
1.5V
2.7V
1.5V
2.5V 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
VOL 0.3V
VOH 0.3V
VOL 0.3V
VOH 0.3V
VOL 0.15V
VOH 0.15V
Vy
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6
Schematic Diagram Generic for LCX Family
7
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Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
Preliminary
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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www.fairchildsemi.com
10
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
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literature is subject to all applicable copyright laws and is not for resale in any manner.
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