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February 1994

Revised May 2005

74LCX16374

Low Voltage 16-Bit D-Type Flip-Flop

with 5V Tolerant Inputs and Outputs

General Description

Features

■ 5V tolerant inputs and outputs

The LCX16374 contains sixteen non-inverting D-type

flip-flops with 3-STATE outputs and is intended for bus ori-

ented applications. The device is byte controlled. A buff-

ered clock (CP) and Output Enable (OE) are common to

each byte and can be shorted together for full 16-bit opera-

tion.

■ 2.3V–3.6V V_CCspecifications provided

■ 6.2 ns t_PDmax (V_CC3.3V), 20 A I_CCmax

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

The LCX16374 is designed for low voltage (2.5V or 3.3V)

■

24 mA output drive (V_CC3.0V)

V_CCapplications with capability of interfacing to a 5V signal

■ Uses proprietary noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

environment.

The LCX16374 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Human body model 2000V

Machine model 200V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to V

through a pull-up resistor: the minimum value or the

CC

resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Order Number Package Number

Package Description

74LCX16374G

(Note 2)(Note 3)

BGA54A

MS48A

MTD48

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LCX16374MEA

(Note 3)

74LCX16374MTD

(Note 3)

Note 2: Ordering code “G” indicates Trays.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

DS012003

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Connection Diagrams

Pin Descriptions

Pin Assignment for SSOP and TSSOP

Pin Names

Description

OE_n

Output Enable Input (Active LOW)

CP_n

Clock Pulse Input

Inputs

I₀–I₁₅

O₀–O₁₅

NC

Outputs

No Connect

FBGA Pin Assignments

1

2

3

4

5

6

A

B

C

D

E

F

O₀

O₂

NC

O₁

OE₁

NC

CP₁

NC

I₁

I₀

I₂

O₄

O₃

V_CC

GND

V_CC

NC

V_CC

GND

V_CC

NC

I₃

I₄

O₆

O₅

I₅

I₆

O₈

O₇

I₇

I₈

O₁₀

O₁₂

O₁₄

O₉

I₉

I₁₀

I₁₂

I₁₄

G

H

O₁₁

O₁₃

I₁₁

I₁₃

J

O₁₅

NC

OE₂

CP₂

NC

I₁₅

Truth Tables

Pin Assignment for FBGA

Inputs

Outputs

CP₁

OE₁

I₀–I₇

O₀–O₇

L

H

L

H

L

X

O₀

Z

X

H

Inputs

OE₂

Outputs

O₈–O₁₅

CP₂

I₈–I₁₅

L

H

L

H

L

(Top Thru View)

L

X

O₀

Z

X

H

L

X

Z

O

HIGH Voltage Level

LOW Voltage Level

Immaterial

High Impedance

Previous O before HIGH-to-LOW of CP

0

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2

Functional Description

The LCX16374 consists of sixteen edge-triggered flip-flops

with individual D-type inputs and 3-STATE true outputs.

The device is byte controlled with each byte functioning

identically, but independent of the other. The control pins

can be shorted together to obtain full 16-bit operation. Each

byte has a buffered clock and buffered Output Enable com-

mon to all flip-flops within that byte. The description which

follows applies to each byte. Each flip-flop will store the

state of their individual D inputs that meet the setup and

hold time requirements on the LOW-to-HIGH Clock (CP_n)

transition. With the Output Enable (OE_n) LOW, the con-

tents of the flip-flops are available at the outputs. When

OE_nis HIGH, the outputs go to the high impedance state.

Operation of the OE_ninput does not affect the state of the

flip-flops.

Logic Diagrams

Byte 1 (0:7)

Byte 2 (8:15)

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

3

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Absolute Maximum Ratings(Note 4)

Symbol

V_CC

Parameter

Supply Voltage

Value

Conditions

Units

0.5 to 7.0

V

V_I

DC Input Voltage

V_O

DC Output Voltage

3-STATE

V

0.5 to V_CC0.5 Output in HIGH or LOW State (Note 5)

I_IK

DC Input Diode Current

DC Output Diode Current

50

V_IGND

V_OGND

V_OV_CC

mA

I_OK

50

I_O

DC Output Source/Sink Current

DC Supply Current per Supply Pin

DC Ground Current per Ground Pin

Storage Temperature

50

mA

C

I_CC

100

I_GND

T_STG

100

65 to 150

Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-

mended Operating Conditions” table will define the conditions for actual device operation.

Note 5: I Absolute Maximum Rating must be observed.

O

Recommended Operating Conditions (Note 6)

Symbol

Parameter

Min

2.0

1.5

0

Max

3.6

5.5

V_CC

5.5

24

Units

V_CC

Supply Voltage

Operating

V

Data Retention

V_I

Input Voltage

V_O

Output Voltage

HIGH or LOW State

3-STATE

0

I

_OH/I_OL

Output Current

V_CC3.0V 3.6V

V_CC2.7V 3.0V

V_CC2.3V 2.7V

12

mA

8

T_A

t/ V

Free-Air Operating Temperature

40

0

85

C

Input Edge Rate, V_IN0.8V – 2.0V, V_CC3.0V

10

ns/V

Note 6: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

V

T

40 C to 85 C

Min Max

CC

A

Symbol

Parameter

Conditions

Units

(V)

2.3 2.7

2.7 3.6

2.3 2.7

2.7 3.6

2.3 3.6

2.3

V

HIGH Level Input Voltage

1.7

2.0

IH

V

LOW Level Input Voltage

HIGH Level Output Voltage

0.7

IL

0.8

I

100

A

V

CC

0.2

OH

I

8 mA

1.8

2.2

2.4

2.2

OH

I

12 mA

18 mA

24 mA

2.7

V

OH

I

3.0

OH

I

3.0

OH

V

LOW Level Output Voltage

I

100

8 mA

A

2.3 3.6

2.3

0.2

0.6

OL

I

OL

I

12 mA

16 mA

24 mA

2.7

0.4

0.55

5.0

OL

I

3.0

OL

I

3.0

OL

I

Input Leakage Current

0

V

5.5V

2.3 3.6

A

I

3-STATE Output Leakage

OZ

O

2.3 3.6

0

5.0

10

V

or V

IL

I

IH

I

Power-Off Leakage Current

V or V

O

5.5V

OFF

I

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4

DC Electrical Characteristics (Continued)

V

T

40 C to 85 C

CC

A

Symbol

Parameter

Conditions

V or GND

CC

Units

(V)

Min

Max

20

I

Quiescent Supply Current

V

2.3 3.6

CC

I

A

3.6V V , V

5.5V (Note 7)

V 0.6V

CC

20

I

O

I

Increase in I per Input

V

500

CC

IH

Note 7: Outputs disabled or 3-STATE only.

AC Electrical Characteristics

T

40 to 85 C, R

500

A

L

V

3.3V 0.3V

50 pF

V

2.7V

V

CC

2.5V 0.2V

CC

Symbol

Parameter

Units

C

50 pF

C

L

30 pF

Max

L

Min

170

1.5

2.5

1.5

3.0

Max

Min

Max

Min

f

t

Maximum Clock Frequency

Propagation Delay

CP to O

MHz

ns

MAX

6.2

6.1

6.0

1.5

2.5

1.5

3.0

6.5

6.3

6.2

1.5

3.0

2.0

3.5

7.4

7.9

7.2

PHL

PLH

PZL

PZH

PLZ

PHZ

S

n

Output Enable time

ns

Output Disable Time

Setup Time

ns

Hold Time

H

Pulse Width

W

Output to Output Skew (Note 8)

1.0

OSHL

OSLH

ns

Note 8: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

) or LOW-to-HIGH (t

). Parameter guaranteed by design.

OSLH

OSHL

Dynamic Switching Characteristics

V

T

25 C

CC

A

Symbol

Parameter

Conditions

Units

(V)

3.3

2.5

3.3

2.5

Typical

0.8

V

Quiet Output Dynamic Peak V

C

50 pF, V

30 pF, V

50 pF, V

30 pF, V

3.3V, V

2.5V, V

3.3V, V

2.5V, V

0V

OLP

OL

L

IH

IL

V

0.6

Quiet Output Dynamic Valley V

0.8

OLV

OL

0.6

Capacitance

Symbol

Parameter

Conditions

Typical

Units

pF

C

Input Capacitance

Output Capacitance

V

Open, V 0V or V

CC

7

8

IN

CC

I

3.3V, V 0V or V

CC

pF

OUT

PD

I

Power Dissipation Capacitance

3.3V, V 0V or V , f 10 MHz

20

pF

I

CC

5

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AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (C_Lincludes probe and jig capacitance)

Test

_PLH, t_PHL

_PZL, t_PLZ

Switch

Open

t

6V at V_CC3.3 0.3V, and 2.7V

V_CCx 2 at V_CC2.5 0.2V

t_PZH, t_PHZ

GND

3-STATE Output High Enable and

Disable Times for Logic

Waveform for Inverting and Non-Inverting Functions

Setup Time, Hold Time and Recovery Time for Logic

Propagation Delay. Pulse Width and t_recWaveforms

t_riseand t_fall

3-STATE Output Low Enable and

Disable Times for Logic

FIGURE 2. Waveforms

(Input Characteristics; f = 1MHz, t_r= t_f= 3ns)

V_CC

Symbol

3.3V 0.3V

1.5V

2.7V

1.5V

2.5V 0.2V

V_CC/2

V_mi

V_mo

V_x

1.5V

V_CC/2

V_OL0.3V

V_OH0.3V

V_OL0.3V

V_OH0.3V

V_OL0.15V

V_OH0.15V

V_y

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6

Schematic Diagram Generic for LCX Family

7

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Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA54A

www.fairchildsemi.com

8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS48A

9

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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10

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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

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1


型号：	74LCX16374MTDX
厂家：	ONSEMI
描述：	带 5V 耐压输入和输出的低压 16 位 D 型触发器驱动光电二极管逻辑集成电路触发器
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