74LCX16646MTDX [ONSEMI]
带5V容差输入和输出的低电压16位收发器/寄存器;
| 型号： | 74LCX16646MTDX |
| 厂家： | 
ONSEMI |
| 描述： | 带5V容差输入和输出的低电压16位收发器/寄存器 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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February 1994
Revised August 2002
74LCX16646
Low Voltage 16-Bit Transceiver/Register
with 5V Tolerant Inputs and Outputs
General Description
Features
■ 5V tolerant inputs and outputs
The LCX16646 contains sixteen non-inverting bidirectional
registered bus transceivers with 3-STATE outputs, provid-
ing multiplexed transmission of data directly from the input
bus or from the internal storage registers. Each byte has
separate control inputs which can be shorted together for
full 16-bit operation.The DIR inputs determine the direction
of data flow through the device. The CPAB and CPBA
inputs load data into the registers on the LOW-to-HIGH
transition (see Functional Description).
■ 2.3V–3.6V VCC specifications provided
■ 5.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ ±24 mA Output Drive (VCC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
The LCX16646 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
■ ESD performance:
Human Body Model > 2000V
Machine Model > 200V
environment.
The LCX16646 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16646MEA
74LCX16646MTD
MS56A
MTD56
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
An
Bn
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Output Enable Inputs
OEn
CPABn, CPBAn Clock Pulse Inputs
SABn, SBAn
DIRn
Select Inputs
Direction Control Inputs
© 2002 Fairchild Semiconductor Corporation
DS012004
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Connection Diagram
Truth Table
(Note 2)
Inputs
Data I/O
A0–7 B0–7
Output Operation Mode
OE1
DIR1 CPAB1 CPBA1 SAB1
SBA1
H
H
H
L
L
L
L
L
L
L
L
X
X
X
H
H
H
H
L
H or L H or L
X
X
X
L
X
X
X
X
X
X
X
L
Isolation
X
Input
Input Clock An Data into A Register
Clock Bn Data Into B Register
X
X
X
X
X
X
X
An to Bn — Real Time (Transparent Mode)
L
Input Output Clock An Data to A Register
A Register to Bn (Stored Mode)
H or L
H
H
X
X
X
X
Clock An Data into A Register and Output to Bn
Bn to An — Real Time (Transparent Mode)
Output Input Clock Bn Data into B Register
X
X
X
X
L
L
L
H or L
H
H
B Register to An (Stored Mode)
L
Clock Bn into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition.
Note 2: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and
#2 control pins.
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2
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both. The select (SABn, SBAn) controls can multiplex
The direction control (DIRn) determines which bus will
receive data when OEn is LOW. In the isolation mode (OEn
HIGH), A data may be stored in one register and/or B data
may be stored in the other register. When an output func-
tion is disabled, the input function is still enabled and may
be used to store and transmit data. Only one of the two
busses, A or B, may be driven at a time.
stored and real-time. The examples shown below demon-
strate the four fundamental bus-management functions
that can be performed.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
OE DIR CPAB CPBA SAB SBA
OE DIR CPAB CPBA SAB SBA
L
L
X
X
X
L
L
H
X
X
L
X
Transfer Storage
Data to A or B
Storage
OE DIR CPAB CPBA SAB SBA
OE DIR CPAB CPBA SAB SBA
L
L
L
X
H or L
X
X
H
H
X
L
L
H
X
X
X
X
L
X
X
X
X
L
H
H or L
X
X
H
H
X
X
X
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4
Absolute Maximum Ratings(Note 3)
Symbol
VCC
VI
Parameter
Supply Voltage
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to VCC + 0.5
−50
Conditions
Units
V
V
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
Output in HIGH or LOW State (Note 4)
IIK
DC Input Diode Current
DC Output Diode Current
VI < GND
mA
mA
IOK
−50
V
V
O < GND
O > VCC
+50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 5)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
5.5
±24
±12
±8
Units
VCC
Supply Voltage
Operating
Data Retention
V
V
V
VI
Input Voltage
VO
Output Voltage
HIGH or LOW State
3-STATE
0
0
IOH/IOL
Output Current
V
V
V
CC = 3.0V − 3.6V
CC = 2.7V − 3.0V
CC = 2.3V − 2.7V
mA
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Unused inputs and I/Os must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
VIH
Parameter
Conditions
Units
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
Min
1.7
2.0
Max
HIGH Level Input Voltage
V
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
VOH
I
I
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −8 mA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OL = 100 µA
OL = 8 mA
VCC − 0.2
1.8
2.7
2.2
V
V
3.0
2.4
3.0
2.2
VOL
LOW Level Output Voltage
2.3 − 3.6
2.3
0.2
0.6
OL = 12 mA
OL = 16 mA
OL = 24 mA
2.7
0.4
3.0
0.4
3.0
0.55
±5.0
II
Input Leakage Current
3-STATE I/O Leakage
0 ≤ VI ≤ 5.5V
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
2.3 − 3.6
µA
µA
µA
IOZ
2.3 − 3.6
±5.0
IOFF
Power-Off Leakage Current
VI or VO = 5.5V
0
10
5
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DC Electrical Characteristics (Continued)
VCC
TA = −40°C to +85°C
Symbol
ICC
Parameter
Conditions
Units
(V)
Min
Max
20
Quiescent Supply Current
VI = VCC or GND
3.6V ≤ VI, VO ≤ 5.5V (Note 6)
VIH = VCC −0.6V
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
µA
µA
±20
500
∆ICC
Increase in ICC per Input
Note 6: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500Ω
CC = 3.3V ± 0.3V CC = 2.7V CC = 2.5V ± 0.2V
L = 50 pF L = 50 pF L = 30 pF
V
V
V
Symbol
Parameter
Units
C
C
C
Min
170
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
Max
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
ns
ns
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPLZ
tPHZ
tS
Propagation Delay
Bus to Bus
5.2
5.2
6.0
6.0
6.0
6.0
7.5
7.5
6.5
6.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
6.0
6.0
7.0
7.0
7.0
7.0
8.5
8.5
7.5
7.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3.0
2.0
3.5
6.2
6.2
7.2
7.2
7.2
7.2
9.8
9.8
7.8
7.8
Propagation Delay
Clock to Bus
ns
ns
ns
ns
Propagation Delay
Select to Bus
Output Enable Time
Output Disable Time
Setup Time
ns
ns
ns
tH
Hold Time
tW
Pulse Width
tOSHL
tOSLH
Output to Output Skew (Note 7)
1.0
1.0
ns
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.8
VOLP
Quiet Output Dynamic Peak VOL
C
C
C
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
V
V
0.6
VOLV
Quiet Output Dynamic Valley VOL
−0.8
−0.6
Capacitance
Symbol
Parameter
Conditions
Typical
Units
CIN
Input Capacitance
V
V
V
CC = Open, VI = 0V or VCC
7
8
pF
pF
pF
CI/O
CPD
Input/Output Capacitance
CC = 3.3V, VI = 0V or VCC
Power Dissipation Capacitance
CC = 3.3V, VI = 0V or VCC, F = 10 MHz
20
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6
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
PZL, tPLZ
Switch
Open
t
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tR = tF = 3ns)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
V
OL + 0.3V
V
OL + 0.3V
VOL + 0.15V
Vy
V
OH − 0.3V
V
OH − 0.3V
VOH − 0.15V
7
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Schematic Diagram Generic for LCX Family
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8
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS56A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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