74LCX244WM [ONSEMI]
带 5V 耐压输入和输出的低压缓冲器/线路驱动器;
| 型号： | 74LCX244WM |
| 厂家： | 
ONSEMI |
| 描述： | 带 5V 耐压输入和输出的低压缓冲器/线路驱动器 PC 驱动 光电二极管 逻辑集成电路 驱动器 |
| 文件： | 总16页 (文件大小：896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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December 2013
74LCX244
Low Voltage Buffer/Line Driver with 5V Tolerant
Inputs and Outputs
Features
General Description
■ 5V tolerant inputs and outputs
The LCX244 contains eight non-inverting buffers with
3-STATE outputs. The device may be employed as a
memory address driver, clock driver and bus-oriented
transmitter/receiver. The LCX244 is designed for low
voltage (2.5V or 3.3V) VCC applications with capability of
interfacing to a 5V signal environment.
■ 2.3V to 3.6V VCC specifications provided
■ 6.5ns tPD max. (VCC = 3.3V), 10µA ICC max.
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal(1)
■ ±24mA output drive (VCC = 3.0V)
■ Implements proprietary noise/EMI reduction circuitry
■ Latch-up performance exceeds 500mA
■ ESD performance:
The LCX244 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
– Human body model > 2000V
– Machine model > 200V
■ Leadless DQFN package
Note:
1. To ensure the high-impedance state during power up
or down, OE should be tied to VCC through a pull-up
resistor: the minimum value or the resistor is
determined by the current-sourcing capability of the
driver.
Ordering Information
Package
Order Number
Number
Package Description
74LCX244WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX244SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 4.5mm
74LCX244BQX(2)
MLP20B
MSA20
MTC20
74LCX244MSA
74LCX244MTC
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
Connection Diagram
Logic Diagram
Pin Assignments for SOIC, SOP, SSOP, and TSSOP
Pad Assignments for DQFN
Truth Tables
Inputs
Outputs
OE
L
I
(Pins 12, 14, 16, 18)
1
n
L
L
H
Z
L
H
X
H
Inputs
Outputs
OE
L
I
(Pins 3, 5, 7, 9)
2
n
L
L
H
Z
L
H
X
H
(Bottom View)
Description
(Top Through View)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Pin Description
Z = High Impedance
Pin Names
OE1, OE2
I0–I7
3-STATE Output Enable Inputs
Inputs
O0–O7
DAP
Outputs
No Connect
Note: DAP (Die Attach Pad)
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Rating
–0.5V to +7.0V
Supply Voltage
VI
DC Input Voltage
DC Output Voltage
Output in 3-STATE
Output in HIGH or LOW State(3)
DC Input Diode Current, VI < GND
DC Output Diode Current
VO < GND
–0.5V to +7.0V
VO
–0.5V to +7.0V
–0.5V to VCC + 0.5V
–50mA
IIK
IOK
–50mA
+50mA
VO > VCC
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50mA
ICC
±100mA
IGND
TSTG
Note:
±100mA
–65°C to +150°C
3. IO Absolute Maximum Rating must be observed.
(4)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Units
VCC
Supply Voltage
Operating
2.0
1.5
0
3.6
3.6
5.5
V
V
V
Data Retention
Input Voltage
VI
VO
Output Voltage
3-STATE
0
0
5.5
HIGH or LOW State
Output Current
VCC = 3.0V–3.6V
VCC = 2.7V–3.0V
VCC = 2.3V–2.7V
VCC
IOH / IOL
±24
±12
±8
mA
TA
Free-Air Operating Temperature
–40
0
85
°C
Δt / ΔV
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
10
ns/V
Note:
4. Unused inputs must be held HIGH or LOW. They may not float.
©1994 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX244 Rev. 1.12.2
3
DC Electrical Characteristics
T = –40°C to +85°C
A
Symbol
Parameter
V
(V)
Conditions
Min.
1.7
Max.
Units
CC
VIH
HIGH Level Input Voltage
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
V
2.0
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
V
V
VOH
IOH = –100µA
VCC – 0.2
1.8
IOH = –8mA
IOH = –12mA
IOH = –18mA
IOH = –24mA
IOL = 100µA
IOL = 8mA
2.7
2.2
3.0
2.4
2.2
VOL
LOW Level Output Voltage
2.3–3.6
2.3
0.2
0.6
V
2.7
IOL = 12mA
IOL = 16mA
IOL = 24mA
0 ≤ VI ≤ 5.5V
0.4
3.0
0.4
0.55
±5.0
±5.0
II
Input Leakage Current
2.3–3.6
2.3–3.6
µA
µA
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 5.5V,
VI = VIH or VIL
IOFF
ICC
Power-Off Leakage Current
Quiescent Supply Current
0
VI or VO = 5.5V
10
10
µA
µA
2.3–3.6
VI = VCC or GND
3.6V ≤ VI, VO ≤ 5.5V(5)
VIH = VCC – 0.6V
±10
500
ΔICC
Increase in ICC per Input
2.3–3.6
µA
Note:
5. Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T = –40°C to +85°C, R = 500Ω
A
L
V
= 3.3V ± 0.3V,
V
= 2.7V,
V = 2.5V ± 0.2V,
CC
CC
CC
C = 50pF
C = 50pF
C = 30pF
L
L
L
Symbol
Parameter
Min.
Max.
Min. Max.
Min.
Max.
Units
tPHL, tPLH
Propagation Delay,
Data to Output
1.5
6.5
1.5
7.5
1.5
7.8
ns
tPZL, tPZH
tPLZ, tPHZ
Output Enable Time
1.5
1.5
8.0
7.0
1.0
1.5
1.5
9.0
8.0
1.5
1.5
10.0
8.4
ns
ns
ns
Output Disable Time
tOSHL, tOSLH Output to Output Skew(6)
Note:
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-
LOW (tOSHL) or LOW-to-HIGH (tOSLH).
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
4
Dynamic Switching Characteristics
T = 25°C
A
Symbol
Parameter
V
(V)
Conditions
Typical
0.8
Unit
CC
VOLP
Quiet Output Dynamic Peak VOL
3.3
2.5
3.3
2.5
CL = 50pF, VIH = 3.3V, VIL = 0V
CL = 30pF, VIH = 2.5V, VIL = 0V
CL = 50pF, VIH = 3.3V, VIL = 0V
CL = 30pF, VIH = 2.5V, VIL = 0V
V
0.6
VOLV
Quiet Output Dynamic Valley VOL
–0.8
–0.6
V
Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
Typical
7.0
Units
pF
CIN
COUT
CPD
VCC = Open, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
8.0
pF
VCC = 3.3V, VI = 0V or VCC, f = 10MHz
25.0
pF
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
5
AC Loading and Waveforms (Generic for LCX Family)
Test
Switch
tPLH, tPHL Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH, tPHZ GND
Figure 1. AC Test Circuit (CL includes probe and jig capacitance)
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
VCC
Symbol
Vmi
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC / 2
Vmo
Vx
1.5V
1.5V
VCC / 2
VOL + 0.3V
VOH – 0.3V
VOL + 0.3V
VOH – 0.3V
VOL + 0.15V
VOH – 0.15V
Vy
Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
6
Schematic Diagram (Generic for LCX Family)
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
7
Tape and Reel Specification
Tape Format for DQFN
Package Designator
Tape Section
Number of Cavities Cavity Status Cover Tape Status
BQX
Leader (Start End)
Carrier
125 (typ.)
3000
Empty
Filled
Sealed
Sealed
Sealed
Trailer (Hub End)
75 (typ.)
Empty
Tape Dimension inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
12mm
13.0 (330.0)
0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4)
0.724 (18.4)
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
8
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
10
0.65
0.51
0.35
1.27
PIN ONE
INDICATOR
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
GAGE PLANE
0.25
8°
0°
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
9
Physical Dimensions (Continued)
Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
10
Physical Dimensions (Continued)
Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
11
Physical Dimensions (Continued)
Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
12
Physical Dimensions (Continued)
Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
©1994 Fairchild Semiconductor Corporation
74LCX244 Rev. 1.12.2
www.fairchildsemi.com
13
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
Sync-Lock™
AccuPowerA
AX-CAP®*
F-PFSA
FRFET®
®
®*
Global Power ResourceSM
GreenBridgeA
Green FPSA
Green FPSA e-SeriesA
GmaxA
PowerTrench®
PowerXS™
Programmable Active DroopA
QFET®
BitSiCA
TinyBoost®
TinyBuck®
TinyCalcA
TinyLogic®
TINYOPTOA
TinyPowerA
TinyPWMA
TinyWireA
TranSiCA
Build it NowA
CorePLUSA
CorePOWERA
CROSSVOLTA
CTLA
QSA
GTOA
IntelliMAXA
Quiet SeriesA
RapidConfigureA
A
Current Transfer LogicA
DEUXPEED®
Dual Cool™
EcoSPARK®
EfficientMaxA
ISOPLANARA
Making Small Speakers Sound Louder
and Better™
Saving our world, 1mW/W/kW at a time™
SignalWiseA
SmartMaxA
MegaBuckA
TriFault DetectA
TRUECURRENT®*
ꢀSerDesA
ESBCA
MICROCOUPLERA
MicroFETA
SMART STARTA
Solutions for Your SuccessA
SPM®
®
MicroPakA
Fairchild®
MicroPak2A
Fairchild Semiconductor®
FACT Quiet SeriesA
FACT®
UHC®
Ultra FRFETA
UniFETA
VCXA
VisualMaxA
VoltagePlusA
XS™
STEALTHA
MillerDriveA
SuperFET®
MotionMaxA
mWSaver®
SuperSOTA-3
FAST®
SuperSOTA-6
OptoHiTA
FastvCoreA
FETBenchA
FPSA
OPTOLOGIC®
OPTOPLANAR®
SuperSOTA-8
SupreMOS®
SyncFETA
* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE
SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN,
WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain
life, and (c) whose failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its
safety or effectiveness.
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Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com,
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Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Preliminary
No Identification Needed
Obsolete
First Production
Full Production
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Rev. I66
© Fairchild Semiconductor Corporation
www.fairchildsemi.com
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