74LCX32BQX [ONSEMI]
低压四路2输入"或"门（5V容许输入电压）;
| 型号： | 74LCX32BQX |
| 厂家： | 
ONSEMI |
| 描述： | 低压四路2输入"或"门（5V容许输入电压） 栅 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：776K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage Quad 2-Input
OR Gate with 5 V Tolerant
Inputs
74LCX32
The LCX32 contains four 2−input OR gates. The inputs tolerate
voltages up to 7 V allowing the interface of 5 V systems to 3 V
systems.
The 74LCX32 is fabricated with advanced CMOS technology to
achieve high speed operation while maintaining CMOS low power
dissipation.
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MARKING DIAGRAM
ON ZXYKK
LCX32
Features
• 5 V Tolerant Inputs
QFN14 3.0x2.5, 0.5P
CASE 510CB
• 2.3 V – 3.6 V V Specifications Provided
CC
• 5.5 ns t Max. (V = 3.3 V), 10 mA I Max.
PD
CC
CC
14
• Power Down High Impedance Inputs and Outputs
ON ZXYKK
LCX32
•
24 mA Output Drive (V = 3.0 V)
CC
• Implements Proprietary Noise/EMI Reduction Circuitry
• Latch−up Performance Exceeds JEDEC 78 Conditions
1
SOIC14
CASE 751EF
• ESD performance:
♦ Human Body Model >2000 V
♦ Machine model >150 V
14
• Available on SOIC, TSSOP WB and Leadless QFN Packages
• These are Pb−Free Devices
ON
ZXYKK
LCX32
1
TSSOP−14 WB
CASE 948G
LCX32 = Specific Device Code
Z
XY
KK
= Assembly Plant Code
= Date Code
= Lot Run Traceability Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 1995
1
Publication Order Number:
April, 2020 − Rev. 2
74LCX32/D
74LCX32
CONNECTION DIAGRAMS
LOGIC SYMBOL
Figure 3. IEEE/IEC
Figure 1. Pin Assignments for SOIC and TSSOP
PIN DESCRIPTION
Pin Names
Description
A , B
Inputs
n
n
O
Outputs
n
DAP
No Connect
1. DAP (Die Attach Pad)
(Top View)
(Bottom View)
Figure 2. Pad Assignments for DQFN
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
V
Supply Voltage
–0.5 V to +7.0 V
–0.5 V to +7.0 V
CC
V
DC Input Voltage
I
V
O
DC Output Voltage, Output in HIGH or LOW State (Note 2)
–0.5 V to V + 0.5 V
CC
I
IK
DC Input Diode Current, V < GND
–50 mA
I
I
DC Output Diode Current
OK
V
< GND
–50 mA
+50 mA
O
V
O
> V
CC
I
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50 mA
O
I
100 mA
CC
I
100 mA
GND
T
–65°C to +150°C
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. I Absolute Maximum Rating must be observed.
O
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2
74LCX32
RECOMMENDED OPERATING CONDITIONS (Note 3)
Symbol Parameter
Min
Max
Unit
V
Supply Voltage
Operating
CC
2.0
1.5
0
3.6
3.6
V
Data Retention
Input Voltage
V
5.5
V
V
I
V
Output Voltage, HIGH or LOW State
Output Current
0
VCC
O
I
/ I
OH OL
V
CC
V
CC
V
CC
= 3.0 V – 3.6 V
= 2.7 V – 3.0 V
= 2.3 V – 2.7 V
−
−
24
12
8
mA
−
T
Free−Air Operating Temperature
Input Edge Rate, V = 0.8 V – 2.0 V, V = 3.0 V
–40
0
85
10
°C
A
Dt / DV
ns/V
IN
CC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. Unused inputs must be held HIGH or LOW. They may not float.
DC ELECTRICAL CHARACTERISTICS
−40°C to 85°C
Symbol
Parameter
Min
1.7
2.0
−
Max
−
Unit
V
(V)
Conditions
CC
V
IH
HIGH Level Input Voltage
2.3 – 2.7
2.7 – 3.6
2.3 – 2.7
2.7 – 3.6
2.3 – 3.6
2.3
V
−
V
IL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
−
V
V
−
V
OH
V
– 0.2
I
I
I
I
I
I
I
I
I
I
= –100 mA
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
CC
= –8 mA
= –12 mA
= –18 mA
= –24 mA
= 100 mA
= 8 mA
1.8
2.2
2.4
2.2
−
−
2.7
−
3.0
−
−
V
OL
LOW Level Output Voltage
2.3 – 3.6
2.3
0.2
0.6
0.4
0.4
0.55
5.0
10
10
10
500
V
−
2.7
= 12 mA
= 16 mA
= 24 mA
−
3.0
−
−
I
I
Input Leakage Current
2.3 – 3.6
0
0 ≤ V ≤ 5.5 V
−
mA
mA
mA
I
I
Power−Off Leakage Current
Quiescent Supply Current
V or V = 5.5 V
−
OFF
I
O
I
2.3 – 3.6
V = V or GND
−
CC
I
CC
3.6 V ≤ V ≤ 5.5 V
−
I
DI
CC
Increase in I per Input
2.3 – 3.6
V
= V – 0.6 V
−
mA
CC
IH
CC
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3
74LCX32
AC ELECTRICAL CHARACTERISTICS
T
A
= –40ꢀ C to +85ꢀ C, RL = 500 W
V
CC
= 3.3 V + 0.3 V,
V
CC
= 2.7 V,
V
CC
= 2.5 V + 0.2 V,
C = 50 pF
L
C = 50 pF
L
C = 30 pF
L
Min
Max
5.5
Min
Max
6.2
−
Min
Max
6.6
−
Symbol
, t
Parameter
Propagation Delay
Output to Output Skew (Note 4)
Unit
1.5
1.5
1.5
ns
t
PHL PLH
t
, t
−
1.0
−
−
ns
OSHL OSLH
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
) or LOW−to−HIGH (t
).
OSHL
OSLH
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= 25°C
Symbol
Parameter
Typical
0.8
Unit
V
(V)
Conditions
C = 50 pF, V = 3.3 V, V = 0 V
CC
V
OLP
Quiet Output Dynamic Peak V
3.3
V
OL
L
IH
IL
2.5
3.3
2.5
C = 30 pF, V = 2.5 V, V = 0 V
0.6
L
IH
IL
V
OLV
Quiet Output Dynamic Valley V
C = 50 pF, V = 3.3 V, V = 0 V
–0.8
–0.6
V
OL
L
IH
IL
C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
CAPACITANCE
Symbol
Parameter
Conditions
Typical
C
Input Capacitance
Output Capacitance
V
= Open, V = 0 V or V
7
8
pF
pF
pF
IN
CC
CC
CC
I
CC
CC
C
V
V
= 3.3 V, V = 0 V or V
I
OUT
C
Power Dissipation Capacitance
= 3. 3 V, V = 0 V or V , f = 10 MHz
25
PD
I
CC
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4
74LCX32
AC LOADING AND WAVEFORMS (GENERIC FOR LCX FAMILY)
Test
Switch
t
, t
Open
6 V at V = 3.3 0.3 V
PLH PHL
t
, t
PZL PLZ
CC
V
CC
x 2 at V = 2.5 0.2 V
CC
t
, t
GND
PZH PHZ
Figure 4. AC Test Circuit (CL Includes Probe and Jig Capacitance)
Waveform for Inverting and Non−Inverting Functions
3−STATE Output Low Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3−STATE Output High Enable and Disable Times for Logic
t and t
rise fall
V
CC
3.3 V ꢁ 0.3 V
2.7 V
2.5 V ꢁ 0.2 V
Symbol
V
1.5 V
1.5 V
1.5 V
1.5 V
/ 2
/ 2
mi
CC
CC
V
mo
V
V
V
+ 0.3 V
– 0.3 V
V
V
+ 0.3 V
V
+ 0.15 V
– 0.15 V
x
y
OL
OL
OL
V
– 0.3 V
V
OH
OH
OH
Figure 5. Waveforms (Input Characteristics; f = 1 MHz, tr = tf = 3 ns)
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5
74LCX32
SCHEMATIC DIAGRAM (GENERIC FOR LCX FAMILY)
Figure 6. Schematic Diagram (Generic for LCX Family)
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6
74LCX32
TAPE AND REEL SPECIFICATION
Tape Format for DQFN
TAPE FORMAT FOR DQFN
Package Designator
BQX
Tape Section
Number of Cavities
125 (Typ.)
3000
Cavity Status
Cover Tape Status
Sealed
Leader (Start End)
Carrier
Empty
Filled
Sealed
Trailer (Hub End)
75 (Typ.)
Empty
Sealed
Tape Dimensions (Inches (Millimeters))
Figure 7. Tape Dimensions (Inches (Millimeters))
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7
74LCX32
Reel Dimensions (Inches (Millimeters))
Figure 8.
Tape Size
A
B
C
D
N
W1
W2
12 mm
13.0 (330.0)
0.059 (1.50)
0.512 (13.00)
0.795 (20.20)
2.165 (55.00)
0.488 (12.4)
0.724 (18.4)
ORDERING INFORMATION
†
Ordering Number
Package Number
Package Description
Shipping
74LCX32M
SOIC14
14−Lead Small Outline Integrated Circuit (SOIC),
JEDEC MS−012, 0.150” Narrow
1100 Units / Tube
3000 Units / Tape & Reel
2350 Units / Tube
74LCX32BQX
(Note 5)
QFN14
14−Terminal Depopulated Quad Very−Thin Flat Pack
No Leads (DQFN), JEDEC MO−241, 2.5 x 3.0 mm
TSSOP−14 WB
TSSOP−14 WB
14−Lead Thin Shrink Small Outline Package (TSSOP),
JEDEC MO−153, 4.4 mm Wide
74LCX32MTC
14−Lead Thin Shrink Small Outline Package (TSSOP),
JEDEC MO−153, 4.4 mm Wide
2500 Units / Tape & Reel
74LCX32MTCX
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
5. DQFN package available in Tape and Reel only.
6. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
7. All packages are lead free per JEDEC: J−STD−020B standard.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN14 3.0x2.5, 0.5P
CASE 510CB
ISSUE O
DATE 31 AUG 2016
4.00 MAX
2.20 MAX
1.40 MAX
B
3.00
0.05 C
A
2X
1.00
MAX
1.70
MAX
3.50
MAX
2.50
2X
0.50 TYP
(0.90)
0.05 C
TOP VIEW
PIN #1 QUADRANT
0.80 0.05
0.50 TYP
0.24 TYP
RECOMMENDED LAND PATTERN
0.10
C
0.20 0.05
C
0.08
0.025 0.025
C
SIDE VIEW
SEATING
PLANE
3.00 0.05
1.65 0.05
0.370 0.05
(14X)
A. CONFORMS TO JEDEC REGISTRATION
MO−241, VARIATION AA
PIN #1 IDENT
0.50
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
1.15 0.05
2.50 0.05
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
0.25 0.05
(14X)
0.50
0.10
0.05
C A B
C
2.00
BOTTOM VIEW
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13643G
QFN14 3.0X2.5, 0.5P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC14
CASE 751EF
ISSUE O
DATE 30 SEP 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13739G
SOIC14
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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