74LVC08A [ONSEMI]
Low-Voltage CMOS Quad 2-Input NAND Gate;
| 型号： | 74LVC08A |
| 厂家： | 
ONSEMI |
| 描述： | Low-Voltage CMOS Quad 2-Input NAND Gate 栅 |
| 文件： | 总8页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC08A
Low-Voltage CMOS Quad
2-Input AND Gate
With 5 V−Tolerant Inputs
The 74LVC08A is a high performance, quad 2−input AND gate
operating from a 1.2 to 3.6 V supply. High impedance TTL compatible
inputs significantly reduce current loading to input drivers while TTL
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MARKING
compatible outputs offer improved switching noise performance. A V
I
DIAGRAMS
specification of 5.5 V allows 74LVC08A inputs to be safely driven
from 5.0 V devices.
14
Current drive capability is 24 mA at the outputs.
SOIC−14
D SUFFIX
CASE 751A
LVC08AG
AWLYWW
14
Features
1
1
• Designed for 1.2 V to 3.6 V V Operation
CC
• 5.0 V Tolerant Inputs − Interface Capability With 5.0 V TTL Logic
• 24 mA Output Sink and Source Capability
14
LVC
08A
TSSOP−14
DT SUFFIX
CASE 948G
• Near Zero Static Supply Current (10 mA) Substantially Reduces
14
System Power Requirements
ALYWG
G
1
• ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
1
A
L, WL
Y
= Assembly Location
= Wafer Lot
= Year
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
W, WW = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
1
© Semiconductor Components Industries, LLC, 2015
Publication Order Number:
September, 2015 − Rev. 0
74LVC08A/D
74LVC08A
1
A0
3
V
A2
B2
O2 A3
B3
O3
CC
O0
O1
O2
O3
2
4
B0
A1
14
13
12
11
10
9
8
6
5
B1
A2
13
11
8
12
10
9
B2
A3
B3
1
2
3
4
5
6
7
A0
B0
O0
A1
B1
O1 GND
Figure 1. Pinout: 14−Lead (Top View)
Figure 2. Logic Diagram
PIN NAMES
TRUTH TABLE
Inputs
Pins
Function
Data Inputs
Outputs
Outputs
An, Bn
On
An
L
Bn
L
On
L
L
H
L
L
H
H
L
H
H
H = High Voltage Level
L = Low Voltage Level
For I reasons, DO NOT FLOAT Inputs
CC
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2
74LVC08A
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
V
V
CC
DC Supply Voltage
−0.5 to +6.5
V
I
DC Input Voltage
−0.5 ≤ V ≤ +6.5
V
I
V
O
DC Output Voltage
−0.5 ≤ V ≤ V + 0.5
Output in HIGH or LOW State
(Note 1)
V
O
CC
I
DC Input Diode Current
DC Output Diode Current
−50
V < GND
mA
mA
mA
mA
mA
mA
°C
IK
I
I
−50
+50
50
V < GND
O
OK
V
O
> V
CC
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
O
I
100
100
CC
I
GND
T
−65 to +150
STG
T
L
Lead Temperature, 1 mm from Case for
10 Seconds
T = 260
L
°C
T
Junction Temperature Under Bias
Thermal Resistance (Note 2)
T = 135
°C
J
J
q
SOIC = 85
TSSOP = 100
°C/W
JA
MSL
Moisture Sensitivity
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I absolute maximum rating must be observed.
O
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage
Operating
Functional
V
1.65
1.2
3.6
3.6
V
Input Voltage
0
5.5
V
V
I
V
O
Output Voltage
HIGH or LOW State
3−State
0
0
V
CC
5.5
I
HIGH Level Output Current
mA
mA
OH
V
CC
V
CC
= 3.0 V − 3.6 V
= 2.7 V − 3.0 V
−24
−12
I
LOW Level Output Current
OL
V
CC
V
CC
= 3.0 V − 3.6 V
= 2.7 V − 3.0 V
24
12
T
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
−40
+125
°C
A
Dt/DV
ns/V
V
V
= 1.65 V to 2.7 V
= 2.7 V to 3.6 V
0
0
20
10
CC
CC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
74LVC08A
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
−405C to +1255C
Typ
Typ
(Note 3)
(Note 3)
Min
Max
−
Min
Max
−
Symbol
Parameter
Conditions
= 1.2 V
Unit
VIH
HIGH−level input
voltage
V
1.08
−
−
1.08
−
−
V
CC
V
CC
= 1.65 V to 1.95 V
0.65 x
VCC
−
0.65 x
VCC
−
V
V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
1.7
2.0
−
−
−
−
−
−
−
1.7
2.0
−
−
−
−
−
−
−
CC
CC
V
LOW−level input
voltage
V
CC
= 1.2 V
0.12
0.35 x
0.12
V
V
IL
V
CC
= 1.65 V to 1.95 V
−
−
0.35 x
VCC
V
CC
V
V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
−
−
−
−
0.7
0.8
−
−
−
−
0.7
0.8
CC
CC
V
OH
HIGH−level output
voltage
V = V or V
I
IH
IL
I
= −100 mA;
V
−
−
−
V −
CC
−
−
O
CC
V
= 1.65 V to 3.6 V
0.2
1.2
1.8
2.2
2.4
2.2
0.3
CC
I
= −4 mA; V = 1.65 V
−
−
−
−
−
−
−
−
−
−
1.05
1.65
2.05
2.25
2.0
−
−
−
−
−
−
−
−
−
−
O
CC
I
= −8 mA; V = 2.3 V
CC
O
I
I
I
= −12 mA; V = 2.7 V
CC
O
O
O
= −18 mA; V = 3.0 V
CC
= −24 mA; V = 3.0 V
CC
VOL
LOW−level output
voltage
V = V or V
IL
V
I
IH
I
O
= 100 mA;
−
−
0.2
−
−
0.3
V
CC
= 1.65 V to 3.6 V
I
= 4 mA; V = 1.65 V
−
−
−
−
−
−
−
0.45
0.6
0.4
0.55
5
−
−
−
−
−
−
−
0.65
0.8
0.6
0.8
20
O
CC
I
= 8 mA; V = 2.3 V
−
−
O
CC
I
O
= 12 mA; V = 2.7 V
−
−
CC
I
O
= −24 mA; V = 3.0 V
−
−
CC
II
Input leakage current
V = 5.5V or GND V = 3.6 V
0.1
0.1
0.1
0.1
mA
mA
I
CC
I
Power−off leakage
current
V or V = 5.5 V; V = 0.0 V
10
20
OFF
I
O
CC
I
Supply current
V = V or GND; I = 0 A;
−
−
0.1
5
10
−
−
0.1
5
40
mA
mA
CC
I
CC
O
V
CC
= 3.6 V
DI
Additional supply
current
per input pin;
V = V − 0.6 V; I = 0 A;
500
5000
CC
I
CC
O
V
CC
= 2.7 V to 3.6 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. All typical values are measured at T = 25°C and V = 3.3 V, unless stated otherwise.
A
CC
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4
74LVC08A
AC ELECTRICAL CHARACTERISTICS (t = t = 2.5 ns)
R
F
−405C to +855C
Min
Typ1
11.0
4.2
2.5
2.5
2.3
−
Max
Typ1
Symbol
Parameter
Conditions
= 1.2 V
Unit
t
pd
Propagation Delay (Note 5)
V
−
−
ns
CC
V
CC
= 1.65 V to 1.95 V
0.5
1.0
1.5
1.0
−
9.0
6.9
4.8
4.1
1.0
ns
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
V
= 3.0 V to 3.6 V
= 3.0 V to 3.6 V
CC
t
Output Skew Time (Note 6)
ns
sk(0)
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
5. t is the same as t
and t
.
pd
PLH
PHL
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
guaranteed by design.
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= +25°C
Min
Typ
Max
Symbol
Characteristic
Condition
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
Unit
V
OLP
Dynamic LOW Peak Voltage (Note 7)
V
CC
V
CC
0.8
0.6
V
L
IH
IL
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
V
OLV
Dynamic LOW Valley Voltage (Note 7)
V
CC
V
CC
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
−0.8
−0.6
V
L
IH
IL
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
7. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
CIN
Parameter
Input Capacitance
Condition
= 3.3 V, V = 0 V or V
Typical
4.0
Unit
pF
V
V
CC
I
CC
CC
COUT
CPD
Output Capacitance
= 3.3 V, V = 0 V or V
5.0
pF
CC
I
Power Dissipation Capacitance
(Note 8)
Per input; V = GND or V
pF
I
CC
V
= 1.65 V to 1.95 V
4.4
7.7
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
10.5
8. C is used to determine the dynamic power dissipation (P in mW).
PD
D
2
2
P
= C x V
x fi x N + S (C x V
x fo) where:
D
PD
CC
L
CC
fi = input frequency in MHz; fo = output frequency in MHz
C = output load capacitance in pF V = supply voltage in Volts
L
CC
N = number of outputs switching
2
S(C x V
x fo) = sum of the outputs.
L
CC
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5
74LVC08A
Vcc
0 V
Vmi
Vmi
An, Bn
t
t
PLH
PHL
V
OH
OL
Vmo
Vmo
On
V
WAVEFORM 1 − PROPAGATION DELAYS
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
t
R
F
W
Vcc
2.7 V
1.5 V
1.5 V
Symbol
Vmi
3.3 V + 0.3 V
1.5 V
V
CC
< 2.7 V
Vcc/2
Vcc/2
Vmo
1.5 V
Figure 3. AC Waveforms
V
CC
V
I
V
O
PULSE
GENERATOR
DUT
R
T
C
R
L
L
C includes jig and probe capacitance
L
R = Z
T
of pulse generator (typically 50 W)
OUT
Supply Voltage
(V)
Input
Load
V
V
I
t , t
C
R
CC
r
f
L
L
1.2
V
V
V
≤ 2 ns
≤ 2 ns
≤ 2 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 kW
1 kW
CC
CC
CC
1.65 − 1.95
2.3 − 2.7
2.7
500 W
500 W
500 W
2.7 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
3 − 3.6
Figure 4. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
74LVC08ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
74LVC08ADTR2G
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
74LVC08A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X K REF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
K1
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
0.10 (0.004)
K1 0.19
SEATING
L
M
6.40 BSC
0.252 BSC
−T−
H
G
DETAIL E
D
PLANE
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
74LVC08A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
0.25
C
A
B
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
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74LVC08A/D
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