74LVC126A [ONSEMI]
Low-Voltage CMOS Quad 2-Input NAND Gate;
| 型号： | 74LVC126A |
| 厂家： | 
ONSEMI |
| 描述： | Low-Voltage CMOS Quad 2-Input NAND Gate 栅 |
| 文件： | 总9页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC125A
Low-Voltage CMOS
Quad Buffer
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
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The 74LVC125A is a high performance, non−inverting quad buffer
operating from a 1.2 to 3.6 V supply. High impedance TTL compatible
inputs significantly reduce current loading to input drivers while TTL
MARKING
DIAGRAMS
compatible outputs offer improved switching noise performance. A V
I
specification of 5.5 V allows 74LVC125A inputs to be safely driven
from 5.0 V devices. The 74LVC125A is suitable for memory address
driving and all TTL level bus oriented transceiver applications.
Current drive capability is 24 mA at the outputs. The Output Enable
(OEn) inputs, when HIGH, disable the outputs by placing them in a
HIGH Z condition.
14
SOIC−14
D SUFFIX
CASE 751A
LVC125AG
AWLYWW
14
1
1
Features
• Designed for 1.2 to 3.6 V V Operation
14
CC
LVC
125A
ALYWG
G
• 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
• Supports Live Insertion and Withdrawal
TSSOP−14
DT SUFFIX
CASE 948G
14
1
1
• I
Specification Guarantees High Impedance When V = 0 V
CC
OFF
• 24 mA Output Sink and Source Capability
• Near Zero Static Supply Current in all Three Logic States (10 mA)
Substantially Reduces System Power Requirements
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
W, WW = Work Week
• ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
G or G
= Pb−Free Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
(Note: Microdot may be in either location)
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
October, 2015 − Rev. 0
74LVC125A/D
74LVC125A
V
OE3 D3
13 12
O3 OE2 D2
11 10 9
O2
8
CC
14
1
10
OE0
OE2
2
4
3
6
9
8
D0
O0 D2
OE3
O2
O3
13
OE1
5
12
11
D1
O1 D3
1
2
3
4
5
6
7
OE0 D0
O0 OE1 D1
O1 GND
Figure 1. Pinout: 14−Lead (Top View)
Figure 2. Logic Diagram
PIN NAMES
TRUTH TABLE
Pins
OEn
Dn
Function
Output Enable Inputs
Data Inputs
INPUTS
OUTPUTS
OEn
L
Dn
L
On
L
On
3−State Outputs
L
H
H
H
X
Z
H
=
=
=
=
High Voltage Level
Low Voltage Level
High Impedance State
L
Z
X
High or Low Voltage Level and Transitions Are
Acceptable; for I reasons, DO NOT FLOAT Inputs
CC
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2
74LVC125A
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
V
V
CC
DC Supply Voltage
−0.5 to +6.5
V
I
DC Input Voltage
−0.5 ≤ V ≤ +6.5
V
I
V
O
DC Output Voltage
−0.5 ≤ V ≤ +6.5
Output in 3−State
V
O
−0.5 ≤ V ≤ V + 0.5
Output in HIGH or LOW State
(Note 1)
V
O
CC
I
DC Input Diode Current
DC Output Diode Current
−50
V < GND
mA
mA
mA
mA
mA
mA
°C
IK
I
I
−50
+50
50
V < GND
O
OK
V
O
> V
CC
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
O
I
100
100
CC
I
GND
T
−65 to +150
STG
T
L
Lead Temperature, 1 mm from Case for
10 Seconds
T = 260
L
°C
T
Junction Temperature Under Bias
Thermal Resistance (Note 2)
T = 135
°C
J
J
q
SOIC = 85
TSSOP = 100
°C/W
JA
MSL
Moisture Sensitivity
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I absolute maximum rating must be observed.
O
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage
Operating
Functional
V
1.65
1.2
3.6
3.6
V
Input Voltage
0
5.5
V
V
I
V
O
Output Voltage
HIGH or LOW State
3−State
0
0
V
CC
5.5
I
HIGH Level Output Current
mA
mA
OH
V
CC
V
CC
= 3.0 V − 3.6 V
= 2.7 V − 3.0 V
−24
−12
I
LOW Level Output Current
OL
V
CC
V
CC
= 3.0 V − 3.6 V
= 2.7 V − 3.0 V
24
12
T
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
−40
+125
°C
A
Dt/DV
ns/V
V
CC
V
CC
= 1.65 V to 2.7 V
= 2.7 V to 3.6 V
0
0
20
10
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
74LVC125A
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
−405C to +1255C
Typ
Typ
(Note 3)
(Note 3)
Min
Max
−
Min
Max
−
Symbol
Parameter
Conditions
= 1.2 V
Unit
VIH
HIGH−level input
voltage
V
1.08
−
−
1.08
−
−
V
CC
V
CC
= 1.65 V to 1.95 V
0.65 x
VCC
−
0.65 x
VCC
−
V
V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
1.7
2.0
−
−
−
−
−
−
−
1.7
2.0
−
−
−
−
−
−
−
CC
CC
V
LOW−level input
voltage
V
CC
= 1.2 V
0.12
0.35 x
0.12
V
V
IL
V
CC
= 1.65 V to 1.95 V
−
−
0.35 x
VCC
V
CC
V
V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
−
−
−
−
0.7
0.8
−
−
−
−
0.7
0.8
CC
CC
V
OH
HIGH−level output
voltage
V = V or V
I
IH
IL
I
= −100 mA;
V
−
−
−
V −
CC
−
−
O
CC
V
= 1.65 V to 3.6 V
0.2
1.2
1.8
2.2
2.4
2.2
0.3
CC
I
= −4 mA; V = 1.65 V
−
−
−
−
−
−
−
−
−
−
1.05
1.65
2.05
2.25
2.0
−
−
−
−
−
−
−
−
−
−
O
CC
I
= −8 mA; V = 2.3 V
CC
O
I
I
I
= −12 mA; V = 2.7 V
CC
O
O
O
= −18 mA; V = 3.0 V
CC
= −24 mA; V = 3.0 V
CC
VOL
LOW−level output
voltage
V = V or V
IL
V
I
IH
I
O
= 100 mA;
−
−
0.2
−
−
0.3
V
CC
= 1.65 V to 3.6 V
I
= 4 mA; V = 1.65 V
−
−
−
−
−
−
−
0.45
0.6
0.4
0.55
5
−
−
−
−
−
−
−
0.65
0.8
0.6
0.8
20
O
CC
I
= 8 mA; V = 2.3 V
−
−
O
CC
I
O
I
O
= 12 mA; V = 2.7 V
−
−
CC
= 24 mA; V = 3.0 V
−
−
CC
II
Input leakage current
V = 5.5V or GND V = 3.6 V
0.1
0.1
0.1
0.1
mA
mA
I
CC
I
OFF−state output
current
VI = VIH or VIL;
5
20
OZ
V
O
= 5.5 V or GND; V = 3.6 V
CC
I
Power−off leakage
current
V or V = 5.5 V; V = 0.0 V
−
−
−
0.1
0.1
5
10
10
−
−
−
0.1
0.1
5
20
40
mA
mA
mA
OFF
I
O
CC
I
Supply current
V = V or GND; I = 0 A;
I CC O
CC
V
CC
= 3.6 V
DI
Additional supply
current
per input pin;
V = V − 0.6 V; I = 0 A;
500
5000
CC
I
CC
O
V
CC
= 2.7 V to 3.6 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. All typical values are measured at T = 25°C and V = 3.3 V, unless stated otherwise.
A
CC
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4
74LVC125A
AC ELECTRICAL CHARACTERISTICS (t = t = 2.5 ns)
R
F
−405C to +855C
Min
Typ1
12.0
5.4
2.9
2.8
2.5
16.0
5.0
2.9
3.1
2.3
7.0
4.6
2.6
3.1
3.2
−
Max
Typ1
Symbol
Parameter
Conditions
Unit
t
pd
Propagation Delay (Note 5)
Dn to On
V
CC
= 1.2 V
−
−
11.0
5.7
5.5
4.8
−
−
−
−
12.8
6.7
7.0
6.0
−
ns
V
= 1.65 V to 1.95 V
1.5
1.0
1.5
1.0
−
1.5
1.0
1.5
1.0
−
−
CC
V
= 2.3 V to 2.7 V
−
CC
V
CC
= 2.7 V
−
V
= 3.0 V to 3.6 V
= 1.2 V
−
CC
t
en
Enable Time (Note 6)
OEn to On
V
CC
−
ns
ns
ns
V
CC
= 1.65 V to 1.95 V
1.0
0.5
1.5
1.0
−
12.2
6.8
6.6
5.4
−
1.0
0.5
1.5
1.0
−
−
14.2
7.9
8.5
7.0
−
V
= 2.3 V to 2.7 V
−
CC
V
CC
= 2.7 V
−
V
= 3.0 V to 3.6 V
= 1.2 V
−
CC
t
dis
Disable Time (Note 7)
OEn to On
V
CC
−
V
CC
= 1.65 V to 1.95 V
2.2
0.5
1.5
1.0
−
7.5
4.2
5.0
4.6
1
2.2
0.5
1.5
1.0
−
−
8.7
5.0
6.5
6.0
1.5
V
= 2.3 V to 2.7 V
−
CC
V
CC
= 2.7 V
−
V
= 3.0 V to 3.6 V
−
CC
t
Output Skew Time (Note 8)
−
sk(0)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
5. t is the same as t
and t
.
pd
PLH
PHL
6. t is the same as t
and t
.
en
PZL
PZH
7. t is the same as t
and t
.
dis
PLZ
PHZ
8. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= +25°C
Min
Typ
Max
Symbol
Characteristic
Condition
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
Unit
V
OLP
Dynamic LOW Peak Voltage (Note 9)
V
CC
V
CC
0.8
0.6
V
L
IH
IL
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
V
OLV
Dynamic LOW Valley Voltage (Note 9)
V
CC
V
CC
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
−0.8
−0.6
V
L
IH
IL
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V
L
IH
IL
9. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Condition
= 3.3 V, V = 0 V or V
Typical
4.0
Unit
pF
CIN
V
V
CC
I
CC
CC
COUT
CPD
Output Capacitance
= 3.3 V, V = 0 V or V
5.0
pF
CC
I
Power Dissipation Capacitance
(Note 10)
Per input; V = GND or V
pF
I
CC
V
= 1.65 V to 1.95 V
6.0
9.4
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
12.4
10.C is used to determine the dynamic power dissipation (P in mW).
PD
D
2
2
P
= C x V
x fi x N + S (C x V
x fo) where:
D
PD
CC
L
CC
fi = input frequency in MHz; fo = output frequency in MHz
C = output load capacitance in pF V = supply voltage in Volts
L
CC
N = number of outputs switching
2
S(C x V
x fo) = sum of the outputs.
L
CC
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5
74LVC125A
V
CC
Vmi
Vmi
Dn
On
0 V
t
t
PHL
PLH
V
OH
Vmo
Vmo
V
OL
WAVEFORM 1 − PROPAGATION DELAYS
t
R
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
F
W
V
CC
Vmi
Vmi
OEn
0 V
t
t
PHZ
PZH
V
CC
V
OH
− 0.3 V
Vmo
Vmo
On
≈ 0 V
t
t
PLZ
PZL
≈ 3.0 V
On
V
OL
+ 0.3 V
GND
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
t
R
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
F
W
Figure 3. AC Waveforms
V
CC
Symbol 3.3 V 0.3 V
2.7 V
1.5 V
1.5 V
V
CC
< 2.7 V
Vmi
1.5 V
1.5 V
V
CC
/2
/2
Vmo
V
CC
V
V
+ 0.3 V
− 0.3 V
V
+ 0.3 V
V
+ 0.15 V
− 015 V
HZ
OL
OL
OL
V
V
OH
V
OH
− 0.3 V
V
OH
LZ
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6
74LVC125A
V
CC
V
EXT
V
I
V
O
OPEN
GND
R
1
PULSE
GENERATOR
DUT
R
T
C
R
L
L
C includes jig and probe capacitance
L
R = Z
T
of pulse generator (typically 50 W)
OUT
R = R
1
L
Supply Voltage
Input
Load
V
EXT
V
CC
(V)
V
I
t , t
C
R
t
, t
t
, t
t
, t
r
f
L
L
PLH PHL
PLZ PZL
PHZ PZH
1.2
V
V
V
≤ 2 ns
≤ 2 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 kW
1 kW
Open
Open
Open
Open
Open
2 x V
GND
CC
CC
1.65 − 1.95
2.3 − 2.7
2.7
2 x V
GND
GND
GND
GND
CC
CC
CC
≤ 2 ns
500 W
500 W
500 W
2 x V
CC
2.7 V
2.7 V
≤ 2.5 ns
≤ 2.5 ns
2 x V
CC
3 − 3.6
2 x V
CC
Figure 4. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
74LVC125ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
74LVC125ADTR2G
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
74LVC125A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X K REF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
0.10 (0.004)
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
0
8
0
8
DETAIL E
D
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
74LVC125A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
0.25
C
A
B
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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