74LVT162245MTDX [ONSEMI]
带 3 态输出和 A 端口输出具有 25 Ω 串联电阻的低电压 16 位收发器;
| 型号： | 74LVT162245MTDX |
| 厂家： | 
ONSEMI |
| 描述： | 带 3 态输出和 A 端口输出具有 25 Ω 串联电阻的低电压 16 位收发器 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总11页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
January 1999
Revised June 2005
74LVT162245 • 74LVTH162245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
and 25: Series Resistors in A Port Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVT162245 and LVTH162245 contains sixteen non-
inverting bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
5V VCC
■ Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162245),
also available without bushold feature (74LVT162245).
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
The LVT162245 and LVTH162245 are designed with
equivalent 25 series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
■ A Port outputs include equivalent series resistance of
25 making external termination resistors unnecessary
and reducing overshoot and undershoot
■ A Port outputs source/sink 12 mA.
B Port outputs source/sink 32 mA/ 64 mA
The LVTH162245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
■ Functionally compatible with the 74 series 162245
■ Latch-up performance exceeds 500 mA
■ ESD performance:
These non-inverting transceivers are designed for low volt-
age (3.3V) VCC applications, but with the capability to pro-
Human-body model 2000V
vide a TTL interface to a 5V environment. The LVT162245
and LVTH162245 are fabricated with an advanced
BiCMOS technology to achieve high speed operation simi-
lar to 5V ABT while maintaining a low power dissipation.
Machine model 200V
Charged-device model 1000V
■ Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
Package Number
Package Description
74LVT162245G
(Note 1)(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVT162245MEA
(Note 2)
MS48A
MTD48
BGA54A
MS48A
MS48A
MTD48
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVT162245MTD
(Note 2)
74LVTH162245G
(Note 1)(Note 2)
74LVTH162245MEA
74LVTH162245MEX
74LVTH162245MTD
74LVTH162245MTX
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBE]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation
DS012446
www.fairchildsemi.com
Logic Symbol
Connection Diagrams
Pin Descriptions
Pin Names
Description
Pin Assignments for SSOP and TSSOP
OEn
Output Enable Input (Active LOW)
Transmit/Receive Input
T/Rn
A0–A15
B0–B15
NC
Side A Inputs/3-STATE Outputs
Side B Inputs/3-STATE Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
B0
B2
NC
B1
T/R1
NC
OE1
NC
NC
A1
A0
A2
B4
B3
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
A3
A4
B6
B5
A5
A6
B8
B7
A7
A8
B10
B12
B14
B9
A9
A10
A12
A14
G
H
B11
B13
A11
A13
J
B15
NC
T/R2
OE2
NC
A15
Truth Tables
Inputs
Outputs
OE1
T/R1
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH-Z State on A0–A7, B0–B7
Pin Assignment for FBGA
H
Inputs
Outputs
OE2
T/R2
L
L
L
H
X
Bus B8–B15 Data to Bus A8–A15
Bus A8–A15 Data to Bus B8–B15
HIGH-Z State on A8–A15, B8–B15
H
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
(Top Thru View)
www.fairchildsemi.com
2
Functional Description
The LVT162245 and LVTH162245 contain sixteen non-
inverting bidirectional buffers with 3-STATE outputs. The
device is byte controlled with each byte functioning identi-
cally, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.fairchildsemi.com
Absolute Maximum Ratings(Note 3)
Symbol
VCC
Parameter
Supply Voltage
Value
0.5 to 4.6
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
50
Conditions
Units
V
V
VI
DC Input Voltage
Output Voltage
VO
Output in 3-STATE
V
Output in HIGH or LOW State (Note 4)
VI GND
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
mA
mA
50
VO GND
64
VO VCC Output at HIGH State
VO VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
64
mA
mA
C
IGND
TSTG
128
65 to 150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
32
Units
Supply Voltage
V
V
VI
Input Voltage
IOH
HIGH-Level Output Current
B Port
A Port
B Port
A Port
mA
mA
12
IOL
LOW-Level Output Current
64
12
TA
t/ V
Free Air Operating Temperature
40
0
85
C
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V
10
ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: I Absolute Maximum Rating must be observed.
O
DC Electrical Characteristics
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
2.7
Min
Max
V
V
V
V
Input Clamp Diode Voltage
Input HIGH Voltage
1.2
V
V
V
V
V
I
18 mA
0.1V or
0.1V
12 mA
IK
I
2.7–3.6
2.7–3.6
3.0
2.0
V
V
IH
IL
O
Input LOW Voltage
0.8
V
O
CC
Output HIGH Voltage
2.0
I
I
OH
OH
OH
A Port
2.7–3.6
100 A
V
0.2
CC
2.7
3.0
3.0
2.7
2.7
3.0
3.0
3.0
2.4
2.0
I
I
I
I
I
I
I
I
8 mA
OH
OH
OL
OL
OL
OL
OL
OL
B Port
A Port
V
32 mA
V
Output LOW Voltage
0.8
0.2
V
V
12 mA
OL
100
A
0.5
24 mA
16 mA
32 mA
64 mA
0.8V
0.4
B Port
V
0.5
0.55
I
Bushold Input Minimum Drive
75
75
V
V
I(HOLD)
I
I
3.0
3.0
A
A
(Note 5)
2.0V
I
Bushold Input Over-Drive
Current to Change State
Input Current
500
500
(Note 6)
(Note 7)
I(OD)
(Note 5)
I
3.6
3.6
10
1
V
V
V
V
5.5V
0V or V
0V
I
I
I
I
I
Control Pins
Data Pins
CC
A
A
5
3.6
0
1
V
CC
I
Power Off Leakage Current
100
0V V or V
5.5V
OFF
I
O
www.fairchildsemi.com
4
DC Electrical Characteristics (Continued)
V
T
40 C to 85 C
Min Max
CC
A
Symbol
Parameter
Power Up/Down
Units
Conditions
0.5V to 3.0V
(V)
I
V
V
V
V
PU/PD
O
0–1.5V
100
A
3-STATE Current
GND to V
0.5V
I
CC
I
I
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3.6
3.6
5
5
A
A
OZL
OZL
O
O
0.0V
(Note 5)
I
I
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3.6
3.6
5
5
A
A
V
V
3.0V
3.6V
OZH
OZH
O
O
(Note 5)
I
I
I
I
I
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
10
0.19
5
A
mA
mA
mA
V
V
O
5.5V
OZH
CCH
CCL
CCZ
CCZ
CC
Outputs HIGH
Outputs LOW
Power Supply Current
Power Supply Current
0.19
Outputs Disabled
Power Supply Current
V
V
5.5V,
Outputs Disabled
One Input at V
CC
O
3.6
3.6
0.19
0.2
mA
mA
I
Increase in Power Supply Current
(Note 8)
0.6V
CC
CC
Other Inputs at V or GND
CC
Note 5: Applies to Bushold versions only (74LVTH162245).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.
CC
Dynamic Switching Characteristics (Note 9)
V
T
25 C
Conditions
CC
A
Symbol
Parameter
Units
C
50 pF, R
500
(V)
3.3
3.3
Min
Typ
Max
L
L
V
V
Quiet Output Maximum Dynamic V
0.8
0.8
V
V
(Note 10)
(Note 10)
OLP
OL
Quiet Output Minimum Dynamic V
OLV
OL
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.
5
www.fairchildsemi.com
AC Electrical Characteristics
T
40 C to 85 C
50 pF, R 500
A
C
L
L
Symbol
Parameter
Units
V
3.3V 0.3V
V
2.7V
Max
CC
CC
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
1.5
Max
4.0
3.7
3.5
3.5
5.3
5.6
4.6
5.3
5.6
5.5
5.4
5.1
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
1.5
t
Propagation Delay Data to A Port Output
Propagation Delay Data to B Port Output
Output Enable Time for A Port Output
Output Enable Time for B Port Output
Output Disable Time for A Port Output
Output Disable Time for B Port Output
4.6
4.1
3.9
3.9
6.3
7.2
5.4
6.9
6.3
5.5
6.1
5.4
PLH
ns
ns
ns
ns
ns
ns
ns
ns
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
A Port Output to Output Skew
(Note 11)
OSHL
1.0
1.0
1.0
1.0
t
OSLH
t
B Port Output to Output Skew
(Note 11)
OSHL
t
OSLH
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
Capacitance (Note 12)
Symbol
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Typical
Units
pF
C
V
V
0V, V 0V or V
4
8
IN
CC
I
CC
C
3.0V, V
0V or V
CC
pF
I/O
CC
O
Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
www.fairchildsemi.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9
www.fairchildsemi.com
ON Semiconductor and
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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
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