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January 2000

Revised October 2001

74LVT16646 • 74LVTH16646

Low Voltage 16-Bit Transceiver/Register

with 3-STATE Outputs

General Description

Features

■ Input and output interface capability to systems at

The LVT16646 and LVTH16646 contains sixteen non-

inverting bidirectional registered bus transceivers providing

multiplexed transmission of data directly from the input bus

or from the internal storage registers. Each byte has sepa-

rate control inputs which can be shorted together for full

16-bit operation. The DIR inputs determine the direction of

data flow through the device. The CPAB and CPBA inputs

load data into the registers on the LOW-to-HIGH transition

(see Functional Description).

5V V_CC

■ Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16646)

■ Also available without bushold feature (74LVT16646)

■ Live insertion/extraction permitted

■ Power Up/Down high impedance provides

glitch-free bus loading

The LVTH16646 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

■ Outputs source/sink −32 mA/+64 mA

■ Latch-up conforms to JEDEC JED78

■ ESD performance:

These transceivers are designed for low-voltage (3.3V)

V_CCapplications, but with the capability to provide a TTL

Human-body model > 2000V

Machine model > 200V

interface to

a 5V environment. The LVT16646 and

Charged-device model > 1000V

LVTH16646 are fabricated with an advanced BiCMOS

technology to achieve high speed operation similar to 5V

ABT while maintaining low power dissipation.

Ordering Code:

Order Number Package Number

Package Description

74LVT16646MEA

(Preliminary)

MS56A

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVT16646MTD

(Preliminary)

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVTH16646MEA

74LVTH16646MTD

MS56A

MTD56

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

DS012023

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Connection Diagram

Pin Descriptions

Pin Names

Description

A₀–A₁₅

B₀–B₁₅

Data Register A Inputs/3-STATE Outputs

Data Register B Inputs/3-STATE Outputs

CPAB_n, CPBA_nClock Pulse Inputs

SAB_n, SBA_n

OE₁, OE₂

DIR_n

Select Inputs

Output Enable Inputs

Direction Control Inputs

Truth Table

(Note 1)

Inputs

Data I/O

Output Operation Mode

OE₁

DIR₁CPAB₁CPBA₁SAB₁SBA₁

A_0–7

B_0–7

H

L

X

H

L

H or L H or L

X

L

X

L

Isolation

X

Input

Input Clock A_nData into A Register

Clock B_nData Into B Register

X

A_nto B_n—Real Time (Transparent Mode)

L

Input Output Clock A_nData to A Register

A Register to B_n(Stored Mode)

H or L

H

X

Clock A_nData into A Register and Output to B_n

B_nto A_n—Real Time (Transparent Mode)

Output Input Clock B_nData into B Register

X

L

H or L

H

B Register to A_n(Stored Mode)

L

Clock B_ninto B Register and Output to A_n

H = HIGH Voltage Level

X = Immaterial

L = LOW Voltage Level

= LOW-to-HIGH Transition.

Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,

data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control

pins.

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2

Functional Description

In the transceiver mode, data present at the HIGH imped-

ance port may be stored in either the A or B register or

both. The select (SAB_n, SBA_n) controls can multiplex

The direction control (DIR_n) determines which bus will

receive data when OE_nis LOW. In the isolation mode (OE_n

HIGH), A data may be stored in one register and/or B data

may be stored in the other register. When an output func-

tion is disabled, the input function is still enabled and may

be used to store and transmit data. Only one of the two

busses, A or B, may be driven at a time.

stored and real-time. The examples shown below demon-

strate the four fundamental bus-management functions

that can be performed.

Real-Time Transfer

Bus B to Bus A

Real-Time Transfer

Bus A to Bus B

OE DIR CPAB CPBA SAB SBA

L

X

L

H

X

L

X

Transfer Storage

Data to A or B

Storage

OE DIR CPAB CPBA SAB SBA

L

H

L

X

L

X

L

X

H or L

X

H

X

H

H or L

H

X

3

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Logic Diagrams

Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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4

Absolute Maximum Ratings(Note 2)

Symbol

V_CC

Parameter

Supply Voltage

Value

−0.5 to +4.6

−0.5 to +7.0

−50

Conditions

Units

V

V_I

DC Input Voltage

V

V_O

DC Output Voltage

Output in 3-STATE

V

Output in HIGH or LOW State (Note 3)

V

I_IK

I_OK

I_O

DC Input Diode Current

DC Output Diode Current

DC Output Current

V_I< GND

mA

−50

V

_O< GND

64

_O> V_CCOutput at HIGH State

_O> V_CCOutput at LOW State

mA

128

I_CC

DC Supply Current per Supply Pin

DC Ground Current per Ground Pin

Storage Temperature

±64

mA

°C

I_GND

T_STG

±128

−65 to +150

Recommended Operating Conditions

Symbol

V_CC

Parameter

Min

2.7

0

Max

3.6

5.5

−32

64

Units

Supply Voltage

V

V_I

Input Voltage

I_OH

I_OL

T_A

HIGH-Level Output Current

LOW-Level Output Current

Free-Air Operating Temperature

mA

−40

85

°C

∆t/∆V

Input Edge Rate, V_IN= 0.8V–2.0V, V_CC= 3.0V

0

10

ns/V

Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.

Note 3: I_OAbsolute Maximum Rating must be observed.

5

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DC Electrical Characteristics

V_CC

T _A= −40°C to +85°C

Symbol

Parameter

Units

Conditions

I_I= −18 mA

(V)

2.7

Min

Max

V_IK

Input Clamp Diode Voltage

Input HIGH Voltage

−1.2

V

V_IH

V_IL

2.7–3.6

2.7

2.0

V

_O≤ 0.1V or

_O≥ V_CC− 0.1V

Input LOW Voltage

0.8

V

V_OH

Output HIGH Voltage

V_CC− 0.2

V

I_OH= −100 µA

I_OH= −8 mA

I_OH= −32 mA

I_OL= 100 µA

I_OL= 24 mA

I_OL= 16 mA

I_OL= 32 mA

I_OL= 64 mA

2.4

3.0

2.0

V

V_OL

Output LOW Voltage

2.7

0.2

0.5

V

2.7

V

3.0

0.4

V

3.0

0.5

V

3.0

0.55

V

I_I(HOLD)

(Note 4)

I_I(OD)

Bushold Input Minimum Drive

75

−75

µA

V_I= 0.8V

3.0

V_I= 2.0V

Bushold Input Over-Drive

Current to Change State

Input Current

500

(Note 5)

(Note 4)

I_I

−500

(Note 6)

3.6

10

±1

V_I= 5.5V

Control Pins

Data Pins

V_I= 0V or V_CC

V_I= 0V

−5

3.6

0

1

V_I= V_CC

I_OFF

Power Off Leakage Current

Power Up/Down 3-STATE

Output Current

±100

0V ≤ V_Ior V_O≤ 5.5V

I_PU/PD

V_O= 0.5V to 3.0V

0–1.5V

±100

µA

V_I= GND or V_CC

I_OZL(Note 4) 3-STATE Output Leakage Current

I_OZL3-STATE Output Leakage Current

_OZH(Note 4) 3-STATE Output Leakage Current

3.6

−5

µA

V

_O= 0.0V

_O= 0.5V

I

5

µA

_O= 3.6V

I_OZH

3-STATE Output Leakage Current

Power Supply Current

5

µA

_O= 3.0V

+

10

µA

_CC< V_O≤ 5.5V

I_CCH

I_CCL

I_CCZ

0.19

5

mA

Outputs HIGH

Outputs LOW

Power Supply Current

0.19

Outputs Disabled

I_CCZ

+

Power Supply Current

V_CC≤ V_O≤ 5.5V,Outputs Disabled

∆I_CC

Increase in Power Supply Current

(Note 7)

One Input at V_CC− 0.6V

3.6

0.2

mA

Other Inputs at V_CCor GND

Note 4: Applies to bushold version only (74LVTH16646)

Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.

Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.

Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V_CCor GND.

Dynamic Switching Characteristics (Note 8)

T

_A= 25°C

Conditions

V_CC

(V)

Symbol

Parameter

Units

C

_L= 50 pF, R_L= 500Ω

Min

Typ

0.8

Max

V_OLP

V_OLV

Quiet Output Maximum Dynamic V_OL

Quiet Output Minimum Dynamic V_OL

3.3

V

(Note 9)

−0.8

Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested.

Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.

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6

AC Electrical Characteristics

T

_A= −40°C to +85°C

_L= 50 pF, R_L= 500Ω

_CC= 3.3 ± 0.3V _CC= 2.7V

Max

C

Symbol

Parameter

Units

V

Min

150

1.3

1.0

2.0

1.0

1.5

3.3

1.2

2.0

0.5

Max

Min

f_MAX

Maximum Clock Frequency

150

1.3

1.0

2.0

1.0

1.5

3.3

1.5

2.8

0.0

0.5

MHz

ns

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PZH

t_PZL

t_PHZ

t_PLZ

t_PZH

t_PZL

t_PHZ

t_PLZ

t_W

Propagation Delay

CPAB or CPBA to A or B

Propagation Delay

Data to A or B

5.4

5.2

4.4

4.6

4.8

4.7

5.1

5.6

5.4

4.9

5.4

6.4

5.4

5.9

5.8

4.7

5.1

5.4

5.6

5.4

6.0

6.1

5.4

6.4

7.1

5.9

ns

Propagation Delay

SBA or SAB to A or B

Output Enable Time

OE to A or B

Output Disable Time

OE to A or B

Output Enable Time

DIR to A or B

Output Disable Time

DIR to A or B

ns

Pulse Duration

CPAB or CPBA HIGH or LOW

t_S

Setup Time

A or B before CPAB or CPBA, Data HIGH

A or B before CPAB or CPBA, Data LOW

A or B after CPAB or CPBA, Data HIGH

A or B after CPAB or CPBA, Data LOW

t_H

Hold Time

ns

t_OSHL

t_OSLH

Output to Output Skew (Note 10)

1.0

Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t_OSHL) or LOW-to-HIGH (t_OSLH).

Capacitance (Note 11)

Symbol

C_IN

C_I/O

Parameter

Input Capacitance

Input/Output Capacitance

Conditions

_CC= Open, V_I= 0V or V_CC

_CC= 3.0V, V_O= 0V or V_CC

Typical

Units

pF

V

4

8

pF

Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.

7

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Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS56A

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8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD56

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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9

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ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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1


型号：	74LVTH16646MTDX
厂家：	ONSEMI
描述：	带3态输出的低电压16位收发器/寄存器 PC 信息通信管理光电二极管逻辑集成电路触发器
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