74LVTH2244MTCX [ONSEMI]

低压八路缓冲器/线路驱动器(带3态输出);
74LVTH2244MTCX
型号: 74LVTH2244MTCX
厂家: ONSEMI    ONSEMI
描述:

低压八路缓冲器/线路驱动器(带3态输出)

驱动 信息通信管理 光电二极管 逻辑集成电路 驱动器
文件: 总11页 (文件大小:399K)
中文:  中文翻译
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February 2008  
74LVT2244, 74LVTH2244  
Low Voltage Octal Buffer/Line Driver with 3-STATE  
Outputs and 25Series Resistors in the Outputs  
Features  
General Description  
Input and output interface capability to systems at  
The LVT2244 and LVTH2244 are octal buffers and line  
drivers designed to be employed as memory address  
drivers, clock drivers and bus oriented transmitters or  
receivers which provides improved PC board density.  
The equivalent 25-Series resistors helps reduce output  
overshoot and undershoot.  
5V V  
CC  
Equivalent 25-Series resistors on outputs  
Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH2244),  
also available without bushold feature (74LVT2244)  
The LVTH2244 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
Live insertion/extraction permitted  
Power Up/Down high impedance provides glitch-free  
bus loading  
Outputs source/sink –12mA/+12mA  
Latch-up performance exceeds 500mA  
ESD performance:  
These octal buffers and line drivers are designed for low-  
voltage (3.3V) V applications, but with the capability to  
CC  
provide a TTL interface to a 5V environment. The  
LVT2244 and LVTH2244 are fabricated with an  
advanced BiCMOS technology to achieve high speed  
operation similar to 5V ABT while maintaining low power  
dissipation.  
– Human-body model > 2000V  
– Machine model > 200V  
– Charged-device model > 1000V  
Ordering Information  
Package  
Order Number  
74LVT2244WM  
74LVT2244SJ  
Number  
Package Description  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20D  
74LVT2244MTC  
MTC20  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74LVTH2244WM  
74LVTH2244SJ  
74LVTH2244MTC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MTC20  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
©1999 Fairchild Semiconductor Corporation  
74LVT2244, 74LVTH2244 Rev. 1.5.0  
www.fairchildsemi.com  
Connection Diagram  
Logic Symbol  
IEEE/IEC  
Pin Description  
Pin Names  
Description  
OE , OE  
3-STATE Output Enable Inputs  
1
2
I –I  
Inputs  
0
7
Truth Tables  
O –O  
Outputs  
0
7
Inputs  
Outputs  
OE  
L
I
(Pins 12, 14, 16, 18)  
1
n
L
L
H
Z
L
H
X
H
Inputs  
Outputs  
OE  
L
I
(Pins 3, 5, 7, 9)  
2
n
L
L
H
Z
L
H
X
H
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
©1999 Fairchild Semiconductor Corporation  
74LVT2244, 74LVTH2244 Rev. 1.5.0  
www.fairchildsemi.com  
2
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
Parameter  
Rating  
V
Supply Voltage  
–0.5V to +4.6V  
CC  
V
DC Input Voltage  
DC Output Voltage  
Output in 3-STATE  
–0.5V to +7.0V  
I
V
O
–0.5V to +7.0V  
–0.5V to +7.0V  
–50mA  
(1)  
Output in HIGH or LOW State  
I
DC Input Diode Current, V < GND  
I
IK  
I
DC Output Diode Current, V < GND  
–50mA  
OK  
O
I
DC Output Current, V > V  
O
O
CC  
Output at HIGH State  
Output at LOW State  
64mA  
128mA  
I
DC Supply Current per Supply Pin  
DC Ground Current per Ground Pin  
Storage Temperature  
64mA  
CC  
I
128mA  
GND  
T
–65°C to +150°C  
STG  
Note:  
1. I Absolute Maximum Rating must be observed.  
O
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to absolute maximum ratings.  
Symbol  
Parameter  
Min.  
2.7  
0
Max.  
3.6  
5.5  
–12  
12  
Units  
V
V
Supply Voltage  
Input Voltage  
CC  
V
V
I
I
HIGH-Level Output Current  
LOW-Level Output Current  
Free-Air Operating Temperature  
mA  
mA  
°C  
OH  
I
OL  
T
–40  
0
85  
A
t/V  
Input Edge Rate, V = 0.8V–2.0V, V = 3.0V  
10  
ns/V  
IN  
CC  
©1999 Fairchild Semiconductor Corporation  
74LVT2244, 74LVTH2244 Rev. 1.5.0  
www.fairchildsemi.com  
3
DC Electrical Characteristics  
TA = –40°C to +85°C  
Symbol  
Parameter  
Input Clamp Diode Voltage  
Input HIGH Voltage  
VCC (V)  
2.7  
Conditions  
Min.  
Typ.(2) Max. Units  
V
V
I = –18mA  
–1.2  
0.8  
V
V
V
V
IK  
IH  
I
2.7–3.6  
2.7–3.6  
2.7–3.6  
3.0  
V
V
0.1V or  
2.0  
O
O
V – 0.1V  
CC  
V
Input LOW Voltage  
IL  
V
Output HIGH Voltage  
I
I
I
I
= –100µA  
= –12mA  
= 100µA  
= 12mA  
V
– 0.2  
CC  
OH  
OH  
OH  
OL  
OL  
2.0  
V
Output LOW Voltage  
2.7  
0.2  
0.8  
V
OL  
3.0  
(3)  
I
Bushold Input Minimum Drive  
3.0  
V = 0.8V  
75  
–75  
500  
–500  
µA  
µA  
µA  
I(HOLD)  
I
V = 2.0V  
I
(3)  
(4)  
I
Bushold Input Over-Drive Current to  
Change State  
3.0  
I(OD)  
(5)  
I
Input Current  
Control Pins  
Data Pins  
3.6  
3.6  
3.6  
V = 5.5V  
10  
1
I
I
V = 0V or V  
I
CC  
V = 0V  
–5  
1
I
V = V  
I
CC  
I
Power Off Leakage Current  
0
0V V or V 5.5V  
100  
100  
µA  
µA  
OFF  
I
O
I
Power up/down 3-STATE  
Output Current  
0–1.5  
V = 0.5V to 3.0V,  
O
PU/PD  
V = GND or V  
I
CC  
I
3-STATE Output Leakage Current  
3-STATE Output Leakage Current  
3-STATE Output Leakage Current  
Power Supply Current  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
V
V
V
= 0.5V  
= 3.0V  
–5  
5
µA  
µA  
OZL  
O
I
OZH  
O
I
+
< V 5.5V  
10  
µA  
OZH  
CC  
O
I
Outputs HIGH  
Outputs LOW  
0.19  
5
mA  
mA  
mA  
mA  
CCH  
I
Power Supply Current  
CCL  
CCZ  
I
Power Supply Current  
Outputs Disabled  
0.19  
0.19  
I
+
Power Supply Current  
V
V 5.5V,  
CC O  
CCZ  
Outputs Disabled  
(6)  
I  
Increase in Power Supply Current  
3.6  
One Input at  
0.2  
mA  
CC  
V
– 0.6V, Other  
CC  
Inputs at V or GND  
CC  
Notes:  
2. All typical values are at V = 3.3V, T = 25°C.  
CC  
A
3. Applies to bushold versions only (74LVTH2244).  
4. An external driver must source at least the specified current to switch from LOW-to-HIGH.  
5. An external driver must sink at least the specified current to switch from HIGH-to-LOW.  
6. This is the increase in supply current for each, input that is at the specified voltage level rather than V or GND.  
CC  
©1999 Fairchild Semiconductor Corporation  
74LVT2244, 74LVTH2244 Rev. 1.5.0  
www.fairchildsemi.com  
4
(7)  
Dynamic Switching Characteristics  
Conditions  
T = 25°C  
A
Symbol  
Parameter  
V
CC  
(V) C = 50pF, R = 500Min. Typ. Max. Units  
L
L
(8)  
(8)  
V
Quiet Output Maximum  
3.3  
0.8  
V
V
OLP  
Dynamic V  
OL  
V
Quiet Output Minimum  
Dynamic V  
3.3  
–0.8  
OLV  
OL  
Notes:  
7. Characterized in SOIC package. Guaranteed parameter, but not tested.  
8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.  
AC Electrical Characteristics  
T = –40°C to +85°C,  
A
C = 50pF, R = 500Ω  
L
L
V
= 3.3V 0.3V  
V
= 2.7V  
CC  
CC  
(9)  
Symbol  
Parameter  
Min.  
1.0  
1.0  
1.0  
1.1  
1.9  
1.8  
Typ.  
Max.  
Min.  
1.0  
1.0  
1.0  
1.1  
1.9  
1.8  
Max.  
Units  
t
t
Propagation Delay Data to Output  
4.4  
4.1  
5.9  
5.5  
6.1  
4.5  
1.0  
5.3  
4.4  
7.7  
6.2  
6.8  
4.5  
1.0  
ns  
PLH  
PHL  
PZH  
t
Output Enable Time  
Output Disable Time  
ns  
ns  
ns  
t
PZL  
PHZ  
t
t
PLZ  
(10)  
t
, t  
Output to Output Skew  
OSHL OSLH  
Notes:  
9. All typical values are at V = 3.3V, T = 25°C.  
CC  
A
10. Skew is defined as the absolute value of the difference between the actual propagation delay for any two  
separate outputs of the same device. The specification applies to any outputs switching in the same direction,  
either HIGH-to-LOW (t  
) or LOW-to-HIGH (t  
).  
OSHL  
OSLH  
(11)  
Capacitance  
Symbol  
Parameter  
Conditions  
Typical  
Units  
pF  
C
Input Capacitance  
Output Capacitance  
V
V
= 0V, V = 0V or V  
CC  
3
6
IN  
CC  
I
C
= 3.0V, V = 0V or V  
CC  
pF  
OUT  
CC  
O
Note:  
11. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883B, Method 3012.  
©1999 Fairchild Semiconductor Corporation  
74LVT2244, 74LVTH2244 Rev. 1.5.0  
www.fairchildsemi.com  
5
Physical Dimensions  
13.00  
12.60  
A
11.43  
20  
11  
B
9.50  
10.65 7.60  
10.00 7.40  
2.25  
1
PIN ONE  
INDICATOR  
10  
0.65  
0.51  
0.35  
1.27  
1.27  
M
0.25  
C B A  
LAND PATTERN RECOMMENDATION  
SEE DETAIL A  
2.65 MAX  
0.33  
0.20  
C
0.10  
C
0.30  
0.10  
SEATING PLANE  
0.75  
0.25  
X 45°  
NOTES: UNLESS OTHERWISE SPECIFIED  
(R0.10)  
(R0.10)  
A) THIS PACKAGE CONFORMS TO JEDEC  
MS-013, VARIATION AC, ISSUE E  
GAGE PLANE  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C) DIMENSIONS DO NOT INCLUDE MOLD  
FLASH OR BURRS.  
0.25  
8°  
0°  
D) CONFORMS TO ASME Y14.5M-1994  
1.27  
0.40  
SEATING PLANE  
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L  
F) DRAWING FILENAME: MKT-M20BREV3  
(1.40)  
DETAIL A  
SCALE: 2:1  
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
©1999 Fairchild Semiconductor Corporation  
74LVT2244, 74LVTH2244 Rev. 1.5.0  
www.fairchildsemi.com  
6
Physical Dimensions (Continued)  
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
©1999 Fairchild Semiconductor Corporation  
74LVT2244, 74LVTH2244 Rev. 1.5.0  
www.fairchildsemi.com  
7
Physical Dimensions (Continued)  
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
©1999 Fairchild Semiconductor Corporation  
74LVT2244, 74LVTH2244 Rev. 1.5.0  
www.fairchildsemi.com  
8
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®
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APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS  
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S  
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR  
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,  
which, (a) are intended for surgical implant into the body or  
(b) support or sustain life, and (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
result in a significant injury of the user.  
device, or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
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PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
This datasheet contains the design specifications for product  
development. Specifications may change in any manner without notice.  
Advance Information  
Formative or In Design  
This datasheet contains preliminary data; supplementary data will be  
published at a later date. Fairchild Semiconductor reserves the right to  
make changes at any time without notice to improve design.  
Preliminary  
First Production  
Full Production  
Not In Production  
This datasheet contains final specifications. Fairchild Semiconductor  
reserves the right to make changes at any time without notice to improve  
the design.  
No Identification Needed  
Obsolete  
This datasheet contains specifications on a product that has been  
discontinued by Fairchild Semiconductor. The datasheet is printed for  
reference information only.  
Rev. I33  
©1999 Fairchild Semiconductor Corporation  
74LVT2244, 74LVTH2244 Rev. 1.5.0  
www.fairchildsemi.com  
9
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