74LVX3245MTC [ONSEMI]
带 3 状态输出的 8 位双电源转换收发器;
| 型号： | 74LVX3245MTC |
| 厂家： | 
ONSEMI |
| 描述： | 带 3 状态输出的 8 位双电源转换收发器 光电二极管 逻辑集成电路 |
| 文件： | 总12页 (文件大小：585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 2016
74LVX3245
8-Bit, Dual-Supply Translating Transceiver with
3-State Outputs
Features
Description
The 74LVX3245 is a dual-supply, 8-bit translating
transceiver designed to interface between a 3 V bus and
a 5 V bus in a mixed 5 V supply environment. The
Transmit/ Receive (T/R¯ ) input determines the direction
of data flow. Transmit (active-HIGH) enables data from
A-ports to B-ports; receive (active-LOW) enables data
from B-ports to A-ports. The output enable input, when
HIGH, disables both A- and B-ports by placing them in a
high-impedance condition. The A-port interfaces with
the 3 V bus; the B-port interfaces with the 5 V bus.
.
.
.
Bidirectional Interface Between 3 V and 5 V Buses
Inputs Compatible with TTL Level
3 V Data Flow at A-Port and 5 V Data Flow at B-
Port
.
.
Outputs Source / Sink: 24 mA
Guaranteed Simultaneous Switching Noise Level
and Dynamic Threshold Performance
.
.
Implements Proprietary EMI Reduction Circuitry
Functionally Compatible with the 74 Series 245
The 74LVX3245 is suitable for mixed-voltage
applications, such as notebook computers using 3.3 V
CPU and 5V peripheral components.
Related Resources
.
AN-5001 — Using Fairchild’s LVX Low-Voltage
Dual-Supply CMOS Translating Transceivers
Ordering Information
Operating
Temperature Range
Part Number
Package
Packing Method
74LVX3245QSC
74LVX3245QSCX
74LVX3245MTC
Tubes
Tape and Reel
Tubes
24-Lead Quarter-Size Outline Package
(QSOP), JEDEC MO-137, 0.150" Wide
-40 to +85°C
24-Lead Thin-Shrink Small-Outline
Package (TSSOP), JEDEC MO-153,
4.4 mm Wide
74LVX3245MTCX
Tape and Reel
© 1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX3245 • Rev. 1.6
Logic Symbol
Figure 1.
Logic Symbol
Pin Configuration
Figure 2.
Pin Configuration
Pin Definitions
Pin #
Name
Description
1
2
VCCA
T/R¯
Supply Voltage
Transmit/Receive Input
A0, A1, A2, A3, A4,
A5, A6, A7
3, 4, 5, 6, 7, 8, 9, 10
11, 12, 13
Port-A Inputs or 3-State Outputs
Ground
GND
14, 15, 16, 17, 18, 19, B7, B6, B5, B4, B3,
Port-B Inputs or 3-State Outputs
20, 21
B2, B1, B0
22
/OE
Output Enable Input
No Connect
23
NC
24
VCCB
Supply Voltage
© 1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX3245 • Rev. 1.6
2
Logic Diagram
Figure 3.
Logic Diagram
Table 1. Truth Table
/OE
Inputs
Outputs
T/R¯
L
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
© 1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX3245 • Rev. 1.6
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VCCA, VCCB Supply Voltage
-0.5
7.0
V
VCCA
+0.5
VIN
DC Input Voltage; (/OE, T/R¯ )
-0.5
-0.5
-0.5
V
V
VCCA to
+0.5
An
Bn
VI/O
DC Input / Output Voltage
VCCB to
+0.5
IIN
IOK
IO
DC Input Diode Current (/OE and T/R¯ )
DC Output Diode Current
±20
±50
mA
mA
mA
DC Output Source or Sink Current
±50
Output Pin
±50
ICC or IGND DC VCC or Ground Current
ICCA
ICCB
±100
±200
+150
±300
+150
mA
Maximum Current at
TSTG
ISINK
TJ
Storage Temperature Range
-65
°C
mA
°C
DC Latch-Up Source or Sink Current
Maximum Junction Temperature Under Bias
Electrostatic Discharge
ESD
Human Body Model, JESD22-A114
2500
V
Capability
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCCA
VCCB
VI
Parameter
Min.
Max.
Unit
2.7
4.5
0
3.6
5.5
Supply Voltage
V
V
V
Input Voltage (/OE and T/R¯ )
DC Input / Output Voltage
VCCA
VCCA
VCCB
+85
An
Bn
0
VI/O
0
TA
t / V
Note:
Operating Temperature, Free Air
-40
°C
Minimum Input Edge Rate (VIN from 30 to 70% of VCC, VCC at 3.0 V,
4.5 V, and 5.5 V)
8
ns/V
1. Unused pins (inputs and I/O’s) must be held HIGH or LOW. They may not float.
© 1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX3245 • Rev. 1.6
4
DC Electrical Characteristics
TA= -25°C
TA=-40 to+85°C
VCCA VCCB
Symbol
Parameter
Conditions
Unit
(V)
(V)
Typ.
Guaranteed Limits
3.6
2.7
3.3
3.3
3.6
2.7
3.3
3.3
3.0
3.0
2.7
2.7
3.0
3.0
3.0
3.0
2.7
2.7
3.0
3.0
5.0
5.0
4.5
5.5
5.0
5.0
4.5
5.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
2.0
2.0
2.0
2.0
An, T/R¯ ,
VIHA
VIHB
VILA
VILB
Minimum
HIGH Level
Input Voltage
/OE
Bn
VOUT 0.1 V or
VCC - 0.1 V
V
2.0
2.0
2.0
2.0
0.8
0.8
An, T/R¯ ,
/OE
Minimum
LOW Level
Input Voltage
0.8
0.8
VOUT 0.1 V or
VCC - 0.1 V
V
V
0.8
0.8
Bn
0.8
0.8
IOUT=-100 µA
IOH=-24 mA
IOH=-12 mA
IOH=-24 mA
IOUT=-100 µA
IOH=-24 mA
IOUT=100 µA
IOH=24 mA
IOH=12 mA
IOH=24 mA
IOUT=100 µA
IOH=24 mA
2.99
2.65
2.90
2.35
2.30
2.10
4.40
3.86
0.100
0.360
0.360
0.420
0.100
0.360
2.90
2.25
2.20
2.00
4.40
3.76
0.100
0.440
0.440
0.500
0.100
0.440
VOHA
VOHB
VOLA
2.50
Minimum HIGH Level
Output Voltage
2.30
4.50
4.25
0.002
0.210
0.110
0.220
0.002
0.180
Minimum LOW Level
Output Voltage
V
VOLB
Maximum Input
Leakage Current;
/OE, T/R¯
IIN
VIN=VCCB, GND
VIN=VIL, VIH;
/OE= VCCA;
VO=VCCA, GND
3.6
3.6
3.6
5.5
5.5
5.5
±0.1
±0.5
±0.5
±1.0
±5.0
±5.0
µA
µA
µA
Maximum 3-State
Output Leakage; An
IOZA
VIN=VIL, VIH;
/OE= VCCA;
VO=VCCB, GND
Maximum 3-State
Output Leakage; Bn
IOZB
Bn
VIN=VCCB-2.1 V
3.6
3.6
5.5
5.5
1.00
1.35
0.35
1.50
0.50
Maximum
ICCT/Input at
mA
ICC
An, T/R¯ ,
/OE
VIN=VCCA-0.6 V
An=VCCA or GND,
Quiescent VCCA Supply Bn=VCCB or GND,
ICCA
3.6
3.6
5.5
5.5
5
8
50
80
Current
/OE=GND,
T/R¯ =GND
µA
An=VCCA or GND,
Quiescent VCCB Supply Bn=VCCB or GND,
ICCB
Current
/OE=GND,
T/R¯ =VCCA
Continued on the following page…
© 1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX3245 • Rev. 1.6
5
DC Electrical Characteristics (Continued)
TA= -25°C
Typ.
TA=-40 to+85°C
VCCA VCCB
Symbol
Parameter
Conditions
Unit
(V)
(V)
Guaranteed Limits
VOLPA
VOLPB
VOLVA
VOLVB
VIHDA
3.3
3.3
3.3
3.3
3.3
5.0
5.0
5.0
5.0
5.0
0.8
1.5
Quiet Output Maximum
Dynamic VOL
V
V
(2, 3)
-0.8
-1.2
2.0
Quiet Output Minimum
(2, 3)
Dynamic VOL
Minimum HIGH Level
Dynamic Input
Voltage(2, 4)
V
V
VIHDB
VILDA
3.3
3.3
3.3
5.0
5.0
5.0
2.0
0.8
0.8
Maximum LOW Level
Dynamic Input
Voltage(2, 4)
VILDB
Notes:
2. Worst-case package.
3. Maximum number of outputs defined as (n). Data inputs are driven 0 V to VCC level; one output at GND.
4. Maximum number of data inputs (n) switching. (n-1) inputs switching 0 V to VCC level. Input-under-test switching;
VCC level to threshold (VIHD), 0V to threshold (VILD), f=1 MHz.
© 1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX3245 • Rev. 1.6
6
AC Electrical Characteristics
TA=-40 to +85°C,
CL=50 pF,
TA=-40 to +85°C,
CL=50 pF,
TA=+25°C, CL=50 pF,
VCCA=3.3 V(5),
VCCB=5.0 V(6)
VCCA=3.3 V(5),
VCCB=5.0 V(6)
VCCA=2.7 V,
VCCB=5.0 V
Symbol
Parameter
Unit
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.4
5.6
5.1
5.7
4.8
6.3
6.3
6.8
5.3
4.2
5.3
3.7
8.0
7.5
7.5
7.5
8.0
8.5
8.5
9.0
7.5
7.0
8.0
6.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.5
8.0
8.0
8.0
8.5
9.0
9.0
9.5
8.0
7.5
8.5
7.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
9.0
8.5
8.5
8.5
9.0
9.5
9.5
10.0
8.5
8.0
9.0
7.5
Propagation
Delay A to B
tPHL, tPLH
tPZL, tPZH
tPHZ, tPLZ
ns
ns
Propagation
Delay B to A
Output Enable
Time /OE to B
Output Enable
Time /OE to A
Output Disable
Time /OE to B
ns
ns
Output Disable
Time /OE to A
Output to Output
tOSHL, tOSLH Skew, Data to
1.0
1.5
1.5
1.5
Output(7)
Notes:
5. Voltage range 3.3 V is 3.3 V ± 0.3 V.
6. Voltage range 5.0 V is 5.0 V ± 0.5 V.
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Conditions
VCC = Open
Typ.
Unit
CIN
Input Capacitance
4.5
pF
VCCA = 3.3 V,
VCCB = 5.0 V
CI/O
CPD
Input / Output Capacitance
15
pF
pF
A to B
B to A
55
40
VCCA = 3.3 V,
VCCB = 5.0 V
Power Dissipation Capacitance(8)
Note:
8. CPD is measured at 10 MHz.
© 1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX3245 • Rev. 1.6
7
8-Bit Dual-Supply Translating Transceiver
The 74LVX3245 is a dual-supply device capable of bi-
directional signal translation. This level shifting ability
provides an efficient interface between low-voltage CPU
local bus with memory and a standard bus defined by
5 V I/O levels. The device control inputs can be
controlled by the low-voltage CPU and core logic or a
bus arbitrator with 5 V I/O levels.
Power-Up Considerations
To ensure that the system does not experience
unnecessary ICC current draw, bus contention, or
oscillations during power up; the following guidelines
should be followed to (refer to Table 2):
.
.
Power up the control side of the device first (VCCA).
Manufactured on a sub-micron CMOS process, the
74LVX3245 is ideal for mixed voltage applications such
as notebook computers using 3.3 V CPUs and 5 V
peripheral devices.
/OE should ramp with or ahead of VCCA. This helps
guard against bus contention.
.
The Transmit/Receive (T/R¯ ) control pin should
ramp with VCCA. This ensures that the A-port data
pins are configured as inputs. With VCCA receiving
power first, the I/O port should be configured as an
input to help guard against bus contention and
oscillations.
.
A-side data inputs should be driven to a valid logic
level. This prevents excessive current draw.
The above steps ensure that there are no bus
contentions or oscillations, and therefore no excessive
current draw occurs during the power-up cycling. These
steps help prevent possible damage to the translator
devices and potential damage to other system
components.
Figure 4.
Application Example
Table 2. Low Voltage Translator Power-Up Sequencing
Floatable
Pin Allowed
Device
VCCA
VCCB
T/R¯
/OE
A-Side I/O B-Side I/O
3 V
5 V
Ramp
Ramp
with VCCA
Logic 0 V or
Outputs
VCCA
74LVX3245
No
(Power-Up First) Configurable with VCCA
© 1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX3245 • Rev. 1.6
8
8.741
8.591
1.75
24
13
0.10
A-B
A
24
13
5.60
3.99
3.84
6
12
1
0.10
A-B
.635
0.4
1
12
0.20
C
2X 12 TIPS
0.635
B
24X
0.3
0.2
LAND PATTERN
RECOMMENDATION
0.178
C A-B D
TOP VIEW
1.49
1.39
(0.695)
0.71
0.61
ꢀꢁ
ꢂꢃꢁ
0.203
0.101
0.254
0.171
1.73 MAX
END VIEW
SIDE VIEW
0.25
0.50
0.25
0.50
R0.09 Min
GAGE
PLANE
NOTES :
0.254
A. THIS PACKAGE CONFORMS TO
JEDEC M0-137 VARIATION AE
ꢀꢀ
B. ALL DIMENSIONS ARE IN MILLIMETERS
0.020
SEATING PLANE
0.0295
C. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
0.039
D. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
DETAIL A
E. LAND PATTERN STANDARD: SOP63P600X175-24M.
F. DRAWING FILE NAME: MKT-MQA24rev3
7.8±0.1
A
0.20 TYP
13
24
13
24
B
1
12
0.65
12
1
0.20 C B A
0.10
C
0.65 TYP
0.10
C B Z
12° TOP & BOTTOM
R0.09MIN
0°-
8°
0.75
0.45
(1.00)
DATE 10/97.
DETAIL A
MTC24REV4
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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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相关型号：
74LVX3245MTC_NL
Bus Transceiver, LV/LV-A/LVX/H Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, 4.40 MM, LEAD FREE, MO-153, TSSOP-24
FAIRCHILD
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